Search results for "DRAM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Ping Chao, Youn-Long Lin	A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding.	ISCAS	2008	DBLP DOI BibTeX RDF
19	Xiangyu Dong, Xiaoxia Wu, Guangyu Sun 0003, Yuan Xie 0001, Hai Li 0001, Yiran Chen 0001	Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.	DAC	2008	DBLP DOI BibTeX RDF	3D stacking, MRAM
19	Richard Tran Mills, Chuan Yue, Andreas Stathopoulos, Dimitrios S. Nikolopoulos	Runtime and Programming Support for Memory Adaptation in Scientific Applications via Local Disk and Remote Memory.	J. Grid Comput.	2007	DBLP DOI BibTeX RDF	Shared computational pools, Network RAM, Scientific libraries, Autonomic computing, Memory management
19	Ivan Jureta, Stéphane Faulkner, Philippe Thiran	Dynamic Requirements Specification for Adaptable and Open Service-Oriented Systems.	ICSOC	2007	DBLP DOI BibTeX RDF
19	Eun-ki Kim, Hyungjong Shin, Byung-Gil Jeon, Seokhee Han, Jaemin Jung, Youjip Won	FRASH: Hierarchical File System for FRAM and Flash.	ICCSA (1)	2007	DBLP DOI BibTeX RDF	FRAM, NVRAM, Hierarchical Storage, Mounting Time, File System, NAND Flash Memory
19	Jung Ho Ahn, William J. Dally	Data parallel address architecture.	IEEE Comput. Archit. Lett.	2006	DBLP DOI BibTeX RDF
19	Yifeng Luo, Jiwu Shu, Bing Yu, Dongchan Wen	A Cache System Hosted on the iSCSI Target in an IP SAN.	GCC Workshops	2006	DBLP DOI BibTeX RDF
19	Ling Wu, Cheng Li 0005	Performance Analysis of Dynamic Reconfigurable Queues for High Speed Routers.	CCECE	2006	DBLP DOI BibTeX RDF
19	Wei Zhang 0012, Niraj K. Jha, Li Shang	NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture.	DAC	2006	DBLP DOI BibTeX RDF	NRAM, logic folding, run-time reconfiguration
19	Magnus Ekman, Per Stenström	A Cost-Effective Main Memory Organization for Future Servers.	IPDPS	2005	DBLP DOI BibTeX RDF
19	Nghi Nguyen, Angel Dominguez, Rajeev Barua	Memory allocation for embedded systems with a compile-time-unknown scratch-pad size.	CASES	2005	DBLP DOI BibTeX RDF	data linked list, downloadable codes, embedded loading, embedded systems, compiler, memory allocation, scratch-pad
19	Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem	Near-memory Caching for Improved Energy Consumption.	ICCD	2005	DBLP DOI BibTeX RDF
19	Sailesh Kumar, Jonathan S. Turner, Patrick Crowley	Addressing Queuing Bottlenecks at High Speeds.	Hot Interconnects	2005	DBLP DOI BibTeX RDF
19	Magnus Ekman, Per Stenström	A case for multi-level main memory.	WMPI	2004	DBLP DOI BibTeX RDF	memory-systems
19	Zaid Al-Ars, Ad J. van de Goor	Soft Faults and the Importance of Stresses in Memory Testing.	DATE	2004	DBLP DOI BibTeX RDF	stress application, Fault modeling, memory testing, defect simulation, soft faults
19	Yoonseo Choi, Taewhan Kim	Memory access driven storage assignment for variables in embedded system design.	ASP-DAC	2004	DBLP DOI BibTeX RDF
19	Mahmut T. Kandemir, Ozcan Ozturk 0001, Mary Jane Irwin, Ibrahim Kolcu	Using Data Compression to Increase Energy Savings in Multi-bank Memories.	Euro-Par	2004	DBLP DOI BibTeX RDF
19	Martin Ohmacht, Dirk Hoenicke, Ruud A. Haring, Alan Gara	The eDRAM based L3-Cache of the BlueGene/L Supercomputer Processor Node.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
19	Ganesan Umanesan, Eiji Fujiwara	A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Random multiple bits in a byte error, single t/b-error correcting—single b-bit byte error detecting (St/bEC-SbED) codes
19	Raju Rangaswami, Zoran Dimitrijevic, Edward Y. Chang, Klaus E. Schauser	MEMS-based Disk Buffer for Streaming Media Servers.	ICDE	2003	DBLP DOI BibTeX RDF
19	Sriram Ramabhadran, George Varghese	Efficient implementation of a statistics counter architecture.	SIGMETRICS	2003	DBLP DOI BibTeX RDF	statistics counter, router
19	Oren Avissar, Rajeev Barua, Dave Stewart	An optimal memory allocation scheme for scratch-pad-based embedded systems.	ACM Trans. Embed. Comput. Syst.	2002	DBLP DOI BibTeX RDF	embedded, Memory, heterogeneous, storage, allocation
19	Y. Chang, Minsu Choi, Nohpill Park, Fabrizio Lombardi	Repairability Evaluation of Embedded Multiple Region DRAMs.	DFT	2002	DBLP DOI BibTeX RDF
19	Krishna Kumar Rangan, Philip A. Wilsey, Nilesh Pisolkar, Nael B. Abu-Ghazaleh	PPIM-SIM: An Efficient Simulator for a Parallel Processor in Memory.	Annual Simulation Symposium	2001	DBLP DOI BibTeX RDF
19	Thomas L. Sterling	An Introduction to the Gilgamesh PIM Architecture.	Euro-Par	2001	DBLP DOI BibTeX RDF
19	Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob	Transparent data-memory organizations for digital signal processors.	CASES	2001	DBLP DOI BibTeX RDF
19	Oren Avissar, Rajeev Barua, Dave Stewart	Heterogeneous memory management for embedded systems.	CASES	2001	DBLP DOI BibTeX RDF	embedded, memory, heterogeneous, storage
19	Ethan L. Miller, Scott A. Brandt, Darrell D. E. Long	HeRMES: High-Performance Reliable MRAM-Enabled Storage.	HotOS	2001	DBLP DOI BibTeX RDF
19	Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle	Dynamic Access Ordering for Streamed Computations.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Memory systems architecture, memory access ordering, memory access scheduling, memory bandwidth, memory latency
19	Valerie Lines, Abdullah Ahmed, Peter Ma, Stanley Ma, Robert McKenzie, Hong-Seok Kim, Cynthia Mar	66MHz 2.3M Ternary Dynamic Content Addressable Memory.	MTDT	2000	DBLP DOI BibTeX RDF
19	Mark Oskin, Diana Keen, Justin Hensley, Lucian Vlad Lita, Frederic T. Chong	Reducing Cost and Tolerating Defects in Page-based Intelligent Memory.	ICCD	2000	DBLP DOI BibTeX RDF
19	Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai	BRAINS: A BIST Compiler for Embedded Memories.	DFT	2000	DBLP DOI BibTeX RDF
19	John Kibarian	Ramping New IC Products in the Deep Submicron Age.	ISQED	2000	DBLP DOI BibTeX RDF
19	Sung I. Hong, Sally A. McKee, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, William A. Wulf	Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory.	HPCA	1999	DBLP DOI BibTeX RDF
19	G. Jack Lipovski, Clement T. Yu	The Dynamic Associative Access Memory Chip and Its Application to SIMD Processing and Full-Text Database Retrieval.	MTDT	1999	DBLP DOI BibTeX RDF
19	Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Josep Torrellas, Pratap Pattnaik	FlexRAM: Toward an Advanced Intelligent Memory System.	ICCD	1999	DBLP DOI BibTeX RDF
19	Jörg E. Vollrath, Markus Huebl, Ernst Stahl	Power Analysis of DRAMs.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
19	Debaleena Das, Mark G. Karpovsky	Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	exhaustive codes, near-exhaustive codes, built-in self-test, memory testing, pattern sensitive faults
19	John J. Fallin	The iRAM: an innovative approach to microprocessor memory solutions.	AFIPS National Computer Conference	1983	DBLP DOI BibTeX RDF
16	Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt	Prefetch-Aware Memory Controllers.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	prefetching, DRAM, Memory systems, memory controllers, multi-core systems
16	Benjamin C. Lee, Ping Zhou, Jun Yang 0002, Youtao Zhang, Bo Zhao 0007, Engin Ipek, Onur Mutlu, Doug Burger	Phase-Change Technology and the Future of Main Memory.	IEEE Micro	2010	DBLP DOI BibTeX RDF	energy efficiency, memory architecture, DRAM, technology scaling, phase-change memory, PCM
16	Dong Kim, Kwanhu Bang, Seung-Hwan Ha, Sungroh Yoon, Eui-Young Chung	Architecture Exploration of High-Performance PCs with a Solid-State Disk.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	dual-port DRAM, North Bridge, direct path, NAND flash memory, Solid-State Disk (SSD)
16	Paul Vincent Mejia, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella	Performance Evaluation of a Multicore System with Optically Connected Memory Modules.	NOCS	2010	DBLP DOI BibTeX RDF	OC-DIMM, DWDM, Performance Evaluation, DRAM, Optics
16	Mohd Wajid, S. B. Shashank	Architecture for Faster RAM Controller Design with Inbuilt Memory.	CICSyN	2010	DBLP DOI BibTeX RDF	FPGA, VLSI, Memory, DRAM
16	Wei Zhang 0032, Ki Chul Chun, Chris H. Kim	Variation aware performance analysis of gain cell embedded DRAMs.	ISLPED	2010	DBLP DOI BibTeX RDF	bitline delay, gain cell, process variation, monte carlo simulation, embedded DRAM
16	Howard David, Eugene Gorbatov, Ulf R. Hanebutte, Rahul Khanna, Christian Le	RAPL: memory power estimation and capping.	ISLPED	2010	DBLP DOI BibTeX RDF	measurements, power, DRAM memory
16	Yossi Azar, Uriel Feige, Iftah Gamzu, Thomas Moscibroda, Prasad Raghavendra	Buffer management for colored packets with deadlines.	SPAA	2009	DBLP DOI BibTeX RDF	dram scheduling, online algorithms, buffer management, packets scheduling, earliest deadline first
16	Ozcan Ozturk 0001, Mahmut T. Kandemir	ILP-Based energy minimization techniques for banked memories.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low-power operating modes, compilers, data compression, replication, migration, DRAM, Memory banking
16	Kiyoo Itoh 0001, Masanao Yamaoka, Takayuki Kawahara	Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FD-SOI, VT variation, bulk, deep-sub-100-nm CMOS LSIs, minimum VDD, speed variation, leakage, SRAM, DRAM, logic gate
16	Christophe Lécuyer, David C. Brock	Biographies.	IEEE Ann. Hist. Comput.	2006	DBLP DOI BibTeX RDF	Gordon Moore, semiconductor industry, silicon technology, silicon device manufacture, Fairchild Semiconductor, Shockley Semiconductor, microprocessor, integrated circuit, DRAM, personal computer, chemistry, Moore's law, Intel
16	Annie (Yujuan) Zeng, James (JianQiang) Lü, Kenneth Rose, Ronald J. Gutmann	First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	wafer-level 3D integration, SRAM, DRAM, cache performance, Access time, cycle time
16	Christianto C. Liu, Ilya Ganusov, Martin Burtscher, Sandip Tiwari	Bridging the Processor-Memory Performance Gapwith 3D IC Technology.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	three-dimensional integration 3-D ICs microprocessor cache design stream prefetching embedded DRAM
16	Ozcan Ozturk 0001, Mahmut T. Kandemir	Integer linear programming based energy optimization for banked DRAMs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low-power, data compression, DRAM, ILP, data migration, memory banking
16	Jayaprakash Pisharath, Alok N. Choudhary, Mahmut T. Kandemir	Energy management schemes for memory-resident database systems.	CIKM	2004	DBLP DOI BibTeX RDF	hardware energy scheme, multiquery optimization, query-directed energy management, database, energy, power consumption, DRAM
16	Jayaprakash Pisharath, Alok N. Choudhary, Mahmut T. Kandemir	Reducing energy consumption of queries in memory-resident database systems.	CASES	2004	DBLP DOI BibTeX RDF	hardware schemes, query-directed energy management, database, mapping, query optimization, energy, power consumption, layouts, DRAM
16	Diana Keen, Mark Oskin, Justin Hensley, Frederic T. Chong	Cache Coherence in Intelligent Memory Systems.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Intelligent memory, merged DRAM logic, cache coherence
16	Jörg E. Vollrath	Output Timing Measurement Using an Idd Method.	MTDT	2003	DBLP DOI BibTeX RDF	DDR, timing, DRAM
16	Jörg E. Vollrath	Signal Margin Analysis for Memory Sense Amplifiers .	DELTA	2002	DBLP DOI BibTeX RDF	Signal margin, Test, Memory, Diagnosis, DRAM
16	Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter	A Memory Specific Notation for Fault Modeling.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	memory specific fault analysis, memory testing, DRAM, functional fault models, fault primitives
16	Zemo Yang, Samiha Mourad	Crosstalk in Deep Submicron DRAMs.	MTDT	2000	DBLP DOI BibTeX RDF	Noise and Submicron, Crosstalk, DRAM
16	J. Bruce Millar, Peter Gillingham	Two High-Bandwidth Memory Bus Structures.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF	SLDRAM, Direct Rambus, DRAM, memory design
16	David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor	Evaluation of Computing in Memory Architectures for Digital Image Processing Applications.	ICCD	1999	DBLP DOI BibTeX RDF	Computing In Memory, FPGA, Image Processing, Parallel Processing, Multiprocessor, System-On-A-Chip, DRAM
16	Stephen J. Walsh, John A. Board	Pollution control caching.	ICCD	1995	DBLP DOI BibTeX RDF	pollution control caching, high speed processors, bandwidth mismatch, standard DRAMS, on-chip caches, miss ratio statistics, expected clock cycles per instruction, main memory latencies, PCC+VB, discrete event simulation, memory architecture, trace driven simulation, cache storage, memory performance, ANOVA, DRAM chips
16	Manoj Franklin, Kewal K. Saluja	Hypergraph Coloring and Reconfigured RAM Testing.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	hypergraph coloring, reconfigured RAM testing, RAM decoders, critical path lengths, memory chips, physical neighborhood pattern sensitive faults, reconfigured DRAMs, decoder faults, computational complexity, logic testing, redundancy, reconfigurable architectures, stuck-at faults, graph colouring, random-access storage, integrated memory circuits, test lengths, test algorithms, DRAM chips, silicon area
16	Charles H. Stapper	Improved Yield Models for Fault-Tolerant Memory Chips.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	fault-tolerant memory chips, defect-monitor data, redundant circuits, failure mechanisms, multivariate distributions, dynamic-random-access-memory, pragmatic approximation, fault tolerant computing, redundancy, DRAM chips, yield modeling, frequency distributions
16	Charles H. Stapper, Hsing-San Lee	Synergistic Fault-Tolerance for Memory Chips.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	bitline redundancy, memory chips, synergistic fault tolerance, VLSI memory chip, redundant circuits, wordline redundancy, fault-tolerance synergism, VLSI, fault tolerant computing, error-correcting codes, error correction codes, error-correction, DRAM chips
13	Leonid Yavits	DRAMA: Commodity DRAM Based Content Addressable Memory.	IEEE Comput. Archit. Lett.	2024	DBLP DOI BibTeX RDF
13	Zuher Jahshan, Leonid Yavits	MajorK: Majority Based kmer Matching in Commodity DRAM.	IEEE Comput. Archit. Lett.	2024	DBLP DOI BibTeX RDF
13	H. D. Kallinatha, Sadhana Rai, Basavaraj Talawar	A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment.	IEEE Access	2024	DBLP DOI BibTeX RDF
13	Jun Hui Park, Jung Nam Kim, Seonhaeng Lee, Gang-Jun Kim, Namhyun Lee, Rock-Hyun Baek, Dae Hwan Kim, Changhyun Kim, Myounggon Kang, Yoon Kim	Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning.	IEEE Access	2024	DBLP DOI BibTeX RDF
13	Hyunseo You, Kihoon Nam, Jehyun An, Chanyang Park, Donghyun Kim, Seonhaeng Lee, Namhyun Lee, Rock-Hyun Baek	Cryogenic Body Bias Effect in DRAM Peripheral and Buried-Channel-Array Transistor for Quantum Computing Applications.	IEEE Access	2024	DBLP DOI BibTeX RDF
13	João Vieira, Nuno Roma, Gabriel Falcão 0001, Pedro Tomás	NDPmulator: Enabling Full-System Simulation for Near-Data Accelerators From Caches to DRAM.	IEEE Access	2024	DBLP DOI BibTeX RDF
13	Wenqi Wang, Sang Don Yi, Fu Li, Qingchen Cao, Jiangliu Shi, Bok-Moon Kang, Meichen Jin, Chang Liu, Zhenhua Wu, Guilei Wang, Chao Zhao	Vertical Surrounding Gate Transistor for High Density and Low Voltage Operation in DRAM.	IEEE Access	2024	DBLP DOI BibTeX RDF
13	Sangjin Kim, Hoi-Jun Yoo	An Overview of Computing-in-Memory Circuits With DRAM and NVM.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
13	Irina Alam, Puneet Gupta 0001	Achieving DRAM-Like PCM by Trading Off Capacity for Latency.	IEEE Trans. Computers	2024	DBLP DOI BibTeX RDF
13	Junpeng Wang, Mengke Ge, Bo Ding, Qi Xu, Song Chen 0001, Yi Kang	NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators With 3-D Stacked-DRAM.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
13	Shailja Pandey, Lokesh Siddhu, Preeti Ranjan Panda	NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching.	ACM Trans. Design Autom. Electr. Syst.	2024	DBLP DOI BibTeX RDF
13	Mike Hamburg, Eric Linstadt, Danny Moore, Thomas Vogelsang	Unraveling codes: fast, robust, beyond-bound error correction for DRAM.	CoRR	2024	DBLP DOI BibTeX RDF
13	Jeongmin Hong, Sungjun Cho, Geonwoo Park, Wonhyuk Yang, Young-Ho Gong, Gwangsun Kim	Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory.	CoRR	2024	DBLP DOI BibTeX RDF
13	Abdullah Giray Yaglikçi, Yahya Can Tugrul, Geraldo F. Oliveira, Ismail Emir Yüksel, Ataberk Olgun, Haocong Luo, Onur Mutlu	Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions.	CoRR	2024	DBLP DOI BibTeX RDF
13	Geraldo F. Oliveira, Ataberk Olgun, Abdullah Giray Yaglikçi, F. Nisa Bostanci, Juan Gómez-Luna, Saugata Ghose, Onur Mutlu	MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing.	CoRR	2024	DBLP DOI BibTeX RDF
13	Antonio Savino, Gautam Gala, Marcello Cinque, Gerhard Fohler	Multicore DRAM Bank-& Row-Conflict Bomb for Timing Attacks in Mixed-Criticality Systems.	CoRR	2024	DBLP DOI BibTeX RDF
13	Minesh Patel, Taha Shahroodi, Aditya Manglik, Abdullah Giray Yaglikçi, Ataberk Olgun, Haocong Luo, Onur Mutlu	Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems.	CoRR	2024	DBLP DOI BibTeX RDF
13	Ismail Emir Yuksel, Yahya Can Tugrul, Ataberk Olgun, F. Nisa Bostanci, Abdullah Giray Yaglikçi, Geraldo F. Oliveira, Haocong Luo, Juan Gómez-Luna, Mohammad Sadrosadati, Onur Mutlu	Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis.	CoRR	2024	DBLP DOI BibTeX RDF
13	Enas E. Abulibdeh, Leen Younes, Baker Mohammad, Khaled Humood, Hani H. Saleh, Mahmoud Al-Qutayri	DRAM-Based PUF Utilizing the Variation of Adjacent Cells.	IEEE Trans. Inf. Forensics Secur.	2024	DBLP DOI BibTeX RDF
13	Yunhong Ji, Wentao Huang, Xuan Zhou	HeterMM: applying in-DRAM index to heterogeneous memory-based key-value stores.	Frontiers Comput. Sci.	2024	DBLP DOI BibTeX RDF
13	Abdullah Giray Yaglikçi, Yahya Can Tugrul, Geraldo F. Oliveira, Ismail Emir Yüksel, Ataberk Olgun, Haocong Luo, Onur Mutlu	Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions.	HPCA	2024	DBLP DOI BibTeX RDF
13	Jaeyoon Lee, Wonyeong Jung, Dongwhee Kim, Daero Kim, Junseung Lee, Jungrae Kim	Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers.	HPCA	2024	DBLP DOI BibTeX RDF
13	Geraldo F. Oliveira, Ataberk Olgun, Abdullah Giray Yaglikçi, F. Nisa Bostanci, Juan Gómez-Luna, Saugata Ghose, Onur Mutlu	MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing.	HPCA	2024	DBLP DOI BibTeX RDF
13	Ismail Emir Yüksel, Yahya Can Tugrul, Ataberk Olgun, F. Nisa Bostanci, Abdullah Giray Yaglikçi, Geraldo F. Oliveira, Haocong Luo, Juan Gómez-Luna, Mohammad Sadrosadati, Onur Mutlu	Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis.	HPCA	2024	DBLP DOI BibTeX RDF
13	Jeongmin Hong, Sungjun Cho, Geonwoo Park, Wonhyuk Yang, Young-Ho Gong, Gwangsun Kim	Bandwidth-Effective DRAM Cache for GPU s with Storage-Class Memory.	HPCA	2024	DBLP DOI BibTeX RDF
13	Yubo Liu, Yuxin Ren 0001, Mingrui Liu, Hongbo Li, Hanjun Guo, Xie Miao, Xinwei Hu, Haibo Chen 0001	Optimizing File Systems on Heterogeneous Memory by Integrating DRAM Cache with Virtual Memory Management.	FAST	2024	DBLP BibTeX RDF
13	Tae Eun Jang, Kyu Hyun Lee, Gi Yeol Kim, Su Yeon Yun, Da-Hyeon Youn, Hyunggu Choi, Jihyang Kim, Soo Youn Kim, Minkyu Song	Compute-in-Memory with SAR ADC and 2T1C DRAM for MAC Operations.	ICEIC	2024	DBLP DOI BibTeX RDF
13	Ho-Sung Lee, Joo-Hyung Chae	A 1-Kb 6T 1C XNOR-DRAM Compute-In-Memory Macro With Signed Bit Adder Block for CNN Operations.	ICEIC	2024	DBLP DOI BibTeX RDF
13	Junil Kim, Seok Young Kim, Seon Wook Kim	Supporting Multi-Channels to DRAM-based PIM Execution for Boosting the Performance.	ICEIC	2024	DBLP DOI BibTeX RDF
13	Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sanghoon Kim, Daewoong Lee, Seongyeal Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gun-hee Cho, ChanYong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hong-Jun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, TaeHoon Park, Tae-Young Oh, Changsik Yoo, SangJoon Hwang	13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration.	ISSCC	2024	DBLP DOI BibTeX RDF
13	IkJoon Choi, Seunghwan Hong, Kihyun Kim, Jeongsik Hwang, Seunghan Woo, Young-Sang Kim, Cheongryong Cho, Eun-Young Lee, Hun-Jae Lee, Min-Su Jung, Hee-Yun Jung, Ju-Seong Hwang, Junsub Yoon, Wonmook Lim, Hyeong-Jin Yoo, Won-Ki Lee, Jung-Kyun Oh, Dong-Su Lee, Jong-Eun Lee, Jun-Hyung Kim, Young-Kwan Kim, Su-Jin Park, Byung-Kyu Ho, Byongwook Na, Hye-In Choi, Chung-Ki Lee, Soo-Jung Lee, Hyunsung Shin, Young-Kyu Lee, Jang-Woo Ryu, Sangwoong Shin, Sungchul Park, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, SangJoon Hwang	13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Jinhyung Lee, Kyungjun Cho, Chang Kwon Lee, Yeonho Lee 0002, Jae-Hyung Park, Su-Hyun Oh, Yucheon Ju, Chunseok Jeong, Ho Sung Cho, Jaeseung Lee, Tae-Sik Yun, Jin Hee Cho, Sangmuk Oh, Junil Moon, Young-Jun Park, Hong-Seok Choi, In-Keun Kim, Seung Min Yang, Sun-Yeol Kim, Jaemin Jang, Jinwook Kim, Seong-Hee Lee, Younghyun Jeon, Juhyung Park, Tae-Kyun Kim, Dongyoon Ka, Sanghoon Oh, Jinse Kim, Junyeol Jeon, Seonhong Kim, Kyeong Tae Kim, Taeho Kim, Hyeonjin Yang, Dongju Yang, Minseop Lee, Heewoong Song, Dongwook Jang, Junghyun Shin, Hyunsik Kim, Chang-Ki Baek, Hajun Jeong, Jongchan Yoon, Seung-Kyun Lim, Kyo Yun Lee, Young Jun Koo, Myeong-Jae Park, Joohwan Cho, Jonghwan Kim	13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Yangho Seo, Jihee Choi, Sunki Cho, Hyunwook Han, Wonjong Kim, Gyeongha Ryu, Jungil Ahn, Younga Cho, Sungphil Choi, Seohee Lee, Wooju Lee, Chaehyuk Lee, Kiup Kim, Seongseop Lee, Sangbeom Park, Minjun Choi, Sungwoo Lee, Mino Kim, Taekyun Shin, Hyeongsoo Jeong, Hyunseung Kim, Houk Song, Yunsuk Hong, Seokju Yoon, Giwook Park, Hokeun You, Changkyu Choi, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim	13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Xingsheng Zhao, Prajwal Challa, Chen Zhong, Song Jiang 0001	Developing Index Structures in Persistent Memory Using Spot-on Optimizations with DRAM.	ICPE	2024	DBLP DOI BibTeX RDF