Search results for "FinFET"

Hits ?▲	Authors	Title	Venue	Year	Link
14	B. Jeevan, Kosaraju Sivani	Design of 0.8V, 22 nm DG-FinFET based efficient VLSI multiplexers.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
14		Analysing digital in-memory computing for advanced finFET node.	CoRR	2021	DBLP BibTeX RDF
14	Sourav De, Yao-Jen Lee, Darsen D. Lu	Alleviation of Temperature Variation Induced Accuracy Degradation in Ferroelectric FinFET Based Neural Network.	CoRR	2021	DBLP BibTeX RDF
14	Sourav De, Bo-Han Qiu, Wei-Xuan Bu, Md. Aftab Baig, Chung-Jun Su, Yao-Jen Lee, Darsen D. Lu	Neuromorphic Computing with Deeply Scaled Ferroelectric FinFET in Presence of Process Variation, Device Aging and Flicker Noise.	CoRR	2021	DBLP BibTeX RDF
14	N. Duraivel, Paulchamy Balaiyah	Simulation and performance analysis of 15 Nm FinFET based carry skip adder.	Comput. Intell.	2021	DBLP DOI BibTeX RDF
14	Hung-Chi Han, Farzan Jazaeri, Antonio A. D'Amico, Andrea Baschirotto, Edoardo Charbon, Christian C. Enz	Cryogenic Characterization of 16 nm FinFET Technology for Quantum Computing.	ESSDERC	2021	DBLP DOI BibTeX RDF
14	Asma Chabane, Mridula Prathapan, Peter Mueller, Eunjung Cha, Pier Andrea Francese, Marcel A. Kossel, Thomas Morf, Cezar B. Zota	Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology.	ESSDERC	2021	DBLP DOI BibTeX RDF
14	Alexandra Feeley, Yoni Xiong, Bharat L. Bhuva, Balaji Narasimham, Shi-Ji Wen, Rita Fung	Effects of Temperature and Supply Voltage on Soft Errors for 7-nm Bulk FinFET Technology.	IRPS	2021	DBLP DOI BibTeX RDF
14	Hai Jiang 0005, Jinju Kim, Kihyun Choi, Hyewon Shim, Hyunchul Sagong, Junekyun Park, Hwasung Rhee, Euncheol Lee	Time Dependent Variability in Advanced FinFET Technology for End-of-Lifetime Reliability Prediction.	IRPS	2021	DBLP DOI BibTeX RDF
14	Maria Toledano-Luque, Peter C. Paliwoda, Mohamed Nour, Thomas Kauerauf, Byoung Min, Germain Bossu, Mahesh Siddabathula, Tanya Nigam	Off-state TDDB in FinFET Technology and its Implication for Safe Operating Area.	IRPS	2021	DBLP DOI BibTeX RDF
14	Rakesh Ranjan, Ki-Don Lee, Md Iqbal Mahmud, Mohammad Shahriar Rahman, Pavitra Ramadevi Perepa, Charles Briscoe LaRow, Caleb Dongkyun Kwon, Maihan Nguyen, Minhyo Kang, Ashish Kumar Jha, Ahmed Shariq, Shamas Musthafa Ummer, Susannah Laure Prater, Hyunchul Sagong, HwaSung Rhee	Systematic Study of Process Impact on FinFET Reliability.	IRPS	2021	DBLP DOI BibTeX RDF
14	Balaji Narasimham, Vikas Chaudhary, Mike Smith, Liming Tsau, Dennis R. Ball, Bharat L. Bhuva	Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5-nm FinFET.	IRPS	2021	DBLP DOI BibTeX RDF
14	M. Monishmurali, Mayank Shrivastava	A Novel High Voltage Drain Extended FinFET SCR for SoC Applications.	IRPS	2021	DBLP DOI BibTeX RDF
14	Taiki Uemura, Byungjin Chung, Jeongmin Jo, Mijoung Kim, Dalhee Lee, Gunrae Kim, Seungbae Lee, Taesjoong Song, Hwasung Rhee, Brandon Lee, Jaehee Choi	Soft-Error Susceptibility in Flip-Flop in EUV 7 nm Bulk-FinFET Technology.	IRPS	2021	DBLP DOI BibTeX RDF
14	Gerhard Rzepa, Markus Karner, Oskar Baumgartner, Georg Strof, Franz Schanovsky, Ferdinand Mitterbauer, Christian Kernstock, Hui-Wen Karner, Pieter Weckx, Geert Hellings, Dieter Claes, Zhicheng Wu, Yang Xiang, Thomas Chiarella, Bertrand Parvais, Jérôme Mitard, Jacopo Franco, Ben Kaczer, Dimitri Linten, Zlatan Stanojevic	Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies.	IRPS	2021	DBLP DOI BibTeX RDF
14	Dhananjaya Tripathy, Debiprasad Priyabrata Acharya, Prakash Kumar Rout, Debasish Nayak	The impact of GATE thickness variation on FinFET performance parameters.	OCIT	2021	DBLP DOI BibTeX RDF
14	G. Cardoso Medeiros, Moritz Fieback, Anteneh Gebregiorgis, Mottaqiallah Taouil, Leticia Bolzani Poehls, Said Hamdioui	Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs.	ETS	2021	DBLP DOI BibTeX RDF
14	Maria Eduarda de Melo Hang, Cleiton Magano Marques, Paulo F. Butzen, Cristina Meinhardt	Soft Error Sensibility Window at FinFET DICE SRAM.	LASCAS	2021	DBLP DOI BibTeX RDF
14	Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis 0001	Current Behavior on Process Variability Aware FinFET Inverter Designs.	LASCAS	2021	DBLP DOI BibTeX RDF
14	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Fernanda Lima Kastensmidt, Cristina Meinhardt, Ricardo A. L. Reis	Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit.	LASCAS	2021	DBLP DOI BibTeX RDF
14	Takamoto Watanabe	All-Digital VCO-ADC TAD Confirming Scaling and Stochastic Effects Using 16-nm FinFET CMOS.	ICECS	2021	DBLP DOI BibTeX RDF
14	Alessio Di Pasquo, Enrico Monaco, Claudio Nani, Luca Fanucci	Delay-lines jitter modeling and efficiency analysis in FinFET technology.	ICECS	2021	DBLP DOI BibTeX RDF
14	Takamoto Watanabe	All-Digital VCO-ADC TAD Using 4CKES-Type in 16-nm FinFET CMOS for Technology Scaling With Stochastic-ADC Method.	ICECS	2021	DBLP DOI BibTeX RDF
14	Zixiang Wan, Xinyu Xu, Woogeun Rhee, Zhihua Wang 0001	A 0.0048mm2 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS.	ICTA	2021	DBLP DOI BibTeX RDF
14	Hung-Chi Han, Farzan Jazaeri, Antonio A. D'Amico, Andrea Baschirotto, Edoardo Charbon, Christian C. Enz	Cryogenic Characterization of 16 nm FinFET Technology for Quantum Computing.	ESSCIRC	2021	DBLP DOI BibTeX RDF
14	Abraham Gonzalez, Jerry Zhao, Ben Korpan, Hasan Genc, Colin Schmidt 0001, John Charles Wright, Ayan Biswas, Alon Amid, Farhana Sheikh, Anton Sorokin, Sirisha Kale, Mani Yalamanchi, Ramya Yarlagadda, Mark Flannigan, Larry Abramowitz, Elad Alon, Yakun Sophia Shao, Krste Asanovic, Borivoje Nikolic	A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET.	ESSCIRC	2021	DBLP DOI BibTeX RDF
14	Asma Chabane, Mridula Prathapan, Peter Mueller, Eunjung Cha, Pier Andrea Francese, Marcel A. Kossel, Thomas Morf, Cezar B. Zota	Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology.	ESSCIRC	2021	DBLP DOI BibTeX RDF
14	Euhan Chong, Faisal Ahmed Musa, Ahmed N. Mustafa, Tim Gao, Peter Krotnev, Rashid Soreefan, Qian Xin, Paul Madeira, Davide Tonietto	A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET.	ESSCIRC	2021	DBLP DOI BibTeX RDF
14	Ping Lu	A 25.6-27.5GHz Phase-Locked Loop for SerDes Transceiver Clocking in 5nm FinFET.	NorCAS	2021	DBLP DOI BibTeX RDF
14	Tamer A. Ali 0001, Mohammed Abdullatif, Henry Park, Ehung Chen, Ramy Awad, Miguel Gandara	56/112Gbps Wireline Transceivers for Next Generation Data Centers on 7nm FINFET CMOS Technology.	CICC	2021	DBLP DOI BibTeX RDF
14	Hao Luo, Somnath Kundu, Chun C. Lee, Rinkle Jain, Sarah Shahraini, Eduardo Alban, Timo Huusari, Jason Mix, Nasser A. Kurd, Mohamed Abdel-moneum, Brent R. Carlton	A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS.	CICC	2021	DBLP DOI BibTeX RDF
14	Chester Liu, Jacob Botimer, Zhengya Zhang	A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer.	CICC	2021	DBLP DOI BibTeX RDF
14	Colin Schmidt 0001, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woo-Rham Bae, Sean Huang, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic	4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET.	ISSCC	2021	DBLP DOI BibTeX RDF
14	Dongseok Shin, Hyung Seok Kim, Chuanchang Liu, Priya Wali, Savyasaachi Keshava Murthy, Yongping Fan	11.5 A 23.9-to-29.4GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET.	ISSCC	2021	DBLP DOI BibTeX RDF
14	James Bailey 0002, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan	A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver.	ISSCC	2021	DBLP DOI BibTeX RDF
14	Dong-Hoon Jung, Tae-Hwang Kong, Jun-Hyeok Yang, SangHo Kim, Kwangho Kim, Jeongpyo Park, Michael Choi, Jongshin Shin	29.6 A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS.	ISSCC	2021	DBLP DOI BibTeX RDF
14	Seung-Yeob Baek 0002, Il-Hoon Jang, Michael Choi, Hyungdong Roh, Woongtaek Lim, Youngjae Cho, Jongshin Shin	A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET.	ISSCC	2021	DBLP DOI BibTeX RDF
14	Alexander Fritsch, Rajiv V. Joshi, Sudipto Chakraborty, Holger Wetter, Uma Srinivasan 0002, Matthew Hyde, Otto A. Torreiter, Michael Kugel, Dan Radko, Hyong Kim, Daniel J. Friedman	24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology.	ISSCC	2021	DBLP DOI BibTeX RDF
14	Jongsoo Lee, Byoungjoong Kang, Seongwon Joo, Seokwon Lee, Joongho Lee, Seunghoon Kang, Ikkyun Jo, Suseop Ahn, Jaeseung Lee, Jeongyeol Bae, Won Ko, Woniun Jung, Sangho Lee, Sangsung Lee, Euiyoung Park, Sungiun Lee, Jeongkyun Woo, Jaehoon Lee 0005, Yanghoon Lee, Kyungmin Lee, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang	6.1 A Low-Power and Low-Cost 14nm FinFET RFIC Supporting Legacy Cellular and 5G FR1.	ISSCC	2021	DBLP DOI BibTeX RDF
14	Edwin Thaller, Run Levinger, Evgeny Shumaker, Aryeh Farber, Sergey Bershansky, Nir Geron, Ashoke Ravi, Rotem Banin, Jasmin Kadry, Gil Horovitz, Christian Krassnitzer, Christoph Duller, Patrick Torta, Mark Elzinga, Kamran Azadet	A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS.	ISSCC	2021	DBLP DOI BibTeX RDF
14	Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Kamran Azadet	10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET.	ISSCC	2021	DBLP DOI BibTeX RDF
14	Ramy Yousry, Ehung Chen, Yu-Ming Ying, Mohammed Abdullatif, Mohammad Elbadry, Ahmed ElShater, Tsz-Bin Liu, Joonyeong Lee, Dhinessh Ramachandran, Kaiz Wang, Chih-Hao Weng, Mau-Lin Wu, Tamer A. Ali 0001	11.1 A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET Technology.	ISSCC	2021	DBLP DOI BibTeX RDF
14	Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Qiao Wang, Haijun Jiang, Jie Yu 0027, Danian Dong, Feng Zhang 0014, Hangbing Lv, Ming Liu 0022	24.2 A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µ m2 Cell Size Using Self-Adaptive Delayed Termination and Multi-Cell Reference.	ISSCC	2021	DBLP DOI BibTeX RDF
14	Jong-Seok Park, Sushil Subramanian, Lester Lampert, Todor Mladenov, Ilya Klotchkov, Dileep Kurian, Esdras Juárez-Hernández, Brando Perez Esparza, Sirisha Rani Kale, K. T. Asma Beevi, Shavindra P. Premaratne, Thomas Watson 0006, Satoshi Suzuki, Mustafijur Rahman, Jaykant Timbadiya, Saksham Soni, Stefano Pellerano	A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology.	ISSCC	2021	DBLP DOI BibTeX RDF
14	P. Mishra, A. Tan, Belal Helal, Cheng-Ru Ho, C. Loi, Jamal Riani, J. Sun, Kaizad Mistry, Karthik Raviprakash, L. Tse, M. Davoodi, M. Takefman, N. Fan, P. Prabha, Q. Liu, Q. Wang, Rajasekhar Nagulapalli, S. Cyrusian, S. Jantzi, S. Scouten, T. Dusatko, T. Setya, V. Giridharan, V. Gurumoorthy, Victor Karam, W. Liew, Y. Liao, Y. Ou	8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET.	ISSCC	2021	DBLP DOI BibTeX RDF
14	Bo-Jr Huang, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Rory Huang, Angus Lin, Chi-Hsun Chiang, Yi-Hsuan Lin, Wen-Wen Hsieh, Barry Chen, Yi-Chang Zhuang, Cheng-Yuh Wu, Jia-Ming Chen, Y. S. Chen, Cheng-Tien Wan, Ericbill Wang, Alex Chiou, Ping Kao, Yuwen Tsai, Harry H. Chen, Shih-Arn Hwang	35.1 An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoC.	ISSCC	2021	DBLP DOI BibTeX RDF
14	Thierry Tambe, En-Yu Yang, Glenn G. Ko, Yuji Chai, Coleman Hooper, Marco Donato, Paul N. Whatmough, Alexander M. Rush, David Brooks 0001, Gu-Yeon Wei	9.8 A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET.	ISSCC	2021	DBLP DOI BibTeX RDF
14	R. L. Nguyen, A. M. Castrillon, A. Fan, A. Mellati, Benjamín T. Reyes, Cindra Abidin, E. Olsen, F. Ahmad, Geoff Hatcher, J. Chana, Laura Biolato, L. Tse, L. Wang, M. Azarmnia, M. Davoodi, N. Campos, N. Fan, P. Prabha, Q. Lu, S. Cyrusian, S. Dallaire, S. Ho, S. Jantzi, T. Dusatko, W. Elsharkasy	8.6 A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and Sub-35fJ/conv-step for 400Gb/s Coherent Optical Applications in 7nm FinFET.	ISSCC	2021	DBLP DOI BibTeX RDF
14	Tsung-Che Lu, Chin-Ming Fu, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, Kenny Hsieh	A Cost-Effective On-Chip Power Impedance Measurement (PIM) System in 7nm FinFET for HPC Applications.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
14	Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang 0003, Ying Cao 0010, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans	A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
14	Suhwan Kim, Harish Krishnamurthy, Sally Amin, Sheldon Weng, Jin Feng, Huong Do, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De	A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
14	Hassan Sepehrian, Stephen Alie, Paul Madeira, Davide Tonietto	106 Gb/s PAM-4 Transmitter With 2.1 Vppd Swing in 7nm FinFET Process.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
14	Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish	Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET.	ISCAS	2021	DBLP DOI BibTeX RDF
14	Jieyu Li, Zihan Lian, Hao Zhang, Weifeng He, Yanan Sun 0003, Mingoo Seok	Investigation of Dynamic Leakage-Suppression Logic Techniques Crossing Different Technology Nodes from 180 nm Bulk CMOS to 7 nm FinFET Plus Process.	ISCAS	2021	DBLP DOI BibTeX RDF
14	Kai Sheng, Linqi Shi, Weixin Gai, Qianting Hua, Peng Lin	A 2-Bit 4-Level 4-Wire 56Gb/s Transceiver in 14nm FinFET.	ISCAS	2021	DBLP DOI BibTeX RDF
14	Qiao Cai, Yuxin Ji, Ce Ma, Xiaocui Li, Ting Zhou, Jian Zhao 0004, Yongfu Li 0002	An Ultra-Low-Voltage Energy-Efficient Dynamic Fully-Regenerative Latch-Based Level-Shifter Circuit with Tunnel-FET & FinFET Devices.	ISCAS	2021	DBLP DOI BibTeX RDF
14	Mehrnaz Ahmadi, Lihong Zhang	Analog Layout Placement for FinFET Technology Using Reinforcement Learning.	ISCAS	2021	DBLP DOI BibTeX RDF
14	Matthias Eberlein, Harald Pretl	A Current-Mode Temperature Sensor with a ±1.56 °C Raw Error and Duty-Cycle Output in 16nm FinFET.	ISCAS	2021	DBLP DOI BibTeX RDF
14	Nan-Hsiung Tseng, Bo-Kuan Wu, Tzu-Ping Huang, Cheng-Yen Lee, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai	A Series Stacked FinFET Structure for Digital Low Dropout Regulators with Minimum Energy Point Technique for 37.5% Energy Reduction in Cortex M0 Processor.	ISCAS	2021	DBLP DOI BibTeX RDF
14	Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis 0001, Cristina Meinhardt	SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology.	LATS	2021	DBLP DOI BibTeX RDF
14	Yan Zheng, Jingchao Lan, Fan Ye 0001, Junyan Ren	A 68.36 dB 12 bit 100MS/s SAR ADC with a low-noise comparator in 14-nm CMOS FinFet.	ASICON	2021	DBLP DOI BibTeX RDF
14	Matthias Eberlein, Harald Pretl	A Compact Thermal Sensor with Duty-Cycle Modulation on 1200 µm2 in 7nm FinFET.	VLSI-DAT	2021	DBLP DOI BibTeX RDF
14	Naheem Olakunle Adesina, Ashok Srivastava, Md Azmot Ullah Khan	Evaluating the Performances of Memristor, FinFET, and Graphene TFET in VLSI Circuit Design.	CCWC	2021	DBLP DOI BibTeX RDF
14	Stephen Traynor, Chen He, Y. Y. Yu, Ken Klein	Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies.	ITC	2021	DBLP DOI BibTeX RDF
14	Maissa Belkhiria, Fraj Echouchene, Nejeh Jaba	Non-Fourier heat conduction effect in nanoscale FinFET and GAAFET Transistor.	SSD	2021	DBLP DOI BibTeX RDF
14	Shashank Banchhor, Nitanshu Chauhan, Aditya Doneria, Bulusu Anand	Gain Stabilization Methodology for FinFET Amplifiers Considering Self-Heating Effect.	VLSID	2021	DBLP DOI BibTeX RDF
14	João Xavier 0001, Pedro Barquinha, João Goes	Design of a Ring-Amplifier Robust Against PVT Variations in Deep-Nanoscale FinFET CMOS.	DCIS	2021	DBLP DOI BibTeX RDF
14	Nandish Mehta, Stephen G. Tell, Walker J. Turner, Lamar Tatro, Giant Goh, C. Thomas Gray	A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop.	A-SSCC	2021	DBLP DOI BibTeX RDF
14	Jeongwon Choe, Youngjoo Lee	A 7Gbps (160, 80) Non-Binary LDPC Decoder with Dual-Message EMS Algorithm in 22nm FinFET Technology.	A-SSCC	2021	DBLP DOI BibTeX RDF
14	G. Cardoso Medeiros, Moritz Fieback, Thiago Santos Copetti, Anteneh Gebregiorgis, Mottaqiallah Taouil, Leticia B. Poehls, Said Hamdioui	Improving the Detection of Undefined State Faults in FinFET SRAMs.	DTIS	2021	DBLP DOI BibTeX RDF
14	Jay Pathak, Anand D. Darji	Analysis of Standard Cells performance for In0.53Ga0.47As FinFET with underlap fin length for High Speed Applications.	VDAT	2021	DBLP DOI BibTeX RDF
14	Sarita Yadav, Nitanshu Chauhan, Archana Pandey, Rajendra Pratap, Anand Bulusu	Behaviour of FinFET Inverter's Effective Capacitances in Low-Voltage Domain.	VDAT	2021	DBLP DOI BibTeX RDF
14	Tzung-Je Lee, Wen-Shou Yang, Chua-Chin Wang	A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology.	APCCAS	2021	DBLP DOI BibTeX RDF
14	Tzung-Je Lee, Wen-Jian Su, Lean Karlo S. Tolentino, Chua-Chin Wang	A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment.	APCCAS	2021	DBLP DOI BibTeX RDF
14	Gerson D. Andrade, Ricardo A. L. Reis, Eduardo A. C. da Costa, Alexandra L. Zimpeck	Sensitivity of FinFET Adders to PVT Variations and Sleep Transistor as a Mitigation Strategy.	APCCAS	2021	DBLP DOI BibTeX RDF
14	Pooja Srivastava, S. C. Bose	Simulated Analysis of Double-Gate MOSFET and FinFET Structure Using High-k Materials.	COMS2	2021	DBLP DOI BibTeX RDF
14	Matteo Pisati, Alberto Minuti, Giacomino Bollati, Fabio Giunco, Roberto G. Massolini, Giovanni Cesura, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Nicola Ghittori, Enrico Pozzati, Marco Sosio, Marco Garampazzi, Antonio Milani	A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
14	Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh	A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
14	Gain Kim, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf	A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
14	Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang	A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
14	Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Shahaboddin Moazzeni, Ralph Mason, Raleigh Smith	A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
14	Paolo Madoglio, Yorgos Palaskas, Jörn Angel, Jakob M. Tomasik, Sven Hampel, Petra Schubert, Peter Preyler, Thomas Mayer 0003, Thomas Bauernfeind, Peter Plechinger, Ashoke Ravi, Ofir Degani, Rotem Banin, Eshel Gordon, Dimo Martev, Timo Gossmann, Andreas Holm, Zdravko Boos	A Cellular Multiband DTC-Based Digital Polar Transmitter With -153-dBc/Hz Noise in 14-nm FinFET.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
14	Mayank Raj, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang	Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
14	Ehsan Mahmoodi, Morteza Gholipour	Design space exploration of low-power flip-flops in FinFET technology.	Integr.	2020	DBLP DOI BibTeX RDF
14	Arindrajit Ghosh, Uddalak Bhattacharya, Manish Kumar, Swapna Banerjee	Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology.	Integr.	2020	DBLP DOI BibTeX RDF
14	Daniel Nagy, Gabriel Espineira, Guillermo Indalecio Fernández, Antonio J. García-Loureiro, Karol Kalna, Natalia Seoane	Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes.	IEEE Access	2020	DBLP DOI BibTeX RDF
14	Jaehyuk Lim, Changhwan Shin	Machine Learning (ML)-Based Model to Characterize the Line Edge Roughness (LER)-Induced Random Variation in FinFET.	IEEE Access	2020	DBLP DOI BibTeX RDF
14	Randy W. Mann, Meixiong Zhao, Oh Sung Kwon, Xi Cao, Sanjay Parihar, Muhammed Ahosan Ul Karim, Jack M. Higman, Joseph Versaggi, Rick Carter	Bias-Dependent Variation in FinFET SRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
14	Siva Nishok Dhanuskodi, Samuel Allen, Daniel E. Holcomb	Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
14	Michael A. Turi, José G. Delgado-Frias	Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
14	Pegah Zakian, Rahebeh Niaraki Asli	An efficient design of low-power and high-speed approximate compressor in FinFET technology.	Comput. Electr. Eng.	2020	DBLP DOI BibTeX RDF
14	Mohd Yasir, Mohammad Samar Ansari	Performance Investigation of FinFET-Based MO-CCII and its Applications: Resistor-Less Multi-Function Bi-Quadratic Filter and Balanced Modulator.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
14	Bhuvana B. P., V. S. Kanchana Bhaaskaran	Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
14	Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo, Kaustav Banerjee	Correction to "Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability".	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
14	Kesavan Subannan Palanisamy, Rajeswari Ramachandran	FinFET-based power-efficient, low leakage, and area-efficient DWT lifting architecture using power gating and reversible logic.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
14	Hong Yang, Luwei Qi, Yanbo Zhang, Bo Tang, Qianqian Liu, Hao Xu, Xueli Ma, Xiaolei Wang, Yongliang Li, Huaxiang Yin, Junfeng Li, Huilong Zhu, Chao Zhao, Wenwu Wang 0006, Tianchun Ye 0001	Influence of an ALD TiN capping layer on the PBTI characteristics of n-FinFET with ALD HfO2/TiN-capping/TiAl gate stacks.	Sci. China Inf. Sci.	2020	DBLP DOI BibTeX RDF
14	Thiago Copetti, Tiago R. Balen, E. Brum, C. Aquistapace, Leticia Bolzani Poehls	Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects.	J. Electron. Test.	2020	DBLP DOI BibTeX RDF
14	Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez 0002, Antonio J. Acosta 0001	Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies.	ACM J. Emerg. Technol. Comput. Syst.	2020	DBLP DOI BibTeX RDF
14	Ning Huang, Weijing Liu, Qinghua Li, Wei Bai, Xiadong Tang, Ting Yang	Thermal and electrical performance investigation of FinFET with encased air-gap gate sidewalls from spacer encapsulation layer material and structure parameter perspectives.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
14	Qiuliang Li, Lei Wu, Ran Liu, Yi Liu	A tunable low noise high PSRR high accuracy bandgap reference using stacked-long cascode technique in 14 nm FinFET process.	Microelectron. J.	2020	DBLP DOI BibTeX RDF