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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6705 occurrences of 3042 keywords
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Results
Found 11076 publication records. Showing 11076 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | Ming-Chung Chen, Ting-Fang Wu |
An Alternative Chinese Keyboard Layout Design for Single-Digit Typists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCHP ![In: Computers Helping People with Special Needs, 10th International Conference, ICCHP 2006, Linz, Austria, July 11-13, 2006, Proceedings, pp. 919-925, 2006, Springer, 3-540-36020-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Esra E. Aleisa, Li Lin 0007 |
For effective facilities planning: layout optimization then simulation, or vice versa? ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the 37th Winter Simulation Conference, Orlando, FL, USA, December 4-7, 2005, pp. 1381-1385, 2005, IEEE Computer Society, 0-7803-9519-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Ulrik Brandes, Daniel Fleischer, Thomas Puppe |
Dynamic Spectral Layout of Small Worlds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GD ![In: Graph Drawing, 13th International Symposium, GD 2005, Limerick, Ireland, September 12-14, 2005, Revised Papers, pp. 25-36, 2005, Springer, 3-540-31425-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Qinghua Liu, Malgorzata Marek-Sadowska |
Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 31-37, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Cristiano Lazzari, Lorena Anghel, Ricardo A. L. Reis |
On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 29-34, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Jae-Gon Kim, Marc Goetschalckx |
A Mixed Integer Programming Model for Modifying a Block Layout to Facilitate Smooth Material Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (4) ![In: Computational Science and Its Applications - ICCSA 2005, International Conference, Singapore, May 9-12, 2005, Proceedings, Part IV, pp. 322-332, 2005, Springer, 3-540-25863-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Rajeev Murgai |
Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 97-102, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Mikko Pohja, Petri Vuorimaa |
CSS Layout Engine for Compound Documents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LA-WEB ![In: Third Latin American Web Congress (LA-Web 2005), 1 October - 2 November 2005, Buenos Aires, Argentina, pp. 148-156, 2005, IEEE Computer Society, 0-7695-2471-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen |
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 604-609, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi |
Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 394-399, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Christian Seybold, Martin Glinz, Silvio Meier, Nancy Merlo-Schett |
An Effective Layout Adaptation Technique for a Graphical Modeling Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: Proceedings of the 25th International Conference on Software Engineering, May 3-10, 2003, Portland, Oregon, USA, pp. 826-827, 2003, IEEE Computer Society, 0-7695-1877-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Maciej J. Ciesielski, Serkan Askar, Samuel Levitin |
Analytical approach to layout generation of datapath cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12), pp. 1480-1488, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Francesca Cesarini, Simone Marinai, Giovanni Soda |
Retrieval by Layout Similarity of Documents Represented with MXY Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Document Analysis Systems ![In: Document Analysis Systems V, 5th International Workshop, DAS 2002, Princeton, NJ, USA, August 19-21, 2002, Proceedings, pp. 353-364, 2002, Springer, 3-540-44068-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Donato Malerba, Floriana Esposito, Oronzo Altamura |
Adaptive Layout Analysis of Document Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMIS ![In: Foundations of Intelligent Systems, 13th International Symposium, ISMIS 2002, Lyon, France, June 27-29, 2002, Proceedings, pp. 526-534, 2002, Springer, 3-540-43785-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Thomas Kutzschebauch, Leon Stok |
Layout Driven Decomposition with Congestion Consideration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 672-676, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Keith J. Keller, Hiroshi Takahashi, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu |
Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 242-247, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong 0001 |
On mask layout partitioning for electron projection lithography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 514-518, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Rituparna Mandal, Dibyendu Goswami, Arup Dash |
Reducing Library Development Cycle Time through an Optimum Layout Create Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 655-660, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Toshinori Yamada, Nobuaki Fujii, Shuichi Ueno |
On three-dimensional layout of pyramid networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 159-164, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Chingwei Yeh, Yin-Shuin Kang |
Cell-based layout techniques supporting gate-level voltage scaling for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(6), pp. 983-986, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, Mu-Chun Wang |
Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 267-272, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Chingwei Yeh, Yin-Shuin Kang |
Cell-based layout techniques supporting gate-level voltage scaling for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(5), pp. 629-633, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky |
Optimal phase conflict removal for layout of dark field alternatingphase shifting masks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2), pp. 175-187, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Mohamed Dessouky, Marie-Minerve Louërat, Jacky Porte |
Layout-Oriented Synthesis of High Performance Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 53-57, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Fenghao Mu, Christer Svensson |
A layout-based schematic method for very high-speed CMOS cell design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(1), pp. 144-148, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Jianying Hu, Ramanujan S. Kashi, Gordon T. Wilfong |
Document Classification Using Layout Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DEXA Workshops ![In: 10th International Workshop on Database & Expert Systems Applications, Florence, Italy, September 1-3, 1999, Proceedings., pp. 556-560, 1999, IEEE Computer Society, 0-7695-0281-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Fenghao Mu, Christer Svensson |
Methodology of layout based schematic and its usage in efficient high performance CMOS design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 254-257, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Bulent Basaran, Kiran Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, Srinivasan Rangarajan, Naresh Sehgal |
GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 448-452, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Pradip K. Kar, Subir K. Roy |
TECHMIG: A Layout Tool for Technology Migration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 615-620, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Toyohide Watanabe, Xiaoou Huang |
Automatic Acquisition of Layout Knowledge for Understanding Business Cards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: 4th International Conference Document Analysis and Recognition (ICDAR '97), 2-Volume Set, August 18-20, 1997, Ulm, Germany, Proceedings, pp. 216-220, 1997, IEEE Computer Society, 0-8186-7898-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Chiu-sing Choy, Tsz-Shing Cheung, Kam-Keung Wong |
Incremental layout placement modification algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(4), pp. 437-445, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
26 | Eser Kandogan, Ben Shneiderman |
Elastic windows: improved spatial layout and rapid multiple window operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AVI ![In: Proceedings of the workshop on Advanced visual interfaces 1996, Gubbio, Italy, May 27-29, 1996, pp. 29-38, 1996, ACM Press, 0-89791-834-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
elastic windows, multi-window operations, personal role manager, CAD, programming environment, window manager, task switching |
26 | Per Andersson, Lars H. Philipson |
Interaction semantics of a symbolic layout editor for parameterized modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8), pp. 1096-1106, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
26 | Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu |
Layout placement for sliced architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(1), pp. 102-114, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
26 | K. P. Ta, T. C. Tan |
Layout Algorithms for DFD Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEKE ![In: SEKE'92, The 4th International Conference on Software Engineering and Knowledge Engineering, June, 15-20 1992, Capri, Italy, pp. 567-573, 1992, IEEE Computer Society, 0-8186-2830-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
26 | Renato Capra |
3D Layout Manipulation Functions with a Glance to Optimization Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APL ![In: Proceedings of the International Conference on APL 1992, St. Petersburg, Russia, July 6-10, 1992., pp. 40-51, 1992, ACM, 0-89791-477-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
APL |
26 | Bradley S. Carlson, C. Y. Roger Chen, Uminder Singh |
Optimal cell generation for dual independent layout styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(6), pp. 770-782, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
26 | Robert L. Maziasz, John P. Hayes |
Layout optimization of static CMOS functional cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7), pp. 708-719, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
26 | William W. Pugh, Grant E. Weddell |
Two-Directional Record Layout for Multiple Inheritance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'90 Conference on Programming Language Design and Implementation (PLDI), White Plains, New York, USA, June 20-22, 1990, pp. 85-91, 1990, ACM, 0-89791-364-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
26 | Magdy S. Abadir, Jack Ferguson |
An improved layout verification algorithm (LAVA). ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 391-395, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
26 | Hong Cai, Ralph H. J. M. Otten |
Conflict-free channel definition in building-block layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(9), pp. 981-988, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
26 | David Marple |
Transistor Size Optimization in the Tailor Layout System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 43-48, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Ichiang Lin, David Hung-Chang Du, Steve H.-C. Yen |
Gate Matrix Layout Synthesis with Two-Dimensional Folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 37-42, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
26 | M. T. Trick, Stephen W. Director |
LASSIE: Structure to Layout for Behavioral Synthesis Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 104-109, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
26 | David Marple, Michiel Smulders, Henk Hegen |
An Efficient Compactor for 45° Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 396-402, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
26 | Y.-C. Chang, S. C. Chang, L.-H. Hsu |
Automated Layout Generation Using Gate Matrix Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 552-558, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
26 | Edward J. DeJesus, James P. Callan, Curtis R. Whitehead |
PEARL: an expert system for power supply layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 615-621, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
26 | Michelangelo Ceci, Margherita Berardi, G. Porcelli, Donato Malerba |
A Data Mining Approach to Reading Order Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: 9th International Conference on Document Analysis and Recognition (ICDAR 2007), 23-26 September, Curitiba, Paraná, Brazil, pp. 924-928, 2007, IEEE Computer Society, 978-0-7695-2822-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | I. Scott MacKenzie, Janet C. Read |
Using paper mockups for evaluating soft keyboard layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASCON ![In: Proceedings of the 2007 conference of the Centre for Advanced Studies on Collaborative Research, October 22-25, 2007, Richmond Hill, Ontario, Canada, pp. 98-108, 2007, IBM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Lihong Zhang, Ulrich Kleine, Yingtao Jiang |
An automated design tool for analog layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 881-894, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Amit Kumar 0022, Noriyuki Miura, Muhammad Muqsith, Tadahiro Kuroda |
Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 271-276, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Martyn Taylor, Peter Rodgers 0001 |
Applying Graphical Design Techniques to Graph Visualisation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IV ![In: 9th International Conference on Information Visualisation, IV 2005, 6-8 July 2005, London, UK, pp. 651-656, 2005, IEEE Computer Society, 0-7695-2397-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Peter Becker 0002 |
Using Intermediate Representation Systems to Interact with Concept Lattices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFCA ![In: Formal Concept Analysis, Third International Conference, ICFCA 2005, Lens, France, February 14-18, 2005, Proceedings, pp. 265-268, 2005, Springer, 3-540-24525-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Sarit Kraus, Alexander Kröner, Lea Tsaban |
IMAP - Intelligent Multimedia Authoring Tools for Electronic Publishing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AH ![In: Adaptive Hypermedia and Adaptive Web-Based Systems, Second International Conference, AH 2002, Malaga, Spain, May 29-31, 2002, Proceedings, pp. 527-530, 2002, Springer, 3-540-43737-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Siu-Cheung Chau, Ada Wai-Chee Fu |
A Gracefully Degradable Declustered RAID Architecture with near Optimal Maximal Read and Write Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2000 IEEE International Conference on Cluster Computing (CLUSTER 2000), November 28th - December 1st, 2000, Technische Universität Chemnitz, Saxony, Germany, pp. 309-318, 2000, IEEE Computer Society, 0-7695-0896-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Declustered RAID, Fault-Tolerant, RAID, Disk Arrays |
26 | Takeshi Tokuda, Jiro Korematsu, Yukihiko Shimazu, Narumi Sakashita, Tohru Kengaku, Toshiki Fugiyama, Takio Ohno, Osamu Tomisawa |
A macrocell approach for VLSI processor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(12), pp. 1272-1277, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
24 | Windsor W. Hsu, Alan Jay Smith, Honesty C. Young |
The automatic improvement of locality in storage systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 23(4), pp. 424-473, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
block layout, defragmentation, disk technology trends, locality improvement, prefetching, data reorganization, data restructuring, Data layout optimization |
24 | Avaneendra Gupta, John P. Hayes |
Width minimization of two-dimensional CMOS cells using integer programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 660-667, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
leaf cell synthesis, two-dimensional layout, diffusion sharing, transistor chains, CMOS networks, Layout optimization, module generation |
24 | Prathima Agrawal, Balakrishnan Narendran, Narayanan Shivakumar |
Multi-way partitioning of VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 393-399, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multi-way partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric |
24 | Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya |
Geometric bipartitioning problem and its applications to VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 400-405, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
geometric bipartitioning problem, layout design, rectilinear modules, staircase, monotone increasing, classical graph bisection problem, weighted permutation graph, integer edge weights, designated nodes, absolute value, edge weights, routing, computational complexity, VLSI, VLSI, graph theory, NP-complete, branch-and-bound, floorplan, heuristic algorithm, search problems, geometry, network routing, circuit layout CAD, hierarchical decomposition |
24 | Alexander Dalal, Lavi Lev, Sundari Mitra |
Design of an efficient power distribution network for the UltraSPARC-I microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 118-123, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
computer power supplies, UltraSPARC-I, simulation method, exact layout locations, excessive voltage drop, floorplanning constraints, power interconnections, reduced time-to-market, circuit analysis computing, circuit layout CAD, microprocessor chips, electromigration, CAD tools, power distribution network |
23 | Mona Haraty, Syavash Nobarany, Steve DiPaola, Brian D. Fisher |
AdWiL: adaptive windows layout manager. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI Extended Abstracts ![In: Proceedings of the 27th International Conference on Human Factors in Computing Systems, CHI 2009, Extended Abstracts Volume, Boston, MA, USA, April 4-9, 2009, pp. 4177-4182, 2009, ACM, 978-1-60558-247-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
creativity, layout, visual analytics, flow, windows management |
23 | Rintaro Miyazaki, Ryo Momose, Hideyuki Shibuki, Tatsunori Mori |
Using web page layout for extraction of sender names. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IUCS ![In: Proceedings of the 3rd International Universal Communication Symposium, IUCS 2009, Tokyo, Japan, 3-4 December 2009, pp. 181-186, 2009, ACM, 978-1-60558-641-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
sender name, web page layout, natural language processing, information credibility |
23 | Daniele Rossi 0001, André K. Nieuwland, Cecilia Metra |
Simultaneous Switching Noise: The Relation between Bus Layout and Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(1), pp. 76-86, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bus layout, switching patterns, system reliability, IC, power supply network, simultaneous switching noise, coding techniques |
23 | Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 387-390, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
layout, body bias |
23 | Krishnan Sundaresan, Nihar R. Mahapatra |
Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 118-122, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bus Energy, Self Heating, Wire Permutation, Optimization, Interconnect, Layout, Temperature, On-Chip Bus |
23 | Edward W. Ishak, Steven Feiner |
Content-aware layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI Extended Abstracts ![In: Extended Abstracts Proceedings of the 2007 Conference on Human Factors in Computing Systems, CHI 2007, San Jose, California, USA, April 28 - May 3, 2007, pp. 2459-2464, 2007, ACM, 978-1-59593-642-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
layout, transparency, scrolling, window manager, fisheye, content-aware |
23 | Nuno C. Lourenço, Nuno C. G. Horta |
Automatic analog IC layout generation based on a evolutionary computation approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2007, Proceedings, London, England, UK, July 7-11, 2007, pp. 2261, 2007, ACM, 978-1-59593-697-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
analog ICs, layout generation, evolutionary computation |
23 | Peter Reid, Fred Hallett-Hook, Beryl Plimmer, Helen C. Purchase |
Applying layout algorithms to hand-drawn graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OZCHI ![In: Proceedings of the 2007 Australasian Computer-Human Interaction Conference, OZCHI 2007, Adelaide, Australia, November 28-30, 2007, pp. 203-206, 2007, ACM, 978-1-59593-872-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
tablet PC, sketch tools, layout algorithms |
23 | Chir-Ho Chang, Jin-Ling Lin |
A Systematic Layout Planning of Visualizing Devices on a Non-rectangular Plane by Genetic Heuristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEA/AIE ![In: New Trends in Applied Artificial Intelligence, 20th International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems, IEA/AIE 2007, Kyoto, Japan, June 26-29, 2007, Proceedings, pp. 424-433, 2007, Springer, 978-3-540-73322-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Layout Planning, Genetic Algorithm, RFID, Heuristic Rules |
23 | Henriette Bier, Adriaan de Jong, Gijs van der Hoorn, Niels Brouwers, Marijn Heule, Hans van Maaren |
Prototypes for Automated Architectural 3D-Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VSMM ![In: Virtual Systems and Multimedia, 13th International Conference, VSMM 2007, Brisbane, Australia, September 23-26, 2007, Revised Selected Papers, pp. 203-214, 2007, Springer, 978-3-540-78565-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
3D-Modeling and Automated Spatial Layout, Euclidean and Non-Euclidean Ge ometries, Satisfiability |
23 | Jie Zou, Daniel X. Le, George R. Thoma |
Combining DOM tree and geometric layout analysis for online medical journal article segmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JCDL ![In: ACM/IEEE Joint Conference on Digital Libraries, JCDL 2006, Chapel Hill, NC, USA, June 11-15, 2006, Proceedings, pp. 119-128, 2006, ACM, 1-59593-354-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
HTML document segmentation, document object model (DOM), web information retrieval, document layout analysis |
23 | Christian Klukas, Falk Schreiber, Henning Schwöbbermeyer |
Coordinated perspectives and enhanced force-directed layout for the analysis of network motifs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APVIS ![In: Asia-Pacific Symposium on Information Visualisation, APVIS 2006, Tokyo, Japan, February 1-3, 2006, pp. 39-48, 2006, Australian Computer Society, 1-920682-41-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
coordinated perspectives, graph drawing, network analysis, multiple views, information visualisation, network motifs, force-directed layout |
23 | Xing Xie 0001, Chong Wang 0002, Li-Qun Chen, Wei-Ying Ma |
An adaptive web page layout structure for small devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multim. Syst. ![In: Multim. Syst. 11(1), pp. 34-44, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Slicing tree, Mobile device, Web browsing, Layout optimization, Adaptive content delivery |
23 | David R. Wood |
Minimising the Number of Bends and Volume in 3-Dimensional Orthogonal Graph Drawings with a Diagonal Vertex Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmica ![In: Algorithmica 39(3), pp. 235-253, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Diagonal layout, Vertex-ordering, Book embedding, Graph drawing, Dimensional, Orthogonal |
23 | Sheelagh Carpendale, Anand Agarawala |
PhylloTrees: Harnessing Nature's Phyllotactic Patterns for Tree Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOVIS ![In: 10th IEEE Symposium on Information Visualization (InfoVis 2004), 10-12 October 2004, Austin, TX, USA, 2004, IEEE Computer Society, 0-7803-8779-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
phyllotactic patterns, information visualization, Graph layout, tree visualization |
23 | Goeran Jerke, Jens Lienig, Jürgen Scheible |
Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 181-184, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
decompaction, layout decomposition, physical design, compaction, electromigration, interconnect reliability |
23 | Steven J. Harrington, J. Fernando Naveda, Rhys Price Jones, Paul G. Roetling, Nishant Thakkar |
Aesthetic measures for automated document layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Symposium on Document Engineering ![In: Proceedings of the 2004 ACM Symposium on Document Engineering, Milwaukee, Wisconsin, USA, October 28-30, 2004, pp. 109-111, 2004, ACM, 1-58113-938-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
document, layout, aesthetics |
23 | Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu |
An algebraic multigrid solver for analytical placement with layout based clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 794-799, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
algebraic multigrid method, layout based clustering, analytical placement |
23 | James Burns, Jean-Luc Gaudiot |
SMT Layout Overhead and Scalability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 13(2), pp. 142-155, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
layout area estimation, microarchitecture trade-off, processor architecture, SMT |
23 | David Harel, Gregory Yashchin |
An algorithm for blob hierarchy layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Vis. Comput. ![In: Vis. Comput. 18(3), pp. 164-185, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Higraph, Hierarchy, Layout, Statechart, Aesthetics |
23 | Katsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka |
Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 162-167, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
automatic fault tracing system, EB tester, CAD layout, VLSI |
23 | Timothy K. Shih, Anthony Y. Chang |
A schedule/layout computation model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 4th International Workshop on Real-Time Computing Systems and Applications (RTCSA '97), 27-29 October 1997, Taipei, Taiwan, pp. 178-181, 1997, IEEE Computer Society, 0-8186-8073-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
schedule/layout computation model, temporal intervals, temporal relation compositions, temporal relation algebraic system, virtual reality timing constraints, virtual reality, time constraints, multimedia presentations, multimedia documents |
23 | Jason Cong, Cheng-Kok Koh |
Interconnect layout optimization under higher-order RLC model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 713-720, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization |
23 | Kanad Chakraborty, Pinaki Mazumder |
An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 685-688, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
bus-layout, bussed driver shorts, early diagnosis, field survivability, interconnect shorts, production yield, printed circuit boards, printed circuit testing |
23 | Nalini K. Ratha, Anil K. Jain 0001, Diane T. Rover |
FPGA-based high performance page layout segmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 29-34, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Splash 2, page layout segmentation algorithm, FPGA array processor, Xilinx synthesis tool, 5 GHz, 1024 pixel, field programmable gate arrays, image segmentation, parallel processing, text |
23 | Chienhua Chen, Dharma P. Agrawal, J. Richard Burke |
dBCube: A New Class of Hierarchical Multiprocessor Interconnection Networks with Area Efficient Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(12), pp. 1332-1344, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
dBCube, hierarchical multiprocessor interconnection networks, area efficient layout, node connectivity, compound graph, necklace, performance evaluation, VLSI, graphs, hypercube, multiprocessor interconnection networks, hierarchical networks, wafer scale integration, de Bruijn graph, hypercube topology, Communication locality |
23 | R. Burgess, C. Wouters |
PARAGON: a new package for gate matrix layout synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 129-134, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
cell generation, gate-matrix layout, routing, simulated annealing, optimisation, placement, logic synthesis, physical design |
23 | Subhas C. Nandy, Bhargab B. Bhattacharya, Sibabrata Ray |
Efficient algorithms for Identifying All Maximal Isothetic Empty Rectangles in VLSI Layout Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSTTCS ![In: Foundations of Software Technology and Theoretical Computer Science, Tenth Conference, Bangalore, India, December 17-19, 1990, Proceedings, pp. 255-269, 1990, Springer, 3-540-53487-3. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
interval trees, complexity, Computational geometry, placement, VLSI layout, geometric algorithms |
23 | Jinseong Jeon, Keoncheol Shin, Hwansoo Han |
Abstracting access patterns of dynamic memory using regular expressions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 5(4), pp. 18:1-18:28, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
field affinity, layout transformation, pool allocation, regular expressions, Access patterns |
23 | Helen C. Purchase, Amanjit Samra |
Extremes Are Better: Investigating Mental Map Preservation in Dynamic Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Diagrams ![In: Diagrammatic Representation and Inference, 5th International Conference, Diagrams 2008, Herrsching, Germany, September 19-21, 2008. Proceedings, pp. 60-73, 2008, Springer, 978-3-540-87729-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Dynamic graph layout, empirical study, mental map |
23 | Cameron L. McCormack, Kim Marriott, Bernd Meyer 0001 |
Authoring adaptive diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Symposium on Document Engineering ![In: Proceedings of the 2008 ACM Symposium on Document Engineering, Sao Paulo, Brazil, September 16-19, 2008, pp. 154-163, 2008, ACM, 978-1-60558-081-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
authoring, diagrams, adaptive layout |
23 | Tim Dwyer, Kim Marriott |
Constrained Stress Majorization Using Diagonally Scaled Gradient Projection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GD ![In: Graph Drawing, 15th International Symposium, GD 2007, Sydney, Australia, September 24-26, 2007. Revised Papers, pp. 219-230, 2007, Springer, 978-3-540-77536-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
constraints, graph layout |
23 | Liying Wang, Wei Hua, Hujun Bao |
Procedural Modeling of Residential Zone Subject to Urban Planning Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEC ![In: Entertainment Computing - ICEC 2007, 6th International Conference, Shanghai, China, September 15-17, 2007, Proceedings, pp. 150-161, 2007, Springer, 978-3-540-74872-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
constrained layout optimization, Procedural modeling, urban planning |
23 | Mehrdad Najibi, Kamran Saleh, Hossein Pedram |
Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 299-304, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
quasi-delay insensitive, standard-cell layout, asynchronous circuits |
23 | Alexander J. Macdonald, David F. Brailsford, Steven R. Bagley, John William Lumley |
Speculative document evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Symposium on Document Engineering ![In: Proceedings of the 2007 ACM Symposium on Document Engineering, Winnipeg, Manitoba, Canada, August 28-31, 2007, pp. 56-58, 2007, ACM, 978-1-59593-776-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
VDP, speculative evaluation, optimisation, SVG, document layout, PPML |
23 | Kim Marriott, Peter Moulder, Nathan Hurst |
Automatic float placement in multi-column documents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Symposium on Document Engineering ![In: Proceedings of the 2007 ACM Symposium on Document Engineering, Winnipeg, Manitoba, Canada, August 28-31, 2007, pp. 125-134, 2007, ACM, 978-1-59593-776-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
floating figure, multi-column layout, optimization techniques |
23 | Yingxin Wu 0001, Masahiro Takatsuka |
Visualizing multivariate network on the surface of a sphere. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APVIS ![In: Asia-Pacific Symposium on Information Visualisation, APVIS 2006, Tokyo, Japan, February 1-3, 2006, pp. 77-83, 2006, Australian Computer Society, 1-920682-41-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
GeoSOM, circular layout, multivariate network, information visualization, graph drawing |
23 | M. Monemizadeh, Hamid Sarbazi-Azad |
The necklace-hypercube: a well scalable hypercube-based interconnection network for multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), Santa Fe, New Mexico, USA, March 13-17, 2005, pp. 729-733, 2005, ACM, 1-58113-964-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
necklace-hypercube, routing, interconnection networks, broadcast, hypercube, VLSI layout, topological properties |
23 | Jack Kustanowitz, Ben Shneiderman |
Meaningful presentations of photo libraries: rationale and applications of bi-level radial quantum layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JCDL ![In: ACM/IEEE Joint Conference on Digital Libraries, JCDL 2005, Denver, CO, USA, June 7-11, 2005, Proceedings, pp. 188-196, 2005, ACM, 1-58113-876-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
layout generation, photo management, visual presentation, user interfaces, digital libraries |
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