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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 3882 publication records. Showing 3880 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
22 | R. Manoj Kumar, P. V. Sridevi |
Design of a High Performance 1 Kb SRAM Array Using Proposed Soft Error Hardened 12T SRAM Cell. |
J. Circuits Syst. Comput. |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda |
A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers. |
HCS |
2022 |
DBLP DOI BibTeX RDF |
|
22 | He Zhang 0011, Linjun Jiang, Jianxin Wu, Tingran Chen, Junzhan Liu, Wang Kang 0001, Weisheng Zhao |
CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory. |
DAC |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Nezam Rohbani, Masoumeh Ebrahimi |
SRAM Gauge: SRAM Health Monitoring via Cells Race. |
ISLPED |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Shihui Yin, Zhewei Jiang, Jae-Sun Seo, Mingoo Seok |
XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks. |
IEEE J. Solid State Circuits |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Frank Bubenhagen |
Analysis and Enhancement of a Fault-Tolerant NoC for SRAM-based FPGAs in Space Applications (Analyse und Erweiterung eines fehler-toleranten NoC für SRAM-basierte FPGAs in Weltraumapplikationen) (PDF / PS) |
|
2020 |
DOI RDF |
|
22 | Avishek Biswas, Anantha P. Chandrakasan |
CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks. |
IEEE J. Solid State Circuits |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Zhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok |
XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism. |
ACM Great Lakes Symposium on VLSI |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Zhi-Wei Lai, Kuen-Jong Lee |
Using Unstable SRAM Bits for Physical Unclonable Function Applications on Off-The-Shelf SRAM. |
APCCAS |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Ihsen Alouani, Wael M. Elsharkasy, Ahmed M. Eltawil, Fadi J. Kurdahi, Smaïl Niar |
AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement. |
IET Circuits Devices Syst. |
2017 |
DBLP DOI BibTeX RDF |
|
22 | T. R. Rajalakshmi, R. Sudhakar 0001 |
Impact of Single Event Upset on Voltage and Current Behaviors of CNTFET SRAM and a Comparison with CMOS SRAM. |
J. Circuits Syst. Comput. |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Anuj Grover, G. S. Visweswaran, Chittoor R. Parthasarathy, Mohammad Daud, David Turgis, Bastien Giraud, Jean-Philippe Noel, Ivan Miro Panades, Guillaume Moritz, Edith Beigné, Philippe Flatresse, Promod Kumar, Shamsi Azmi |
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Harsh Rawat, K. Bharath, Alexander Fell |
Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology. |
SoCC |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Ahmed S. Sajit, Michael A. Turi |
SEU tolerance of FinFET 6T SRAM, 8T SRAM and DICE memory cells. |
CCWC |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Jinhui Wang, Lina Wang, Haibin Yin, Zikui Wei, Zezhong Yang, Na Gong |
cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System. |
IEEE Trans. Computers |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Ebrahim Abiri, Abdolreza Darabi |
A novel design of low power and high read stability Ternary SRAM (T-SRAM), memory based on the modified Gate Diffusion Input (m-GDI) method in nanotechnology. |
Microelectron. J. |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Ali Asghar, Muhammad Mazher Iqbal, Waqar Ahmed, Mujahid Ali, Husain Parvez, Muhammad Rashid |
Exploring shared SRAM tables among NPN equivalent large LUTs in SRAM-based FPGAs. |
FPT |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Pulkit Sharma, R. Anusha, K. Bharath, Jasmine Kaur Gulati, Preet K. Walia, Sumit Jagdish Darak |
Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Farid Lahrach |
Tolérance aux pannes des circuits FPGAs à base de mémoire SRAM. (Fault tolerance of SRAM-based FPGAs circuits). |
|
2016 |
RDF |
|
22 | Arijit Banerjee 0002, Jacob Breiholz, Benton H. Calhoun |
A 130nm canary SRAM for SRAM dynamic write VMIN tracking across voltage, frequency, and temperature variations. |
CICC |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Zhe Zhang, Michael A. Turi, José G. Delgado-Frias |
SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang |
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. |
VLSI-DAT |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Adam Teman, Lidor Pergament, Omer Cohen, Alexander Fish |
A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM). |
IEEE J. Solid State Circuits |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Tony Tae-Hyoung Kim, Zhi-Hui Kong |
Impacts of NBTI/PBTI on SRAM VMIN and design techniques for SRAM VMIN improvement. |
ISOCC |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Yen-Huei Chen, Gary Chan, Shao-Yu Chou, Hsien-Yu Pan, Jui-Jen Wu, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi |
A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs. |
IEEE J. Solid State Circuits |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das |
Yield estimation of SRAM circuits using "Virtual SRAM Fab". |
ICCAD |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara |
Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices. |
CICC |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Mahadevan Gomathisankaran, Akhilesh Tyagi |
WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays. |
J. Low Power Electron. |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Tohru Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Takemitsu Kunio |
NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors. |
IEEE J. Solid State Circuits |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Tohm Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Tom Tatsumi, Yukihiro Maejima, Hiromitsu Hada, Takemitsu Kunio |
NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors. |
CICC |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Bo-Ting Wang, James B. Kuo |
A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. |
ISCAS |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Xin He, Jorgen Peddersen, Sri Parameswaran |
LOP: a novel SRAM-based architecture for low power and high throughput packet classification. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
low-power, packet classification, hardware design |
19 | Egas Henes Neto, Gilson I. Wirth, Fernanda Lima Kastensmidt |
Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors. |
J. Electron. Test. |
2008 |
DBLP DOI BibTeX RDF |
Fault-tolerance, Reliability, Testing, Built-in tests, Error-checking |
19 | Alexandre Ney, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin |
A Design-for-Diagnosis Technique for SRAM Write Drivers. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Tadayoshi Enomoto, Yuki Higuchi |
A low-leakage current power 180-nm CMOS SRAM. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Hoang Le, Weirong Jiang, Viktor K. Prasanna |
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA. |
FCCM |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang |
Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Michael Wieckowski, Martin Margala |
A portless SRAM Cell using stunted wordline drivers. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Bastien Giraud, Amara Amara |
A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty |
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Mark Lysinger, François Jacquet, Mehdi Zamanian, David McClure, Philippe Roche, Naren Sahoo, John Russell |
A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Rad Hard |
19 | Robert C. Aitken, Sachin Idgunji |
Worst-case design and margin for embedded SRAM. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura |
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan |
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Xiaoyao Liang, Kerem Turgay, David M. Brooks |
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan |
CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Jungseob Lee, Azadeh Davoodi |
Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan |
Multiple Upsets Tolerance in SRAM Memory. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif |
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi |
Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Lava P. Kumar, Baquer Mazhari |
Optimum Supply Voltages for Minimization of Leakage Currents in SRAM in Stand-by Mode. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard 0001 |
Minimizing test power in SRAM through reduction of pre-charge activity. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene |
On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components. |
MTDT |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Tianzhou Chen, Hu Wei, Lian Yi |
Microkernel of Embedded Operating System in SRAM. |
IWNAS |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Thomas Janik, Eric Liau, Harald Lorenz, Manfred Menke, Eckehard Plaettner, Joerg Schweden, Helmut Seitz, Esther Vega-Ordonez |
A 1.8V p(seudo)SRAM using standard 140nm DRAM technology with self adapting clocked standby operation. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Melanie Berg |
Fault Tolerance Implementation within SRAM Based FPGA Design Based upon the Increased Level of Single Event Upset Susceptibility. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Maico Cassel, Fernanda Lima Kastensmidt |
Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene |
Statistically Aware SRAM Memory Array Design. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara |
Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor. |
IEEE Micro |
2005 |
DBLP DOI BibTeX RDF |
11 fan-out of four, 11FO4, Synergistic Processor Element, private memory, streaming processing, Cell processor, multimedia processing, scratch pad memory |
19 | Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell |
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. |
J. Electron. Test. |
2005 |
DBLP DOI BibTeX RDF |
look-up table (LUT), FPGA, test, delay fault |
19 | Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda |
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Hua Wang, Miguel Miranda, Wim Dehaene, Francky Catthoor, Karen Maex |
Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Baosheng Wang, Josh Yang, Yuejian Wu, André Ivanov |
A retention-aware test power model for embedded SRAM. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
data retention fault test, multiple embedded SRAMs, test power modeling, test scheduling |
19 | Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001 |
A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, Jethro C. Law, Rajiv V. Joshi |
A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Ramy E. Aly, Mohamed A. Elgamel, Magdy A. Bayoumi |
Dual sense amplified bit lines (DSABL) architecture for low-power SRAM design. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Yat-Fong Yung, Amine Bermak |
A PWM DPS with pixel-level reconfigurable 4/8-bit counter/SRAM. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Balkaran S. Gill, Michael Nicolaidis, Christos A. Papachristou |
Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Somsubhra Mondal, Seda Ogrenci Memik |
Fine-grain leakage optimization in SRAM based FPGAs. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
hierarchical LUT, FPGA, low power, leakage power |
19 | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan |
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
Complex Logic Blocks, Routing Errors, Vertex Coloring problem, Fault Tolerance, Field Programmable Gate Arrays, Graph Theory, Single Event Upset |
19 | Fernanda Lima Kastensmidt, Gustavo Neuberger, Renato Fernandes Hentschke, Luigi Carro, Ricardo Reis 0001 |
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs. |
IEEE Des. Test Comput. |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Stefan Cserveny, Jean-Marc Masgonty, Christian Piguet |
Noise Margin in Low Power SRAM Cells. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Fatih Kocan, Jason Meyer |
Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Carolina Selva, Cosimo Torelli, Danilo Rimondi, Rita Zappa, Stefano Corbani, Giovanni Mastrodomenico, Lara Albani |
A Programmable Built-in Self-Diagnosis for Embedded SRAM. |
MTDT |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Fernanda Lima Kastensmidt, Gustavo Neuberger, Luigi Carro, Ricardo Reis 0001 |
Designing and testing fault-tolerant techniques for SRAM-based FPGAs. |
Conf. Computing Frontiers |
2004 |
DBLP DOI BibTeX RDF |
fault-tolerance, FPGA |
19 | Hari Ananthan, Aditya Bansal, Kaushik Roy 0001 |
FinFET SRAM - Device and Circuit Design Considerations. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Navid Azizi, Farid N. Najm |
An Asymmetric SRAM Cell to Lower Gate Leakage. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Ad J. van de Goor, Said Hamdioui, Rob Wadsworth |
Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
address directions, peripheral circuit faults, fault coverage, March tests, data-backgrounds |
19 | Rajiv V. Joshi, Ching-Te Chuang, Samuel K. H. Fung, Fari Assaderaghi, Melanie Sherony, I. Yang, Ghavam V. Shahidi |
PD/SOI SRAM performance in presence of gate-to-body tunneling current. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Abderrahim Doumar, Hideo Ito |
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
19 | L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti 0001 |
A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Rei-Fu Huang, Yung-Fa Chou, Cheng-Wen Wu |
Defect Oriented Fault Analysis for SRAM. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Monica Alderighi, Sergio D'Angelo, Marcello Mancini, Giacomo R. Sechi |
A Fault Injection Tool for SRAM-based FPGAs. |
IOLTS |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Massimo Violante, M. Ceschia, Matteo Sonza Reorda, Alessandro Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori |
Analyzing SEU Effects in SRAM-based FPGAs. |
IOLTS |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Li Ding 0002, Pinaki Mazumder |
The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Fernanda Lima 0001, Luigi Carro, Ricardo Augusto da Luz Reis |
Designing fault tolerant systems into SRAM-based FPGAs. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
fault-tolerance, FPGA |
19 | Hong-Sik Kim, Sungho Kang 0001 |
DPSC SRAM Transparent Test Algorithm. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Bernard Coloma, Patrick Delaunay, Olivier Husson |
High Speed 15 ns 4 Mbits SRAM for Space Application. |
MTDT |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Chris H. Kim, Kaushik Roy 0001 |
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
|
19 | A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis |
SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Bernard Coloma, Patrick Delaunay, Olivier Husson |
High Speed 15 ns 4 Mbits SRAM for Space Application. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira 0001 |
Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Jayasanker Jayabalan, Juraj Povazanec |
Integration of SRAM Redundancy into Production Test. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka Phani, Ansuman Rout |
Architecture and Design of a High Performance SRAM for SOC Design. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang 0002 |
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Michael Meißner, Michael C. Doggett, Urs Kanus, Johannes Hirche |
Accelerating volume rendering using an on-chip SRAM occupancy map. |
ISCAS (2) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
Testing the Local Interconnect Resources of SRAM-Based FPGA's. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
FPGA, VLSI, test, ATPG |
19 | Michel Renovell |
A Specific Test Methodology for Symmetric SRAM-Based FPGAs. |
FPL |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Christophe Frey, F. Genevaux, C. Issartel, D. Turgis, Jean-Pierre Schoellkopf |
A Low Voltage Embedded Single Port SRAM Generator in a 0.18µm Standard CMOS Process. |
MTDT |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni |
A Family of Self-Repair SRAM Cores. |
IOLTW |
2000 |
DBLP DOI BibTeX RDF |
Memory Self-Repair, Memory BIST, BISR |
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