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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6285 occurrences of 1975 keywords
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Results
Found 21486 publication records. Showing 21486 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
32 | Kuen Hung Tsoi, Wayne Luk |
Axel: a heterogeneous cluster with FPGAs and GPUs. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
FPGA, heterogeneous cluster |
32 | Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita |
Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
overclocking, timing error detection, timing error recovery, fpga |
32 | Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain |
Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only). |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
fpga, dynamic programming, systolic array, throughput optimization, recurrences |
32 | Viktor Pus, Jan Korenek |
Fast and scalable packet classification using perfect hash functions. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
fpga, sram, packet classification |
32 | Süleyman Sirri Demirsoy, Martin Langhammer |
Cholesky decomposition using fused datapath synthesis. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
cholesky, fused datapath synthesis, fpga, floating-point |
32 | Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour |
Towards automated ECOs in FPGAs. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
pst, optimization, fpga, boolean satisfiability, resynthesis |
32 | Dirk Koch, Christian Beckhoff, Jürgen Teich |
A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
fpga, reconfiguration, communication architecture |
32 | David Sheldon, Frank Vahid |
Making good points: application-specific pareto-point generation for design space exploration using statistical methods. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
configurable platform, fpga, low-power, exploration, speedup, pruning, pareto-optimal, design of experiments |
32 | Abhranil Maiti, Patrick Schaumont |
Impact and compensation of correlated process variation on ring oscillator based puf. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
correlated process variation, physical unclonable function (puf), ring oscillator (ro), fpga |
32 | Jason Helge Anderson |
Emerging application domains: research challenges and opportunities for FPGAs. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
performance, field-programmable gate array, fpga, applications, high-performance computing, power, reconfigurable computing |
32 | Jean-Baptiste Note, Éric Rannaud |
From the bitstream to the netlist. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
bitstream format, FPGA, reverse-engineering |
32 | Matthew Collin Jordan, Ramachandran Vaidyanathan |
Configurable decoders with application in fast partial reconfiguration of FPGAs. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
FPGA, decoder, look-up table, configurable logic |
32 | Maryam Moazeni, Alireza Vahdatpour, Karthik Gururaj, Majid Sarrafzadeh |
Communication bottleneck in hardware-software partitioning. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
FPGA, communication, hardware-software codesign |
32 | Atul Mahajan, Benfano Soewito, Sai K. Parsi, Ning Weng, Haibo Wang 0005 |
Implementing high-speed string matching hardware for network intrusion detection systems. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
FPGA, string matching, network intrusion detection systems |
32 | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer |
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
simulation, FPGA, prototyping, performance models, emulation |
32 | Kai Zhu 0001 |
Post-route LUT output polarity selection for timing optimization. |
FPGA |
2007 |
DBLP DOI BibTeX RDF |
optimization, timing, polarity, FPGA lookup table |
32 | Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton |
Improvements to technology mapping for LUT-based FPGAs. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
area recovery, cut enumeration, lossless synthesis, FPGA, technology mapping |
32 | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
Application-specific customization of soft processor microarchitecture. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
Nios, RTL generation, SPREE, FPGA, customization, embedded processor, ASIP, microarchitecture, application specific, soft processor |
32 | Peter A. Milder, Mohammad Ahmad, James C. Hoe, Markus Püschel |
Fast and accurate resource estimation of automatically generated custom DFT IP cores. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
FPGA resource estimation, design generator, IP, discrete fourier transform |
32 | Ling Zhuo, Viktor K. Prasanna |
Sparse Matrix-Vector multiplication on FPGAs. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
FPGA, reconfigurable architecture, high performance, floating-point, sparse matrix |
32 | Mike Hutton, David Karchmer, Bryan Archell, Jason Govig |
Efficient static timing analysis and applications using edge masks. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
cut-path, multicycle, thru-x, FPGA, placement, timing analysis |
32 | Gang Chen 0020, Jason Cong |
Simultaneous timing-driven placement and duplication. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
logic duplication, FPGA, legalization, timing-driven placement, redundancy removal |
32 | Paul Metzgen |
A high performance 32-bit ALU for programmable logic. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
ALU, Apex 20KE, Nios, FPGA, programmable logic, soft processors |
32 | Seonil Choi, Ronald Scrofano, Viktor K. Prasanna, Ju-wook Jang |
Energy-efficient signal processing using FPGAs. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
energy efficient design techniques, matrix multiplicaiton, FPGA, FFT, performance estimation |
32 | Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä |
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
FPGA, pipelining, advanced encryption standard (AES) |
32 | Prasanna Sundararajan, Steve Guccione |
Run-Time defect tolerance using JBits. |
FPGA |
2001 |
DBLP DOI BibTeX RDF |
Java, FPGA, cores, defect tolerance, run-time reconfiguration |
32 | John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak |
Efficiently Supporting Fault-Tolerance in FPGAs. |
FPGA |
1998 |
DBLP DOI BibTeX RDF |
fault-tolerance, FPGA |
32 | Mingjie Lin, Ilia A. Lebedev, John Wawrzynek |
High-throughput bayesian computing machine with reconfigurable hardware. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
reconfigurable hardware, bayesian computing |
32 | Florian Dittmann 0001, Elmar Weber, Norma Montealegre |
Implementation of the reconfiguration port scheduling on the erlangen slot machine. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
erlangen slot machine, scheduling, fpgas, reconfiguration |
32 | Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal |
Architecture-specific packing for virtex-5 FPGAs. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
optimization, performance, FPGAs, field-programmable gate arrays, power, placement, packing |
32 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
High-throughput interconnect wave-pipelining for global communication in FPGAs. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
|
32 | John H. Kelm, Steven S. Lumetta |
HybridOS: runtime support for reconfigurable accelerators. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
CPU/accelerator architecture, operating system, reconfigurable computing |
32 | Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton |
GlitchLess: an active glitch minimization technique for FPGAs. |
FPGA |
2007 |
DBLP DOI BibTeX RDF |
field-programmable gate arrays, power minimization |
32 | Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali |
Testing embedded RAM modules in SRAM-based FPGAs. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Young H. Cho, James Moscola, John W. Lockwood |
Context-free-grammar based token tagger in reconfigurable devices. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Oliver Sims, James Irvine 0001 |
A real-time implementation of Richardson-Lucy deconvolution. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Ian Kuon, Aaron Egier, Jonathan Rose |
Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
32 | John Teifel, Rajit Manohar |
Highly pipelined asynchronous FPGAs. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
concurrency, pipelining, asynchronous circuits, programmable logic, correctness by construction |
32 | Vinay Verma, Shantanu Dutt |
Roving testing using new built-in-self-tester designs for FPGAs. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Deshanand P. Singh, Stephen Dean Brown |
The case for registered routing switches in field programmable gate arrays. |
FPGA |
2001 |
DBLP DOI BibTeX RDF |
|
32 | César Torres-Huitzil, Miguel O. Arias-Estrada |
An FPGA Architecture for High Speed Edge and Corner Detection. |
CAMP |
2000 |
DBLP DOI BibTeX RDF |
FPGA resources utilization, computer vision, computer vision, edge detection, architecture design, corner detection, high speed, FPGA architecture |
32 | Maya B. Gokhale, Janice M. Stone, Jeffrey M. Arnold, Mirek Kalinowski |
Stream-Oriented FPGA Computing in the Streams-C High Level Language. |
FCCM |
2000 |
DBLP DOI BibTeX RDF |
FPGA design tools, FPGA, high-level synthesis, configurable computing, hardware-software co-design, silicon compiler |
32 | Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen |
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
LUT-Based FPGA Technology Mapping, Area/Performance Trade-Off and Timing Driven FPGA Synthesis |
32 | Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo 0003, Jie Zhou 0007, Li Shen |
FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing. |
ICS |
2010 |
DBLP DOI BibTeX RDF |
double-double precision, high precision floating-point multiplication and accumulation (HP-MAC), quad-double precision, FPGA |
32 | Ming Liu 0022, Haigang Yang, Sansiri Tanachutiwat, Wei Wang 0003 |
Carbon Nanotube Nanorelays with Pass-Transistor for FPGA Routing Devices. |
NanoNet |
2009 |
DBLP DOI BibTeX RDF |
carbon nanorelay, nanoelectromechanical switch, CMOS-nano hybrid, FPGA, carbon nanotube |
32 | JingXia Wang, Sin Ming Loo |
Case study of finite resource optimization in FPGA using genetic algorithm. |
GEC Summit |
2009 |
DBLP DOI BibTeX RDF |
genetic algorithm, scheduling, FPGA, resource utilization |
32 | Yong Dou, Fei Xia, Jingfei Jiang |
Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA. |
CASES |
2009 |
DBLP DOI BibTeX RDF |
SCFGS, reconfigurable algorithm accelerator, secondary structure prediction, FPGA, RNA |
32 | Sol Pedre, Andres Stoliar, Patricia Borensztejn |
Real Time Hot Spot Detection Using FPGA. |
CIARP |
2009 |
DBLP DOI BibTeX RDF |
hot spot detection, FPGA, remote sensing, embedded computing, real time image processing |
32 | Abner Corrêa Barros, Victor Wanderley Costa de Medeiros, Viviane Lucy Santos de Souza, Paulo Sérgio Brandão do Nascimento, Ângelo Mazer, João Paulo Fernandes Barbosa, Bruno P. Neves, Ismael Santos 0001, Manoel Eusébio de Lima |
Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA. |
SBCCI |
2008 |
DBLP DOI BibTeX RDF |
FPGA, scientific computing, floating-point, HPC |
32 | Helano Castro, Alexandre Augusto Coelho, Ricardo Jardel Silveira |
Fault-tolerance in FPGA's through CRC voting. |
SBCCI |
2008 |
DBLP DOI BibTeX RDF |
cyclic redundancy check, fault tolerance, FPGA, partial reconfiguration |
32 | Maizura Mokhtar, David M. Halliday, Andy M. Tyrrell |
Hippocampus-Inspired Spiking Neural Network on FPGA. |
ICES |
2008 |
DBLP DOI BibTeX RDF |
Bio-inspired Hardware, FPGA, Spiking Neural Network |
32 | Greg Stitt, Gaurav Chaudhari, James Coole |
Traversal caches: a first step towards FPGA acceleration of pointer-based data structures. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
traversal cache, fpga, synthesis, hardware/software partitioning, pointers, cad |
32 | Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia |
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
STTRAM, emerging memory technologies, nonvolatile FPGA |
32 | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
VESPA: portable, scalable, and flexible FPGA-based vector processors. |
CASES |
2008 |
DBLP DOI BibTeX RDF |
SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor |
32 | Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger |
An 8x8 run-time reconfigurable FPGA embedded in a SoC. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
FPGA, RTR |
32 | Yan Lin Aung, Douglas L. Maskell, Timothy F. Oliver, Bertil Schmidt, William Bong |
C-Based Design Methodology for FPGA Implementation of ClustalW MSA. |
PRIB |
2007 |
DBLP DOI BibTeX RDF |
ClustalW, FPGA, multiple sequence alignment, sequence analysis |
32 | Thinh Ngoc Tran, Surin Kittitornkun |
FPGA-Based Cuckoo Hashing for Pattern Matching in NIDS/NIPS. |
APNOMS |
2007 |
DBLP DOI BibTeX RDF |
NIPS, FPGA, Pattern Matching, NIDS, Cuckoo Hashing |
32 | Paulo Sérgio B. do Nascimento, Manoel Eusébio de Lima, Stelita M. da Silva, Jordana L. Seixas |
Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration. |
SBCCI |
2006 |
DBLP DOI BibTeX RDF |
FPGA-computers, area-time trade-offs, temporal partitioning techniques, image processing, design space exploration |
32 | Georges Nabaa, Navid Azizi, Farid N. Najm |
An adaptive FPGA architecture with process variation compensation and reduced leakage. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
FPGA, process variations, leakage, body-biasing |
32 | Brendan P. Glackin, T. Martin McGinnity, Liam P. Maguire, Qingxiang Wu, Ammar Belatreche |
A Novel Approach for the Implementation of Large Scale Spiking Neural Networks on FPGA Hardware. |
IWANN |
2005 |
DBLP DOI BibTeX RDF |
SNN, I&F, FPGA, Hardware |
32 | Young-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel |
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool. |
SLIP |
2005 |
DBLP DOI BibTeX RDF |
3-D FPGA, wire resource prediction |
32 | Chris Dick, Fred Harris 0001, Michael Rice |
FPGA Implementation of Carrier Synchronization for QAM Receivers. |
J. VLSI Signal Process. |
2004 |
DBLP DOI BibTeX RDF |
carrier recovery, system generator, FPGA, synchronization, wireless communication, software define radio, CORDIC, QAM |
32 | Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu 0001 |
Zero overhead watermarking technique for FPGA designs. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
configuration bitstream, timing analyzer, user constraint file, zero overhead, performance, FPGA, place and route, IP protection |
32 | Javier Valls, Martin Kuhlmann, Keshab K. Parhi |
Evaluation of CORDIC Algorithms for FPGA Design. |
J. VLSI Signal Process. |
2002 |
DBLP DOI BibTeX RDF |
FPGA, CORDIC, redundant arithmetic, Two's complement |
32 | Anna Antola, Mariagiovanna Sami, Vincenzo Piuri |
On-line Diagnosis and Reconfiguration of FPGA Systems. |
DELTA |
2002 |
DBLP DOI BibTeX RDF |
on-line detection, fault tolerance, FPGA, reconfiguration, diagnosis |
32 | Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian |
A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. |
J. Electron. Test. |
2001 |
DBLP DOI BibTeX RDF |
FPGA, test, ATPG |
32 | Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey |
Fast Run-Time Fault Location in Dependable FPGA-Based Applications. |
DFT |
2001 |
DBLP DOI BibTeX RDF |
Run-time fault location, Field-Programmable Gate Array (FPGA), concurrent error detection, on-line testing |
32 | Hojin Kee, Newton Petersen, Jacob Kornerup, Shuvra S. Bhattacharyya |
Systematic generation of FPGA-based FFT implementations. |
ICASSP |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Bryan S. Goda, John F. McDonald 0001 |
A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Kushal Datta, Ron Sass |
RBoot: Software Infrastructure for a Remote FPGA Laboratory. |
FCCM |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Wei-Kei Mak, C.-L. Lai |
On Constrained Pin-Mapping for FPGA-PCB Codesign. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Narashiman Chakravarthy, Jizhong Xiao |
FPGA-based Control System for Miniature Robots. |
IROS |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Fritz Mayer-Lindenberg |
Design and Application of a Scalable Embedded Systems' Architecture with an FPGA Based Operating Infrastucture. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou |
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Hayden Kwok-Hay So, Robert W. Brodersen |
Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Ángel Quirós-Olozábal, Ma de los Ángeles Cifredo Chacón, Diego Gomez Vela |
FPGA-Based Boundary-Scan Bist. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi |
Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller 0006 |
Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS - High Energy Physics Experiment. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Ryan J. Fong, Scott J. Harper, Peter M. Athanas |
A Versatile Framework for FPGA Field Updates: An Application of Partial Self-Reconfiguation. |
IEEE International Workshop on Rapid System Prototyping |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers |
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64. |
FCCM |
2002 |
DBLP DOI BibTeX RDF |
|
32 | V. Srinivasan, Sriram Govindarajan, Ranga Vemuri |
Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Parag K. Lala, Alvernon Walker |
An On-Line Reconfigurable FPGA Architecture. |
DFT |
2000 |
DBLP DOI BibTeX RDF |
|
32 | Brian Von Herzen |
Signal processing at 250 MHz using high-performance FPGA's. |
IEEE Trans. Very Large Scale Integr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
32 | Scott Hauck, Gaetano Borriello |
Pin assignment for multi-FPGA systems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
32 | Norman Margolus |
An FPGA architecture for DRAM-based systolic computations. |
FCCM |
1997 |
DBLP DOI BibTeX RDF |
|
32 | Steven Trimberger, Dean Carberry, Anders Johnson, Jennifer Wong |
A time-multiplexed FPGA. |
FCCM |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Kenneth M. Zick, John P. Hayes |
On-line sensing for healthier FPGA systems. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
on-line sensing, physically-adaptive computing., fpgas, reliability, process variation, leakage, temperature, dynamic power, ring oscillator, static power, health management |
31 | Hidenori Matsubayashi, Shinsuke Nino, Toru Aramaki, Yuichiro Shibata, Kiyoshi Oguri |
Retrieving 3-d information with FPGA-based stream processing. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
template matching, stream processing, stereo matching |
31 | Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton |
A synthesizable datapath-oriented embedded FPGA fabric. |
FPGA |
2007 |
DBLP DOI BibTeX RDF |
embedded block, field programmable gate array, system-on-chip, synthesis, integrated circuit, datapath |
31 | Michael P. Gilroy, James Irvine 0001, William Berrie |
FPGA based RAID 6 hardware accelerator. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Welson Sun, Michael J. Wirthlin, Stephen Neuendorffer |
Combining module selection and resource sharing for efficient FPGA pipeline synthesis. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
resource sharing, pipeline scheduling, module selection, data-path synthesis |
31 | Yong-Gang Wang, Tian-Xin Yan |
Design and implementation of packet classification with FPGA (abstract only). |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee |
SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only). |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Chao-Yang Yeh, Malgorzata Marek-Sadowska |
Skew-programmable clock design for FPGA and skew-aware placement. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
clock architecture, skew optimization, placement |
31 | Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry |
A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only). |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Rohini Krishnan, R. I. M. P. Meijer, Durand Guillaume |
Energy-efficient FPGA interconnect architecture design (abstract only). |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Roman Bartosinski, Martin Danek, Petr Honzík, Rudolf Matousek |
Dynamic reconfiguration in FPGA-based SoC designs (abstract only). |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Martin Danek, Josef Kolár |
FPGA modelling for high-performance algorithms. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee |
An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Paul Berube, José Nelson Amaral, Mike H. MacGregor |
An FPGA prototype for the experimental evaluation of a multizone network cache. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
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