Search results for "layout"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Ming-Chung Chen, Ting-Fang Wu	An Alternative Chinese Keyboard Layout Design for Single-Digit Typists.	ICCHP	2006	DBLP DOI BibTeX RDF
26	Esra E. Aleisa, Li Lin 0007	For effective facilities planning: layout optimization then simulation, or vice versa?	WSC	2005	DBLP DOI BibTeX RDF
26	Ulrik Brandes, Daniel Fleischer, Thomas Puppe	Dynamic Spectral Layout of Small Worlds.	GD	2005	DBLP DOI BibTeX RDF
26	Qinghua Liu, Malgorzata Marek-Sadowska	Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement.	ICCD	2005	DBLP DOI BibTeX RDF
26	Cristiano Lazzari, Lorena Anghel, Ricardo A. L. Reis	On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study.	IOLTS	2005	DBLP DOI BibTeX RDF
26	Jae-Gon Kim, Marc Goetschalckx	A Mixed Integer Programming Model for Modifying a Block Layout to Facilitate Smooth Material Flows.	ICCSA (4)	2005	DBLP DOI BibTeX RDF
26	Rajeev Murgai	Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering.	VLSI Design	2005	DBLP DOI BibTeX RDF
26	Mikko Pohja, Petri Vuorimaa	CSS Layout Engine for Compound Documents.	LA-WEB	2005	DBLP DOI BibTeX RDF
26	Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen	Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models.	DATE	2004	DBLP DOI BibTeX RDF
26	Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi	Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting.	ASP-DAC	2004	DBLP DOI BibTeX RDF
26	Christian Seybold, Martin Glinz, Silvio Meier, Nancy Merlo-Schett	An Effective Layout Adaptation Technique for a Graphical Modeling Tool.	ICSE	2003	DBLP DOI BibTeX RDF
26	Maciej J. Ciesielski, Serkan Askar, Samuel Levitin	Analytical approach to layout generation of datapath cells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
26	Francesca Cesarini, Simone Marinai, Giovanni Soda	Retrieval by Layout Similarity of Documents Represented with MXY Trees.	Document Analysis Systems	2002	DBLP DOI BibTeX RDF
26	Donato Malerba, Floriana Esposito, Oronzo Altamura	Adaptive Layout Analysis of Document Images.	ISMIS	2002	DBLP DOI BibTeX RDF
26	Thomas Kutzschebauch, Leon Stok	Layout Driven Decomposition with Congestion Consideration.	DATE	2002	DBLP DOI BibTeX RDF
26	Keith J. Keller, Hiroshi Takahashi, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu	Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
26	Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong 0001	On mask layout partitioning for electron projection lithography.	ICCAD	2002	DBLP DOI BibTeX RDF
26	Rituparna Mandal, Dibyendu Goswami, Arup Dash	Reducing Library Development Cycle Time through an Optimum Layout Create Flow.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
26	Toshinori Yamada, Nobuaki Fujii, Shuichi Ueno	On three-dimensional layout of pyramid networks.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
26	Chingwei Yeh, Yin-Shuin Kang	Cell-based layout techniques supporting gate-level voltage scaling for low power.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
26	Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, Mu-Chun Wang	Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process.	ISQED	2001	DBLP DOI BibTeX RDF
26	Chingwei Yeh, Yin-Shuin Kang	Cell-based layout techniques supporting gate-level voltage scaling for low power.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
26	Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky	Optimal phase conflict removal for layout of dark field alternatingphase shifting masks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
26	Mohamed Dessouky, Marie-Minerve Louërat, Jacky Porte	Layout-Oriented Synthesis of High Performance Analog Circuits.	DATE	2000	DBLP DOI BibTeX RDF
26	Fenghao Mu, Christer Svensson	A layout-based schematic method for very high-speed CMOS cell design.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
26	Jianying Hu, Ramanujan S. Kashi, Gordon T. Wilfong	Document Classification Using Layout Analysis.	DEXA Workshops	1999	DBLP DOI BibTeX RDF
26	Fenghao Mu, Christer Svensson	Methodology of layout based schematic and its usage in efficient high performance CMOS design.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
26	Bulent Basaran, Kiran Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, Srinivasan Rangarajan, Naresh Sehgal	GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs.	VLSI Design	1999	DBLP DOI BibTeX RDF
26	Pradip K. Kar, Subir K. Roy	TECHMIG: A Layout Tool for Technology Migration.	VLSI Design	1999	DBLP DOI BibTeX RDF
26	Toyohide Watanabe, Xiaoou Huang	Automatic Acquisition of Layout Knowledge for Understanding Business Cards.	ICDAR	1997	DBLP DOI BibTeX RDF
26	Chiu-sing Choy, Tsz-Shing Cheung, Kam-Keung Wong	Incremental layout placement modification algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
26	Eser Kandogan, Ben Shneiderman	Elastic windows: improved spatial layout and rapid multiple window operations.	AVI	1996	DBLP DOI BibTeX RDF	elastic windows, multi-window operations, personal role manager, CAD, programming environment, window manager, task switching
26	Per Andersson, Lars H. Philipson	Interaction semantics of a symbolic layout editor for parameterized modules.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
26	Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu	Layout placement for sliced architecture.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
26	K. P. Ta, T. C. Tan	Layout Algorithms for DFD Processors.	SEKE	1992	DBLP DOI BibTeX RDF
26	Renato Capra	3D Layout Manipulation Functions with a Glance to Optimization Problems.	APL	1992	DBLP DOI BibTeX RDF	APL
26	Bradley S. Carlson, C. Y. Roger Chen, Uminder Singh	Optimal cell generation for dual independent layout styles.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
26	Robert L. Maziasz, John P. Hayes	Layout optimization of static CMOS functional cells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
26	William W. Pugh, Grant E. Weddell	Two-Directional Record Layout for Multiple Inheritance.	PLDI	1990	DBLP DOI BibTeX RDF
26	Magdy S. Abadir, Jack Ferguson	An improved layout verification algorithm (LAVA).	EURO-DAC	1990	DBLP DOI BibTeX RDF
26	Hong Cai, Ralph H. J. M. Otten	Conflict-free channel definition in building-block layout.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
26	David Marple	Transistor Size Optimization in the Tailor Layout System.	DAC	1989	DBLP DOI BibTeX RDF
26	Ichiang Lin, David Hung-Chang Du, Steve H.-C. Yen	Gate Matrix Layout Synthesis with Two-Dimensional Folding.	DAC	1989	DBLP DOI BibTeX RDF
26	M. T. Trick, Stephen W. Director	LASSIE: Structure to Layout for Behavioral Synthesis Tools.	DAC	1989	DBLP DOI BibTeX RDF
26	David Marple, Michiel Smulders, Henk Hegen	An Efficient Compactor for 45° Layout.	DAC	1988	DBLP BibTeX RDF
26	Y.-C. Chang, S. C. Chang, L.-H. Hsu	Automated Layout Generation Using Gate Matrix Approach.	DAC	1987	DBLP DOI BibTeX RDF
26	Edward J. DeJesus, James P. Callan, Curtis R. Whitehead	PEARL: an expert system for power supply layout.	DAC	1986	DBLP DOI BibTeX RDF
26	Michelangelo Ceci, Margherita Berardi, G. Porcelli, Donato Malerba	A Data Mining Approach to Reading Order Detection.	ICDAR	2007	DBLP DOI BibTeX RDF
26	I. Scott MacKenzie, Janet C. Read	Using paper mockups for evaluating soft keyboard layouts.	CASCON	2007	DBLP DOI BibTeX RDF
26	Lihong Zhang, Ulrich Kleine, Yingtao Jiang	An automated design tool for analog layouts.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
26	Amit Kumar 0022, Noriyuki Miura, Muhammad Muqsith, Tadahiro Kuroda	Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication.	VLSI Design	2006	DBLP DOI BibTeX RDF
26	Martyn Taylor, Peter Rodgers 0001	Applying Graphical Design Techniques to Graph Visualisation.	IV	2005	DBLP DOI BibTeX RDF
26	Peter Becker 0002	Using Intermediate Representation Systems to Interact with Concept Lattices.	ICFCA	2005	DBLP DOI BibTeX RDF
26	Sarit Kraus, Alexander Kröner, Lea Tsaban	IMAP - Intelligent Multimedia Authoring Tools for Electronic Publishing.	AH	2002	DBLP DOI BibTeX RDF
26	Siu-Cheung Chau, Ada Wai-Chee Fu	A Gracefully Degradable Declustered RAID Architecture with near Optimal Maximal Read and Write Parallelism.	CLUSTER	2000	DBLP DOI BibTeX RDF	Declustered RAID, Fault-Tolerant, RAID, Disk Arrays
26	Takeshi Tokuda, Jiro Korematsu, Yukihiko Shimazu, Narumi Sakashita, Tohru Kengaku, Toshiki Fugiyama, Takio Ohno, Osamu Tomisawa	A macrocell approach for VLSI processor design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
24	Windsor W. Hsu, Alan Jay Smith, Honesty C. Young	The automatic improvement of locality in storage systems.	ACM Trans. Comput. Syst.	2005	DBLP DOI BibTeX RDF	block layout, defragmentation, disk technology trends, locality improvement, prefetching, data reorganization, data restructuring, Data layout optimization
24	Avaneendra Gupta, John P. Hayes	Width minimization of two-dimensional CMOS cells using integer programming.	ICCAD	1996	DBLP DOI BibTeX RDF	leaf cell synthesis, two-dimensional layout, diffusion sharing, transistor chains, CMOS networks, Layout optimization, module generation
24	Prathima Agrawal, Balakrishnan Narendran, Narayanan Shivakumar	Multi-way partitioning of VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	multi-way partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric
24	Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya	Geometric bipartitioning problem and its applications to VLSI.	VLSI Design	1996	DBLP DOI BibTeX RDF	geometric bipartitioning problem, layout design, rectilinear modules, staircase, monotone increasing, classical graph bisection problem, weighted permutation graph, integer edge weights, designated nodes, absolute value, edge weights, routing, computational complexity, VLSI, VLSI, graph theory, NP-complete, branch-and-bound, floorplan, heuristic algorithm, search problems, geometry, network routing, circuit layout CAD, hierarchical decomposition
24	Alexander Dalal, Lavi Lev, Sundari Mitra	Design of an efficient power distribution network for the UltraSPARC-I microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	computer power supplies, UltraSPARC-I, simulation method, exact layout locations, excessive voltage drop, floorplanning constraints, power interconnections, reduced time-to-market, circuit analysis computing, circuit layout CAD, microprocessor chips, electromigration, CAD tools, power distribution network
23	Mona Haraty, Syavash Nobarany, Steve DiPaola, Brian D. Fisher	AdWiL: adaptive windows layout manager.	CHI Extended Abstracts	2009	DBLP DOI BibTeX RDF	creativity, layout, visual analytics, flow, windows management
23	Rintaro Miyazaki, Ryo Momose, Hideyuki Shibuki, Tatsunori Mori	Using web page layout for extraction of sender names.	IUCS	2009	DBLP DOI BibTeX RDF	sender name, web page layout, natural language processing, information credibility
23	Daniele Rossi 0001, André K. Nieuwland, Cecilia Metra	Simultaneous Switching Noise: The Relation between Bus Layout and Coding.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	bus layout, switching patterns, system reliability, IC, power supply network, simultaneous switching noise, coding techniques
23	Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	layout, body bias
23	Krishnan Sundaresan, Nihar R. Mahapatra	Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses.	ISQED	2008	DBLP DOI BibTeX RDF	Bus Energy, Self Heating, Wire Permutation, Optimization, Interconnect, Layout, Temperature, On-Chip Bus
23	Edward W. Ishak, Steven Feiner	Content-aware layout.	CHI Extended Abstracts	2007	DBLP DOI BibTeX RDF	layout, transparency, scrolling, window manager, fisheye, content-aware
23	Nuno C. Lourenço, Nuno C. G. Horta	Automatic analog IC layout generation based on a evolutionary computation approach.	GECCO	2007	DBLP DOI BibTeX RDF	analog ICs, layout generation, evolutionary computation
23	Peter Reid, Fred Hallett-Hook, Beryl Plimmer, Helen C. Purchase	Applying layout algorithms to hand-drawn graphs.	OZCHI	2007	DBLP DOI BibTeX RDF	tablet PC, sketch tools, layout algorithms
23	Chir-Ho Chang, Jin-Ling Lin	A Systematic Layout Planning of Visualizing Devices on a Non-rectangular Plane by Genetic Heuristics.	IEA/AIE	2007	DBLP DOI BibTeX RDF	Layout Planning, Genetic Algorithm, RFID, Heuristic Rules
23	Henriette Bier, Adriaan de Jong, Gijs van der Hoorn, Niels Brouwers, Marijn Heule, Hans van Maaren	Prototypes for Automated Architectural 3D-Layout.	VSMM	2007	DBLP DOI BibTeX RDF	3D-Modeling and Automated Spatial Layout, Euclidean and Non-Euclidean Ge ometries, Satisfiability
23	Jie Zou, Daniel X. Le, George R. Thoma	Combining DOM tree and geometric layout analysis for online medical journal article segmentation.	JCDL	2006	DBLP DOI BibTeX RDF	HTML document segmentation, document object model (DOM), web information retrieval, document layout analysis
23	Christian Klukas, Falk Schreiber, Henning Schwöbbermeyer	Coordinated perspectives and enhanced force-directed layout for the analysis of network motifs.	APVIS	2006	DBLP DOI BibTeX RDF	coordinated perspectives, graph drawing, network analysis, multiple views, information visualisation, network motifs, force-directed layout
23	Xing Xie 0001, Chong Wang 0002, Li-Qun Chen, Wei-Ying Ma	An adaptive web page layout structure for small devices.	Multim. Syst.	2005	DBLP DOI BibTeX RDF	Slicing tree, Mobile device, Web browsing, Layout optimization, Adaptive content delivery
23	David R. Wood	Minimising the Number of Bends and Volume in 3-Dimensional Orthogonal Graph Drawings with a Diagonal Vertex Layout.	Algorithmica	2004	DBLP DOI BibTeX RDF	Diagonal layout, Vertex-ordering, Book embedding, Graph drawing, Dimensional, Orthogonal
23	Sheelagh Carpendale, Anand Agarawala	PhylloTrees: Harnessing Nature's Phyllotactic Patterns for Tree Layout.	INFOVIS	2004	DBLP DOI BibTeX RDF	phyllotactic patterns, information visualization, Graph layout, tree visualization
23	Goeran Jerke, Jens Lienig, Jürgen Scheible	Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs.	DAC	2004	DBLP DOI BibTeX RDF	decompaction, layout decomposition, physical design, compaction, electromigration, interconnect reliability
23	Steven J. Harrington, J. Fernando Naveda, Rhys Price Jones, Paul G. Roetling, Nishant Thakkar	Aesthetic measures for automated document layout.	ACM Symposium on Document Engineering	2004	DBLP DOI BibTeX RDF	document, layout, aesthetics
23	Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu	An algebraic multigrid solver for analytical placement with layout based clustering.	DAC	2003	DBLP DOI BibTeX RDF	algebraic multigrid method, layout based clustering, analytical placement
23	James Burns, Jean-Luc Gaudiot	SMT Layout Overhead and Scalability.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	layout area estimation, microarchitecture trade-off, processor architecture, SMT
23	David Harel, Gregory Yashchin	An algorithm for blob hierarchy layout.	Vis. Comput.	2002	DBLP DOI BibTeX RDF	Higraph, Hierarchy, Layout, Statechart, Aesthetics
23	Katsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka	Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	automatic fault tracing system, EB tester, CAD layout, VLSI
23	Timothy K. Shih, Anthony Y. Chang	A schedule/layout computation model.	RTCSA	1997	DBLP DOI BibTeX RDF	schedule/layout computation model, temporal intervals, temporal relation compositions, temporal relation algebraic system, virtual reality timing constraints, virtual reality, time constraints, multimedia presentations, multimedia documents
23	Jason Cong, Cheng-Kok Koh	Interconnect layout optimization under higher-order RLC model.	ICCAD	1997	DBLP DOI BibTeX RDF	RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization
23	Kanad Chakraborty, Pinaki Mazumder	An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards.	ICCAD	1996	DBLP DOI BibTeX RDF	bus-layout, bussed driver shorts, early diagnosis, field survivability, interconnect shorts, production yield, printed circuit boards, printed circuit testing
23	Nalini K. Ratha, Anil K. Jain 0001, Diane T. Rover	FPGA-based high performance page layout segmentation.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	Splash 2, page layout segmentation algorithm, FPGA array processor, Xilinx synthesis tool, 5 GHz, 1024 pixel, field programmable gate arrays, image segmentation, parallel processing, text
23	Chienhua Chen, Dharma P. Agrawal, J. Richard Burke	dBCube: A New Class of Hierarchical Multiprocessor Interconnection Networks with Area Efficient Layout.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	dBCube, hierarchical multiprocessor interconnection networks, area efficient layout, node connectivity, compound graph, necklace, performance evaluation, VLSI, graphs, hypercube, multiprocessor interconnection networks, hierarchical networks, wafer scale integration, de Bruijn graph, hypercube topology, Communication locality
23	R. Burgess, C. Wouters	PARAGON: a new package for gate matrix layout synthesis.	EURO-DAC	1990	DBLP DOI BibTeX RDF	cell generation, gate-matrix layout, routing, simulated annealing, optimisation, placement, logic synthesis, physical design
23	Subhas C. Nandy, Bhargab B. Bhattacharya, Sibabrata Ray	Efficient algorithms for Identifying All Maximal Isothetic Empty Rectangles in VLSI Layout Design.	FSTTCS	1990	DBLP DOI BibTeX RDF	interval trees, complexity, Computational geometry, placement, VLSI layout, geometric algorithms
23	Jinseong Jeon, Keoncheol Shin, Hwansoo Han	Abstracting access patterns of dynamic memory using regular expressions.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	field affinity, layout transformation, pool allocation, regular expressions, Access patterns
23	Helen C. Purchase, Amanjit Samra	Extremes Are Better: Investigating Mental Map Preservation in Dynamic Graphs.	Diagrams	2008	DBLP DOI BibTeX RDF	Dynamic graph layout, empirical study, mental map
23	Cameron L. McCormack, Kim Marriott, Bernd Meyer 0001	Authoring adaptive diagrams.	ACM Symposium on Document Engineering	2008	DBLP DOI BibTeX RDF	authoring, diagrams, adaptive layout
23	Tim Dwyer, Kim Marriott	Constrained Stress Majorization Using Diagonally Scaled Gradient Projection.	GD	2007	DBLP DOI BibTeX RDF	constraints, graph layout
23	Liying Wang, Wei Hua, Hujun Bao	Procedural Modeling of Residential Zone Subject to Urban Planning Constraints.	ICEC	2007	DBLP DOI BibTeX RDF	constrained layout optimization, Procedural modeling, urban planning
23	Mehrdad Najibi, Kamran Saleh, Hossein Pedram	Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	quasi-delay insensitive, standard-cell layout, asynchronous circuits
23	Alexander J. Macdonald, David F. Brailsford, Steven R. Bagley, John William Lumley	Speculative document evaluation.	ACM Symposium on Document Engineering	2007	DBLP DOI BibTeX RDF	VDP, speculative evaluation, optimisation, SVG, document layout, PPML
23	Kim Marriott, Peter Moulder, Nathan Hurst	Automatic float placement in multi-column documents.	ACM Symposium on Document Engineering	2007	DBLP DOI BibTeX RDF	floating figure, multi-column layout, optimization techniques
23	Yingxin Wu 0001, Masahiro Takatsuka	Visualizing multivariate network on the surface of a sphere.	APVIS	2006	DBLP DOI BibTeX RDF	GeoSOM, circular layout, multivariate network, information visualization, graph drawing
23	M. Monemizadeh, Hamid Sarbazi-Azad	The necklace-hypercube: a well scalable hypercube-based interconnection network for multiprocessors.	SAC	2005	DBLP DOI BibTeX RDF	necklace-hypercube, routing, interconnection networks, broadcast, hypercube, VLSI layout, topological properties
23	Jack Kustanowitz, Ben Shneiderman	Meaningful presentations of photo libraries: rationale and applications of bi-level radial quantum layouts.	JCDL	2005	DBLP DOI BibTeX RDF	layout generation, photo management, visual presentation, user interfaces, digital libraries