Search results for "pipelining"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Won So, Alexander G. Dean	Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP.	CASES	2006	DBLP DOI BibTeX RDF	TI C6000, static profitability estimation, DSP, software pipelining, VLIW, iterative compilation, software thread integration
20	Seongmoo Heo, Krste Asanovic	Replacing global wires with an on-chip network: a power analysis.	ISLPED	2005	DBLP DOI BibTeX RDF	on-chip network power model, tile size, wire power model, pipelining, router, tiled architecture
20	Mario R. Casu, Luca Macchiarulo	Floorplanning for throughput.	ISPD	2004	DBLP DOI BibTeX RDF	systems-on-chip, throughput, floorplanning, wire pipelining
20	Masaru Takesue	A Model of Pipelined Mutual Exclusion on Cache-Coherent Multiprocessors.	Euro-Par	2003	DBLP DOI BibTeX RDF	Models, pipelining, mutual exclusion
20	Luis Díaz de Cerio, Miguel Valero-García, Antonio González 0001	Hypercube Algorithms on Mesh Connected Multicomputers.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	mesh interconnected multicomputers, standard embedding, communication pipelining, message-scheduling algorithms, Mapping algorithms, complete exchange, hypercube algorithms
20	Jason Cong	Timing closure based on physical hierarchy.	ISPD	2002	DBLP DOI BibTeX RDF	interconnect planning, logic hierarchy, physical hierarchy, retiming and pipelining, sequential arrival time, interconnect optimization, timing closure, multilevel optimization
20	Bin Xiao 0001, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge	Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops.	ISSS	2002	DBLP DOI BibTeX RDF	rotation scheduling, software pipelining, retiming, unfolding
20	Hongbo Yang, Guang R. Gao, Clement Leung	On achieving balanced power consumption in software pipelined loops.	CASES	2002	DBLP DOI BibTeX RDF	power-aware compilation, instruction level parallelism, software pipelining
20	Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri	Framework for Synthesis of Virtual Pipelines.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Virtual Pipeline, SLAAC-1V board, JHDL, FPGAs, Pipelining, Dynamic Reconfiguration, Partial Reconfiguration
20	M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas	The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays.	ISCA	2002	DBLP DOI BibTeX RDF	instruction queue clock rate, Pipelining
20	Steve Haynal, Forrest Brewer	Automata-Based Symbolic Scheduling for Looping DFGs.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Scheduling, high-level synthesis, automata, Binary Decision Diagrams, nondeterminism, loop pipelining, symbolic model
20	Josep Llosa, Eduard Ayguadé, Antonio González 0001, Mateo Valero, Jason Eckhardt	Lifetime-Sensitive Modulo Scheduling in a Production Environment.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	register requirements, software pipelining, VLIW, instruction scheduling, loop scheduling, Fine grain parallelism, superscalar architectures
20	Sergey Melnik 0001, Sriram Raghavan, Beverly Yang, Hector Garcia-Molina	Building a distributed full-text index for the web.	ACM Trans. Inf. Syst.	2001	DBLP DOI BibTeX RDF	Embedded databases, Pipelining, Text retrieval, Inverted files, Distributed indexing
20	U. Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee	An algorithm for synthesis of large time-constrained heterogeneous adaptive systems.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	delay/cost table, hierarchical control data-flow graph, time-constrained synthesis, pipelining, reconfigurable computing, mixed integer linear programming, list scheduling
20	Jörg Ritter 0002, Paul Molitor	A pipelined architecture for partitioned DWT based lossy image compression using FPGA's.	FPGA	2001	DBLP DOI BibTeX RDF	embedded zero tree coding, FPGA, field programmable gate arrays, architecture, wavelet transformation, pipelining, Xilinx, lossy image compression
20	Federico Silla, José Duato	On the Use of Virtual Channels in Networks of Workstations with Irregular Topology.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	block multiplexing, channel pipelining, flow control, Networks of workstations, virtual channels, wormhole switching, irregular topology
20	Montek Singh, Steven M. Nowick	High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths.	ASYNC	2000	DBLP DOI BibTeX RDF	fine-grain pipelining, VLSI, pipelines, asynchronous, dynamic logic, FIFO, high-throughput, digital design
20	Herbert Leitold, Wolfgang Mayerwieser, Udo Payer, Karl C. Posch, Reinhard Posch, Johannes Wolkerstorfer	A 155 Mbps Triple-DES Network Encryptor.	CHES	2000	DBLP DOI BibTeX RDF	DES algorithm, cipher block chaining, true single-phase logic, full-custom design, Network security, pipelining, encryption, Triple-DES
20	Johann Großschädl	The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip.	ACSAC	2000	DBLP DOI BibTeX RDF	RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency
20	Dolors Royo, Antonio González 0001, Miguel Valero-García	Low Communication Overhead Jacobi Algorithms for Eigenvalues Computation on Hypercubes.	J. Supercomput.	1999	DBLP DOI BibTeX RDF	eigenproblem, Jacobi ordering, CC-cube algorithms, communication pipelining, one port architecture, multiple port architecture, hamiltonian path
20	Tao Yang 0009, Cong Fu 0002	Heuristic Algorithms for Scheduling Iterative Task Computations on Distributed Memory Machines.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	iterative task graphs, Scheduling, directed acyclic graphs, software pipelining, granularity, communication optimization
20	Hui-I Hsiao, Ming-Syan Chen, Philip S. Yu	Parallel Execution of Hash Joins in Parallel Databases.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	Hash filters, bushy trees, pipelining, hash joins
20	F. Jesús Sánchez, Antonio González 0001	Cache Sensitive Modulo Scheduling.	MICRO	1997	DBLP DOI BibTeX RDF	VLIW machines, Software pipelining, software prefetching, locality analysis
20	Seongbae Park, SangMin Shim, Soo-Mook Moon	Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed.	MICRO	1997	DBLP DOI BibTeX RDF	SPARC-based VLIW testbed, VLIW microprocessors, Very Long Instruction Word microprocessors, all-path speculation, gcc-generated optimized SPARC code, high-performance VLIW code, nongreedy enhanced pipeline scheduling, nonspeculative operations, profile-based all-path speculation, restricted speculative loads, scheduling compiler, speculative operations, trace-based speculation, performance, compiler, computer architecture, parallel machines, software pipelining, loop unrolling, renaming, memory disambiguation, copies, scheduling techniques
20	Chih-Tung Chen, Kayhan Küçükçakar	High-level scheduling model and control synthesis for a broad range of design applications.	ICCAD	1997	DBLP DOI BibTeX RDF	multi-phase clocking, relative scheduling, architectural power optimization, high-level synthesis, pipelining, multi-threading, behavioral synthesis, control synthesis, architectural synthesis, scheduling model
20	Manuel Sánchez, Juan López, Oscar G. Plata, Emilio L. Zapata	An efficient architecture for the in place fast cosine transform.	ASAP	1997	DBLP DOI BibTeX RDF	in place fast cosine transform, image encoding, inverse cosine transform, locality, pipelining, image compression, discrete cosine transforms, DCT, VLSI implementation
20	Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma 0011	A strategy for determining a Jacobi specific dataflow processor.	ASAP	1997	DBLP DOI BibTeX RDF	Jacobi specific dataflow processor, Jacobi algorithms, real-lime adaptive signal processing applications, quasi regularity property, dependence graph representations, exploration iteration, processor template, mapper, hierarchical exploration method, mapping efficiency, lookahead techniques, pipelining, retiming, adaptive signal processing, application domain, array processing
20	Sissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Nelson L. Passos	Probabilistic Rotation: Scheduling Graphs with Uncertain Execution Time.	ICPP	1997	DBLP DOI BibTeX RDF	Scheduling, probability, software pipelining, rotation, data-flow graph
20	James D. Allen, David E. Schimmel	Issues in the Design of High Performance SIMD Architectures.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	MasPar, caches, pipelining, SIMD, data parallel
20	Joseph G. Peters, Michel Syska	Circuit-Switched Broadcasting in Torus Networks.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	circuit-switched routing, Broadcasting, pipelining, tilings, torus networks
20	Val Donaldson, Jeanne Ferrante	Determining Asynchronous Acyclic Pipeline Execution Times.	IPPS	1996	DBLP DOI BibTeX RDF	asynchronous pipelining, parallel execution time, loop parallelism, task graph scheduling, pipeline scheduling
20	Ching-Long Su, Yin-Tsung Hwang	Distributed arithmetic-based architectures for high speed IIR filter design.	ICPADS	1996	DBLP DOI BibTeX RDF	high speed IIR filter, pipelining techniques, SPDM technology, parallel processing, parallel architectures, digital arithmetic, recursion, recursive filters, Distributed Arithmetic, IIR filters, DSP applications
20	S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri	A VLSI chip for image compression using variable block size segmentation.	ICCD	1996	DBLP DOI BibTeX RDF	variable block size segmentation, VBSS scheme, variable size blocks, redundancy features, maximum compression, nearest neighbor communication, CMOS VLSI chip, image characteristics extraction subsystem, Cadence design tools, VLSI, parallelism, pipelining, image compression, VLSI architecture, VLSI implementation, lossless image compression, VLSI chip, coding techniques
20	Miodrag Potkonjak	Discrete-relaxation-based heuristic techniques for video algorithm/architecture matching and system level transformations.	ICIP	1995	DBLP DOI BibTeX RDF	discrete-relaxation-based heuristic techniques, video algorithm, system level transformations, computational transformations, throughput performance, iterative heuristic approach, behavioral transformations, rephasing, architecture matching, computational complexity, image processing, VLSI, pipelining, iterative methods, pipeline processing, retiming, integrated circuit design, system level design, video processing, video signal processing, heuristic programming, digital signal processing chips, circuit optimisation, throughput optimization
20	Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington	A high performance bus and cache controller for PowerPC multiprocessing systems.	ICCD	1995	DBLP DOI BibTeX RDF	high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
20	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray	Concurrent timing optimization of latch-based digital systems.	ICCD	1995	DBLP DOI BibTeX RDF	concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
20	Jayesh Siddhiwala, Liang-Fang Chao	Scheduling conditional data-flow graphs with resource sharing.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	conditional data-flow graphs, resource sharing algorithm, pipeline scheduling algorithms, loop constructs, condition vector, dynamic resource sharing, rotation scheduling technique, parallel algorithms, data structures, data structure, resource allocation, high level synthesis, high level synthesis, processor scheduling, pipeline processing, data flow graphs, loop pipelining, conditional branches
20	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
20	Debabrata Ghosh, Soumitra Kumar Nandy	Wave pipelined architecture folding: a method to achieve low power and low area.	VLSI Design	1995	DBLP DOI BibTeX RDF	wave pipelined architecture folding, clock-free wave pipelining scheme, chip area reduction, VLSI, low power design, logic design, pipeline processing, integrated circuit design, digital integrated circuits
20	Anne Rogers, Keshav Pingali	Compiling for Distributed Memory Architectures.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	processdecomposition, locality ofreference, run-time resolution, message traffic, hydrodynamicsbenchmark, Intel iPSC/2, load balancing, parallel programming, synchronization, pipelining, synchronisation, program compilers, distributed memory systems, parallelizing compiler, pipeline processing, high-level languages, distributed memory architectures, SIMPLE
20	Vikram S. Adve, Mary K. Vernon	Performance Analysis of Mesh Interconnection Networks with Deterministic Routing.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	mesh interconnection networks, single-hit buffers, infinite buffers, nonadaptive deadlock-free routing scheme, closedqueueing network, message blocking, message pipelining, arbitrary source-destinationprobability distribution, 2D networks, shared-memory traffic, two dimensional network, performance evaluation, performance analysis, concurrency control, probability, multiprocessor interconnection networks, queueing theory, wormhole routing, network routing, virtual channels, deterministic routing, k-ary n-cube networks, deadlock-free routing algorithm, performance issues
20	Daniel H. Linder, James C. Harden	Access Graphs: A Model for Investigating Memory Consistency.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	access pipelining, synchronization, caches, computer architecture, computer architectures, synchronisation, shared memory systems, memory consistency, massively parallel systems
20	Michel Dubois 0001, Christoph Scheurich	Memory Access Dependencies in Shared-Memory Multiprocessors.	IEEE Trans. Software Eng.	1990	DBLP DOI BibTeX RDF	memory access dependencies, logical concurrency model, pipelining, multiprocessing systems, rules, shared-memory multiprocessors, multiprogramming, storage allocation, multiprocessor architectures, private caches
20	Zhiwei Xu, Kai Hwang 0001	Molecule: A Language Construct for Layered Development of Parallel Programs.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	layered development, molecule type, computation mode, layered software development, iPSC, application flexibility, algorithms, parallel programs, parallel programming, parallel computers, pipelining, multicomputer, dataflow, high-level languages, multiprocessing, sequential, array processing, user friendliness, language construct, procedural language, PAL
15	Shanthi Pavan, Saravana Manivannan, Nishanth Basavaraj	Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
15	Athina Georgara, Raman Kazhamiakin, Ornella Mich, Alessio Palmero Aprosio, Jean-Christophe R. Pazzaglia, Juan Antonio Rodríguez-Aguilar, Carles Sierra	Correction to: The AI4Citizen pilot: Pipelining AI-based technologies to support school-work alternation programmes.	Appl. Intell.	2024	DBLP DOI BibTeX RDF
15	Masaki Arai, Naoto Fukumoto, Hitoshi Murai	Introducing software pipelining for the A64FX processor into LLVM.	HPC Asia Workshops	2024	DBLP DOI BibTeX RDF
15	Zili Zhang, Fangyue Liu, Gang Huang 0001, Xuanzhe Liu, Xin Jin 0008	Fast Vector Query Processing for Large Datasets Beyond GPU Memory with Reordered Pipelining.	NSDI	2024	DBLP BibTeX RDF
15	Rahma Nouaji, Stella Bitchebe, Oana Balmau	SpeedyLoader: Efficient Pipelining of Data Preprocessing and Machine Learning Training.	EuroMLSys@EuroSys	2024	DBLP DOI BibTeX RDF
15	Nicolai Fiege, Peter Zipf	BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining.	ACM Trans. Reconfigurable Technol. Syst.	2023	DBLP DOI BibTeX RDF
15	Delia Velasco-Montero, Bart Goossens, Jorge Fernández-Berni, Ángel Rodríguez-Vázquez, Wilfried Philips	A Pipelining-Based Heterogeneous Scheduling and Energy-Throughput Optimization Scheme for CNNs Leveraging Apache TVM.	IEEE Access	2023	DBLP DOI BibTeX RDF
15	Daeyeon Kim, Heonchoel Lee, Hyuck-Hoon Kwon, Yeji Hwang, Wonseok Choi 0005	Parallelized Particle Filter With Efficient Pipelining on FPGA for Real-Time Ballistic Target Tracking.	IEEE Access	2023	DBLP DOI BibTeX RDF
15	Cihat Keçeci, Mohammad Shaqfeh, Fawaz S. Al-Qahtani, Muhammad Ismail 0001, Erchin Serpedin	Clustered Scheduling and Communication Pipelining for Efficient Resource Management of Wireless Federated Learning.	IEEE Internet Things J.	2023	DBLP DOI BibTeX RDF
15	Yimin Zhuang, Xing Hu 0001, Xiaobing Chen, Tian Zhi	DyPipe: A Holistic Approach to Accelerating Dynamic Neural Networks with Dynamic Pipelining.	J. Comput. Sci. Technol.	2023	DBLP DOI BibTeX RDF
15	Xiaoyu Yu	Genofunc: genome annotation and identification of genome features for automated pipelining analysis of virus whole genome sequences.	BMC Bioinform.	2023	DBLP DOI BibTeX RDF
15	Ziying Ni, Ayesha Khalid, Dur-e-Shahwar Kundi, Máire O'Neill, Weiqiang Liu 0001	HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
15	Jingzhe Guo, Mingsheng Ying	Software Pipelining for Quantum Loop Programs.	IEEE Trans. Software Eng.	2023	DBLP DOI BibTeX RDF
15	Argyrios Sideris, Minas Dasygenis	Enhancing the Hardware Pipelining Optimization Technique of the SHA-3 via FPGA.	Comput.	2023	DBLP DOI BibTeX RDF
15	Mark Horeni, Siddharth Joshi	Improvements in Interlayer Pipelining of CNN Accelerators Using Genetic Algorithms.	CoRR	2023	DBLP DOI BibTeX RDF
15	Kingshuk Majumder, Uday Bondhugula	Automatic multi-dimensional pipelining for high-level synthesis of dataflow accelerators.	CoRR	2023	DBLP DOI BibTeX RDF
15	Athina Georgara, Raman Kazhamiakin, Ornella Mich, Alessio Palmero Aprosio, Jean-Christophe R. Pazzaglia, Juan Antonio Rodríguez-Aguilar, Carles Sierra	The AI4Citizen pilot: Pipelining AI-based technologies to support school-work alternation programmes.	Appl. Intell.	2023	DBLP DOI BibTeX RDF
15	Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos	ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining.	DATE	2023	DBLP DOI BibTeX RDF
15	Yifan Yang, Joel S. Emer, Daniel Sánchez 0003	ISOSceles: Accelerating Sparse CNNs through Inter-Layer Pipelining.	HPCA	2023	DBLP DOI BibTeX RDF
15	Zeqian Dong, Qiang He 0001, Feifei Chen 0001, Hai Jin 0001, Tao Gu, Yun Yang 0001	EdgeMove: Pipelining Device-Edge Model Training for Mobile Intelligence.	WWW	2023	DBLP DOI BibTeX RDF
15	Liang Yuan, Qiang He 0001, Feifei Chen 0001, Ruihan Dou, Hai Jin 0001, Yun Yang 0001	PipeEdge: A Trusted Pipelining Collaborative Edge Training based on Blockchain.	WWW	2023	DBLP DOI BibTeX RDF
15	Shaohuai Shi, Xinglin Pan, Xiaowen Chu 0001, Bo Li 0001	PipeMoE: Accelerating Mixture-of-Experts through Adaptive Pipelining.	INFOCOM	2023	DBLP DOI BibTeX RDF
15	Siddhisanket Raskar, Thomas Applencourt, Kalyan Kumaran, Guang R. Gao	Codelet Pipe: Realization of Dataflow Software Pipelining for Extended Codelet Model.	ICPP Workshops	2023	DBLP DOI BibTeX RDF
15	Viktor Razilov, Juncen Zhong, Emil Matús, Gerhard P. Fettweis	Dual Vector Load for Improved Pipelining in Vector Processors.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
15	Yuke Wang, Boyuan Feng, Zheng Wang, Tong Geng, Kevin J. Barker, Ang Li 0006, Yufei Ding	MGG: Accelerating Graph Neural Networks with Fine-Grained Intra-Kernel Communication-Computation Pipelining on Multi-GPU Platforms.	OSDI	2023	DBLP BibTeX RDF
15	Lin Zhang, Shaohuai Shi, Xiaowen Chu 0001, Wei Wang 0030, Bo Li 0001, Chengjian Liu	DeAR: Accelerating Distributed Deep Learning with Fine-Grained All-Reduce Pipelining.	ICDCS	2023	DBLP DOI BibTeX RDF
15	Ryan Dutra de Abreu, Laura Silva de Assis, Douglas de O. Cardoso	Experimental Analysis of Pipelining Community Detection and Recommender Systems.	WEBIST	2023	DBLP DOI BibTeX RDF
15	Siddhisanket Raskar, Jose Manuel Monsalve Diaz, Thomas Applencourt, Kalyan Kumaran, Guang Gao	Implementation of Dataflow Software Pipelining for Codelet Model.	ICPE	2023	DBLP DOI BibTeX RDF
15	B. Naresh Kumar Reddy, K. Sarangam, Sushmita Dandeliya, S. Pavan Sai Naidu, Naveen Kumar P	Accelerating Sorting Performance on FPGA: Combining Quick Sort and Heap Sort through Hybrid Pipelining.	iSES	2023	DBLP DOI BibTeX RDF
15	Miyeon Lee, Inhwan Kim, Pureuna Shin, Hwayong Oh, Keewon Joe	Prediction-Reconstruction VLSI architecture with efficient pipelining for VVC Decoder.	ICCE	2023	DBLP DOI BibTeX RDF
15	Ian Healy, Peter Giordano, Wafa Elmannai	Branch Prediction in CPU Pipelining.	UEMCON	2023	DBLP DOI BibTeX RDF
15	Yuzuo Zhang, Xinyuan Tu, Lin Wang, Yuchong Hu, Fang Wang, Ye Wang	FullRepair: Towards Optimal Repair Pipelining in Erasure-Coded Clustered Storage Systems.	CLUSTER	2023	DBLP DOI BibTeX RDF
15	Liwei Guo, Wonkyo Choe, Felix Xiaozhu Lin	STI: Turbocharge NLP Inference at the Edge via Elastic Pipelining.	ASPLOS (2)	2023	DBLP DOI BibTeX RDF
15	Chengning Wang, Dan Feng 0001, Wei Tong 0001, Jingning Liu	CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays.	DAC	2023	DBLP DOI BibTeX RDF
15	Ophélie Renaud, Naouel Haggui, Karol Desnos, Jean-François Nezan	Automated Clustering and Pipelining of Dataflow Actors for Controlled Scheduling Complexity.	EUSIPCO	2023	DBLP DOI BibTeX RDF
15	Xin Zhou, Yong Dou, Rongchun Li, Peng Zhang 0035, Yuntao Liu	A pipelining strategy for accelerating convolution neural networks on ARM CPUs.	Concurr. Comput. Pract. Exp.	2022	DBLP DOI BibTeX RDF
15	Haiqiao Wu, Wan Du, Peng Gong 0001, Dapeng Oliver Wu	CPU: Cross-Rack-Aware Pipelining Update for Erasure-Coded Storage.	IEEE Trans. Cloud Comput.	2022	DBLP DOI BibTeX RDF
15	Chun Chen, Li Ning 0001, Junxue Li, Shengzhong Feng, Hao Zhang, Qiang Zhang, Jinchun Yin	Dynamic pipelining for the loosely-coupled distributed constraint satisfaction problems.	Comput. Electr. Eng.	2022	DBLP DOI BibTeX RDF
15	Mochamad Asri, Andreas Gerstlauer	CASPHAr: Cache-Managed Accelerator Staging and Pipelining in Heterogeneous System Architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
15	Cunlu Li, Dezun Dong, Xiangke Liao	MUA-Router: Maximizing the Utility-of-Allocation for On-chip Pipelining Routers.	ACM Trans. Archit. Code Optim.	2022	DBLP DOI BibTeX RDF
15	Alexei A. Ivankov, G. A. Manuilov	Data Repository in Framework for Computation Pipelining: Model, Architecture, the Implementation Performance Estimates.	Program. Comput. Softw.	2022	DBLP DOI BibTeX RDF
15	Kazuki Osawa, Shigang Li 0002, Torsten Hoefler	PipeFisher: Efficient Training of Large Language Models Using Pipelining and Fisher Information Matrices.	CoRR	2022	DBLP DOI BibTeX RDF
15	Guyue Huang, Yang Bai, Liu Liu 0017, Yuke Wang, Bei Yu 0001, Yufei Ding, Yuan Xie 0001	Enabling Data Movement and Computation Pipelining in Deep Learning Compiler.	CoRR	2022	DBLP DOI BibTeX RDF
15	Liwei Guo, Wonkyo Choe, Felix Xiaozhu Lin	Efficient NLP Inference at the Edge via Elastic Pipelining.	CoRR	2022	DBLP DOI BibTeX RDF
15	Cihat Keçeci, Mohammad Shaqfeh, Fawaz S. Al-Qahtani, Muhammad Ismail 0001, Erchin Serpedin	Clustered Scheduling and Communication Pipelining For Efficient Resource Management Of Wireless Federated Learning.	CoRR	2022	DBLP DOI BibTeX RDF
15	Yuke Wang, Boyuan Feng, Zheng Wang, Tong Geng, Kevin J. Barker, Ang Li 0006, Yufei Ding	Empowering GNNs with Fine-grained Communication-Computation Pipelining on Multi-GPU Platforms.	CoRR	2022	DBLP DOI BibTeX RDF
15	Jennifer Andreoli-Fang, John T. Chapman	Latency Reduction for Mobile Backhaul by Pipelining LTE and DOCSIS.	CoRR	2022	DBLP DOI BibTeX RDF
15	Jackson Melchert, Yuchen Mei, Kalhan Koul, Qiaoyi Liu, Mark Horowitz, Priyanka Raina	Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays.	CoRR	2022	DBLP DOI BibTeX RDF
15	Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos	ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining.	CoRR	2022	DBLP DOI BibTeX RDF
15	Hongwu Peng, Shaoyi Huang, Shiyang Chen, Bingbing Li, Tong Geng, Ang Li 0006, Weiwen Jiang, Wujie Wen, Jinbo Bi, Hang Liu 0001, Caiwen Ding	A Length Adaptive Algorithm-Hardware Co-design of Transformer on FPGA Through Sparse Attention and Dynamic Pipelining.	CoRR	2022	DBLP DOI BibTeX RDF
15	María Novo-Lourés, Yeray Lage, Reyes Pavón 0001, Rosalía Laza, David Ruano-Ordás, José Ramón Méndez 0001	Improving Pipelining Tools for Pre-processing Data.	Int. J. Interact. Multim. Artif. Intell.	2022	DBLP DOI BibTeX RDF
15	Adriaan Peetermans, Ingrid Verbauwhede	An energy and area efficient, all digital entropy source compatible with modern standards based on jitter pipelining.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2022	DBLP DOI BibTeX RDF
15	Ziying Ni, Ayesha Khalid, Dur-e-Shahwar Kundi, Máire O'Neill, Weiqiang Liu 0001	Efficient Pipelining Exploration for A High-performance CRYSTALS-Kyber Accelerator.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
15	Carl Poelking, Felix A. Faber, Bingqing Cheng	BenchML: an extensible pipelining framework for benchmarking representations of materials and molecules at scale.	Mach. Learn. Sci. Technol.	2022	DBLP DOI BibTeX RDF
15	Nicolai Fiege, Patrick Sittel, Peter Zipf	Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis.	FPL	2022	DBLP DOI BibTeX RDF
15	Konstantinos Parasyris, Giorgis Georgakoudis, Johannes Doerfert, Ignacio Laguna, Thomas R. W. Scogland	Piper: Pipelining OpenMP Offloading Execution Through Compiler Optimization For Performance.	P3HPC@SC	2022	DBLP DOI BibTeX RDF