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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1997 occurrences of 975 keywords
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Results
Found 1754 publication records. Showing 1754 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Won So, Alexander G. Dean |
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 13-23, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
TI C6000, static profitability estimation, DSP, software pipelining, VLIW, iterative compilation, software thread integration |
20 | Seongmoo Heo, Krste Asanovic |
Replacing global wires with an on-chip network: a power analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 369-374, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
on-chip network power model, tile size, wire power model, pipelining, router, tiled architecture |
20 | Mario R. Casu, Luca Macchiarulo |
Floorplanning for throughput. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 62-69, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
systems-on-chip, throughput, floorplanning, wire pipelining |
20 | Masaru Takesue |
A Model of Pipelined Mutual Exclusion on Cache-Coherent Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2003. Parallel Processing, 9th International Euro-Par Conference, Klagenfurt, Austria, August 26-29, 2003. Proceedings, pp. 917-922, 2003, Springer, 3-540-40788-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Models, pipelining, mutual exclusion |
20 | Luis Díaz de Cerio, Miguel Valero-García, Antonio González 0001 |
Hypercube Algorithms on Mesh Connected Multicomputers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 13(12), pp. 1247-1260, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
mesh interconnected multicomputers, standard embedding, communication pipelining, message-scheduling algorithms, Mapping algorithms, complete exchange, hypercube algorithms |
20 | Jason Cong |
Timing closure based on physical hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 170-174, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
interconnect planning, logic hierarchy, physical hierarchy, retiming and pipelining, sequential arrival time, interconnect optimization, timing closure, multilevel optimization |
20 | Bin Xiao 0001, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge |
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 144-149, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
rotation scheduling, software pipelining, retiming, unfolding |
20 | Hongbo Yang, Guang R. Gao, Clement Leung |
On achieving balanced power consumption in software pipelined loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 210-217, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
power-aware compilation, instruction level parallelism, software pipelining |
20 | Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri |
Framework for Synthesis of Virtual Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 326-331, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Virtual Pipeline, SLAAC-1V board, JHDL, FPGAs, Pipelining, Dynamic Reconfiguration, Partial Reconfiguration |
20 | M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas |
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 14-24, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
instruction queue clock rate, Pipelining |
20 | Steve Haynal, Forrest Brewer |
Automata-Based Symbolic Scheduling for Looping DFGs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(3), pp. 250-267, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Scheduling, high-level synthesis, automata, Binary Decision Diagrams, nondeterminism, loop pipelining, symbolic model |
20 | Josep Llosa, Eduard Ayguadé, Antonio González 0001, Mateo Valero, Jason Eckhardt |
Lifetime-Sensitive Modulo Scheduling in a Production Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(3), pp. 234-249, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
register requirements, software pipelining, VLIW, instruction scheduling, loop scheduling, Fine grain parallelism, superscalar architectures |
20 | Sergey Melnik 0001, Sriram Raghavan, Beverly Yang, Hector Garcia-Molina |
Building a distributed full-text index for the web. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Inf. Syst. ![In: ACM Trans. Inf. Syst. 19(3), pp. 217-241, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Embedded databases, Pipelining, Text retrieval, Inverted files, Distributed indexing |
20 | U. Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee |
An algorithm for synthesis of large time-constrained heterogeneous adaptive systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(2), pp. 207-225, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
delay/cost table, hierarchical control data-flow graph, time-constrained synthesis, pipelining, reconfigurable computing, mixed integer linear programming, list scheduling |
20 | Jörg Ritter 0002, Paul Molitor |
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 201-206, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
embedded zero tree coding, FPGA, field programmable gate arrays, architecture, wavelet transformation, pipelining, Xilinx, lossy image compression |
20 | Federico Silla, José Duato |
On the Use of Virtual Channels in Networks of Workstations with Irregular Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 11(8), pp. 813-828, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
block multiplexing, channel pipelining, flow control, Networks of workstations, virtual channels, wormhole switching, irregular topology |
20 | Montek Singh, Steven M. Nowick |
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 198-, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fine-grain pipelining, VLSI, pipelines, asynchronous, dynamic logic, FIFO, high-throughput, digital design |
20 | Herbert Leitold, Wolfgang Mayerwieser, Udo Payer, Karl C. Posch, Reinhard Posch, Johannes Wolkerstorfer |
A 155 Mbps Triple-DES Network Encryptor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2000, Second International Workshop, Worcester, MA, USA, August 17-18, 2000, Proceedings, pp. 164-174, 2000, Springer, 3-540-41455-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
DES algorithm, cipher block chaining, true single-phase logic, full-custom design, Network security, pipelining, encryption, Triple-DES |
20 | Johann Großschädl |
The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 16th Annual Computer Security Applications Conference (ACSAC 2000), 11-15 December 2000, New Orleans, Louisiana, USA, pp. 384-393, 2000, IEEE Computer Society, 0-7695-0859-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency |
20 | Dolors Royo, Antonio González 0001, Miguel Valero-García |
Low Communication Overhead Jacobi Algorithms for Eigenvalues Computation on Hypercubes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 14(2), pp. 171-193, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
eigenproblem, Jacobi ordering, CC-cube algorithms, communication pipelining, one port architecture, multiple port architecture, hamiltonian path |
20 | Tao Yang 0009, Cong Fu 0002 |
Heuristic Algorithms for Scheduling Iterative Task Computations on Distributed Memory Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(6), pp. 608-622, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
iterative task graphs, Scheduling, directed acyclic graphs, software pipelining, granularity, communication optimization |
20 | Hui-I Hsiao, Ming-Syan Chen, Philip S. Yu |
Parallel Execution of Hash Joins in Parallel Databases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(8), pp. 872-883, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Hash filters, bushy trees, pipelining, hash joins |
20 | F. Jesús Sánchez, Antonio González 0001 |
Cache Sensitive Modulo Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 338-348, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
VLIW machines, Software pipelining, software prefetching, locality analysis |
20 | Seongbae Park, SangMin Shim, Soo-Mook Moon |
Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 104-113, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
SPARC-based VLIW testbed, VLIW microprocessors, Very Long Instruction Word microprocessors, all-path speculation, gcc-generated optimized SPARC code, high-performance VLIW code, nongreedy enhanced pipeline scheduling, nonspeculative operations, profile-based all-path speculation, restricted speculative loads, scheduling compiler, speculative operations, trace-based speculation, performance, compiler, computer architecture, parallel machines, software pipelining, loop unrolling, renaming, memory disambiguation, copies, scheduling techniques |
20 | Chih-Tung Chen, Kayhan Küçükçakar |
High-level scheduling model and control synthesis for a broad range of design applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 236-243, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
multi-phase clocking, relative scheduling, architectural power optimization, high-level synthesis, pipelining, multi-threading, behavioral synthesis, control synthesis, architectural synthesis, scheduling model |
20 | Manuel Sánchez, Juan López, Oscar G. Plata, Emilio L. Zapata |
An efficient architecture for the in place fast cosine transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 499-508, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
in place fast cosine transform, image encoding, inverse cosine transform, locality, pipelining, image compression, discrete cosine transforms, DCT, VLSI implementation |
20 | Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma 0011 |
A strategy for determining a Jacobi specific dataflow processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 53-, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Jacobi specific dataflow processor, Jacobi algorithms, real-lime adaptive signal processing applications, quasi regularity property, dependence graph representations, exploration iteration, processor template, mapper, hierarchical exploration method, mapping efficiency, lookahead techniques, pipelining, retiming, adaptive signal processing, application domain, array processing |
20 | Sissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Nelson L. Passos |
Probabilistic Rotation: Scheduling Graphs with Uncertain Execution Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 292-297, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Scheduling, probability, software pipelining, rotation, data-flow graph |
20 | James D. Allen, David E. Schimmel |
Issues in the Design of High Performance SIMD Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(8), pp. 818-829, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
MasPar, caches, pipelining, SIMD, data parallel |
20 | Joseph G. Peters, Michel Syska |
Circuit-Switched Broadcasting in Torus Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(3), pp. 246-255, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
circuit-switched routing, Broadcasting, pipelining, tilings, torus networks |
20 | Val Donaldson, Jeanne Ferrante |
Determining Asynchronous Acyclic Pipeline Execution Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 568-572, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
asynchronous pipelining, parallel execution time, loop parallelism, task graph scheduling, pipeline scheduling |
20 | Ching-Long Su, Yin-Tsung Hwang |
Distributed arithmetic-based architectures for high speed IIR filter design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 156-161, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
high speed IIR filter, pipelining techniques, SPDM technology, parallel processing, parallel architectures, digital arithmetic, recursion, recursive filters, Distributed Arithmetic, IIR filters, DSP applications |
20 | S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri |
A VLSI chip for image compression using variable block size segmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 500-505, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
variable block size segmentation, VBSS scheme, variable size blocks, redundancy features, maximum compression, nearest neighbor communication, CMOS VLSI chip, image characteristics extraction subsystem, Cadence design tools, VLSI, parallelism, pipelining, image compression, VLSI architecture, VLSI implementation, lossless image compression, VLSI chip, coding techniques |
20 | Miodrag Potkonjak |
Discrete-relaxation-based heuristic techniques for video algorithm/architecture matching and system level transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP ![In: Proceedings 1995 International Conference on Image Processing, Washington, DC, USA, October 23-26, 1995, pp. 77-80, 1995, IEEE Computer Society, 0-8186-7310-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
discrete-relaxation-based heuristic techniques, video algorithm, system level transformations, computational transformations, throughput performance, iterative heuristic approach, behavioral transformations, rephasing, architecture matching, computational complexity, image processing, VLSI, pipelining, iterative methods, pipeline processing, retiming, integrated circuit design, system level design, video processing, video signal processing, heuristic programming, digital signal processing chips, circuit optimisation, throughput optimization |
20 | Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington |
A high performance bus and cache controller for PowerPC multiprocessing systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 204-211, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor |
20 | Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray |
Concurrent timing optimization of latch-based digital systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 680-685, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period |
20 | Jayesh Siddhiwala, Liang-Fang Chao |
Scheduling conditional data-flow graphs with resource sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 94-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
conditional data-flow graphs, resource sharing algorithm, pipeline scheduling algorithms, loop constructs, condition vector, dynamic resource sharing, rotation scheduling technique, parallel algorithms, data structures, data structure, resource allocation, high level synthesis, high level synthesis, processor scheduling, pipeline processing, data flow graphs, loop pipelining, conditional branches |
20 | W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi |
A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 398-402, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron |
20 | Debabrata Ghosh, Soumitra Kumar Nandy |
Wave pipelined architecture folding: a method to achieve low power and low area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 184-, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
wave pipelined architecture folding, clock-free wave pipelining scheme, chip area reduction, VLSI, low power design, logic design, pipeline processing, integrated circuit design, digital integrated circuits |
20 | Anne Rogers, Keshav Pingali |
Compiling for Distributed Memory Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(3), pp. 281-298, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
processdecomposition, locality ofreference, run-time resolution, message traffic, hydrodynamicsbenchmark, Intel iPSC/2, load balancing, parallel programming, synchronization, pipelining, synchronisation, program compilers, distributed memory systems, parallelizing compiler, pipeline processing, high-level languages, distributed memory architectures, SIMPLE |
20 | Vikram S. Adve, Mary K. Vernon |
Performance Analysis of Mesh Interconnection Networks with Deterministic Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(3), pp. 225-246, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
mesh interconnection networks, single-hit buffers, infinite buffers, nonadaptive deadlock-free routing scheme, closedqueueing network, message blocking, message pipelining, arbitrary source-destinationprobability distribution, 2D networks, shared-memory traffic, two dimensional network, performance evaluation, performance analysis, concurrency control, probability, multiprocessor interconnection networks, queueing theory, wormhole routing, network routing, virtual channels, deterministic routing, k-ary n-cube networks, deadlock-free routing algorithm, performance issues |
20 | Daniel H. Linder, James C. Harden |
Access Graphs: A Model for Investigating Memory Consistency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(1), pp. 39-52, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
access pipelining, synchronization, caches, computer architecture, computer architectures, synchronisation, shared memory systems, memory consistency, massively parallel systems |
20 | Michel Dubois 0001, Christoph Scheurich |
Memory Access Dependencies in Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 16(6), pp. 660-673, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
memory access dependencies, logical concurrency model, pipelining, multiprocessing systems, rules, shared-memory multiprocessors, multiprogramming, storage allocation, multiprocessor architectures, private caches |
20 | Zhiwei Xu, Kai Hwang 0001 |
Molecule: A Language Construct for Layered Development of Parallel Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 15(5), pp. 587-599, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
layered development, molecule type, computation mode, layered software development, iPSC, application flexibility, algorithms, parallel programs, parallel programming, parallel computers, pipelining, multicomputer, dataflow, high-level languages, multiprocessing, sequential, array processing, user friendliness, language construct, procedural language, PAL |
15 | Shanthi Pavan, Saravana Manivannan, Nishanth Basavaraj |
Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(1), pp. 268-281, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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15 | Athina Georgara, Raman Kazhamiakin, Ornella Mich, Alessio Palmero Aprosio, Jean-Christophe R. Pazzaglia, Juan Antonio Rodríguez-Aguilar, Carles Sierra |
Correction to: The AI4Citizen pilot: Pipelining AI-based technologies to support school-work alternation programmes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Intell. ![In: Appl. Intell. 54(1), pp. 1218, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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15 | Masaki Arai, Naoto Fukumoto, Hitoshi Murai |
Introducing software pipelining for the A64FX processor into LLVM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPC Asia Workshops ![In: Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region Workshops, HPCAsia 2024, Nagoya, Japan, January 25-27, 2024, pp. 1-6, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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15 | Zili Zhang, Fangyue Liu, Gang Huang 0001, Xuanzhe Liu, Xin Jin 0008 |
Fast Vector Query Processing for Large Datasets Beyond GPU Memory with Reordered Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NSDI ![In: 21st USENIX Symposium on Networked Systems Design and Implementation, NSDI 2024, Santa Clara, CA, April 15-17, 2024., pp. 23-40, 2024, USENIX Association. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP BibTeX RDF |
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15 | Rahma Nouaji, Stella Bitchebe, Oana Balmau |
SpeedyLoader: Efficient Pipelining of Data Preprocessing and Machine Learning Training. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroMLSys@EuroSys ![In: Proceedings of the 4th Workshop on Machine Learning and Systems, EuroMLSys 2024, Athens, Greece, 22 April 2024, pp. 65-72, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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15 | Nicolai Fiege, Peter Zipf |
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 16(3), pp. 49:1-49:32, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Delia Velasco-Montero, Bart Goossens, Jorge Fernández-Berni, Ángel Rodríguez-Vázquez, Wilfried Philips |
A Pipelining-Based Heterogeneous Scheduling and Energy-Throughput Optimization Scheme for CNNs Leveraging Apache TVM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 35007-35021, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Daeyeon Kim, Heonchoel Lee, Hyuck-Hoon Kwon, Yeji Hwang, Wonseok Choi 0005 |
Parallelized Particle Filter With Efficient Pipelining on FPGA for Real-Time Ballistic Target Tracking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 104830-104838, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Cihat Keçeci, Mohammad Shaqfeh, Fawaz S. Al-Qahtani, Muhammad Ismail 0001, Erchin Serpedin |
Clustered Scheduling and Communication Pipelining for Efficient Resource Management of Wireless Federated Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Things J. ![In: IEEE Internet Things J. 10(15), pp. 13303-13316, August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Yimin Zhuang, Xing Hu 0001, Xiaobing Chen, Tian Zhi |
DyPipe: A Holistic Approach to Accelerating Dynamic Neural Networks with Dynamic Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 38(4), pp. 899-910, July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Xiaoyu Yu |
Genofunc: genome annotation and identification of genome features for automated pipelining analysis of virus whole genome sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMC Bioinform. ![In: BMC Bioinform. 24(1), pp. 218, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Ziying Ni, Ayesha Khalid, Dur-e-Shahwar Kundi, Máire O'Neill, Weiqiang Liu 0001 |
HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 72(12), pp. 3340-3353, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Jingzhe Guo, Mingsheng Ying |
Software Pipelining for Quantum Loop Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 49(4), pp. 2815-2828, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Argyrios Sideris, Minas Dasygenis |
Enhancing the Hardware Pipelining Optimization Technique of the SHA-3 via FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. ![In: Comput. 11(8), pp. 152, August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Mark Horeni, Siddharth Joshi |
Improvements in Interlayer Pipelining of CNN Accelerators Using Genetic Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2311.12235, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Kingshuk Majumder, Uday Bondhugula |
Automatic multi-dimensional pipelining for high-level synthesis of dataflow accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2309.03203, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Athina Georgara, Raman Kazhamiakin, Ornella Mich, Alessio Palmero Aprosio, Jean-Christophe R. Pazzaglia, Juan Antonio Rodríguez-Aguilar, Carles Sierra |
The AI4Citizen pilot: Pipelining AI-based technologies to support school-work alternation programmes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Intell. ![In: Appl. Intell. 53(20), pp. 24157-24186, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos |
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023, pp. 1-6, 2023, IEEE, 978-3-9819263-7-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Yifan Yang, Joel S. Emer, Daniel Sánchez 0003 |
ISOSceles: Accelerating Sparse CNNs through Inter-Layer Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023, Montreal, QC, Canada, February 25 - March 1, 2023, pp. 598-610, 2023, IEEE, 978-1-6654-7652-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Zeqian Dong, Qiang He 0001, Feifei Chen 0001, Hai Jin 0001, Tao Gu, Yun Yang 0001 |
EdgeMove: Pipelining Device-Edge Model Training for Mobile Intelligence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WWW ![In: Proceedings of the ACM Web Conference 2023, WWW 2023, Austin, TX, USA, 30 April 2023 - 4 May 2023, pp. 3142-3153, 2023, ACM, 978-1-4503-9416-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Liang Yuan, Qiang He 0001, Feifei Chen 0001, Ruihan Dou, Hai Jin 0001, Yun Yang 0001 |
PipeEdge: A Trusted Pipelining Collaborative Edge Training based on Blockchain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WWW ![In: Proceedings of the ACM Web Conference 2023, WWW 2023, Austin, TX, USA, 30 April 2023 - 4 May 2023, pp. 3033-3043, 2023, ACM, 978-1-4503-9416-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Shaohuai Shi, Xinglin Pan, Xiaowen Chu 0001, Bo Li 0001 |
PipeMoE: Accelerating Mixture-of-Experts through Adaptive Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: IEEE INFOCOM 2023 - IEEE Conference on Computer Communications, New York City, NY, USA, May 17-20, 2023, pp. 1-10, 2023, IEEE, 979-8-3503-3414-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Siddhisanket Raskar, Thomas Applencourt, Kalyan Kumaran, Guang R. Gao |
Codelet Pipe: Realization of Dataflow Software Pipelining for Extended Codelet Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: Proceedings of the 52nd International Conference on Parallel Processing Workshops, ICPP Workshops 2023, Salt Lake City, UT, USA, August 7-10, 2023, pp. 127-135, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Viktor Razilov, Juncen Zhong, Emil Matús, Gerhard P. Fettweis |
Dual Vector Load for Improved Pipelining in Vector Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COOL CHIPS ![In: IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2023, Tokyo, Japan, April 19-21, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-3201-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Yuke Wang, Boyuan Feng, Zheng Wang, Tong Geng, Kevin J. Barker, Ang Li 0006, Yufei Ding |
MGG: Accelerating Graph Neural Networks with Fine-Grained Intra-Kernel Communication-Computation Pipelining on Multi-GPU Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OSDI ![In: 17th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2023, Boston, MA, USA, July 10-12, 2023., pp. 779-795, 2023, USENIX Association. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
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15 | Lin Zhang, Shaohuai Shi, Xiaowen Chu 0001, Wei Wang 0030, Bo Li 0001, Chengjian Liu |
DeAR: Accelerating Distributed Deep Learning with Fine-Grained All-Reduce Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: 43rd IEEE International Conference on Distributed Computing Systems, ICDCS 2023, Hong Kong, July 18-21, 2023, pp. 142-153, 2023, IEEE, 979-8-3503-3986-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Ryan Dutra de Abreu, Laura Silva de Assis, Douglas de O. Cardoso |
Experimental Analysis of Pipelining Community Detection and Recommender Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WEBIST ![In: Proceedings of the 19th International Conference on Web Information Systems and Technologies, WEBIST 2023, Rome, Italy, November 15-17, 2023., pp. 496-503, 2023, SCITEPRESS, 978-989-758-672-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Siddhisanket Raskar, Jose Manuel Monsalve Diaz, Thomas Applencourt, Kalyan Kumaran, Guang Gao |
Implementation of Dataflow Software Pipelining for Codelet Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPE ![In: Proceedings of the 2023 ACM/SPEC International Conference on Performance Engineering, ICPE 2023, Coimbra, Portugal, April 15-19, 2023, pp. 161-172, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | B. Naresh Kumar Reddy, K. Sarangam, Sushmita Dandeliya, S. Pavan Sai Naidu, Naveen Kumar P |
Accelerating Sorting Performance on FPGA: Combining Quick Sort and Heap Sort through Hybrid Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2023, Ahmedabad, India, December 18-20, 2023, pp. 405-408, 2023, IEEE, 979-8-3503-8324-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Miyeon Lee, Inhwan Kim, Pureuna Shin, Hwayong Oh, Keewon Joe |
Prediction-Reconstruction VLSI architecture with efficient pipelining for VVC Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE ![In: IEEE International Conference on Consumer Electronics, ICCE 2023, Las Vegas, NV, USA, January 6-8, 2023, pp. 1-3, 2023, IEEE, 978-1-6654-9130-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Ian Healy, Peter Giordano, Wafa Elmannai |
Branch Prediction in CPU Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UEMCON ![In: 14th IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference, UEMCON 2023, New York, NY, USA, October 12-14, 2023, pp. 364-368, 2023, IEEE, 979-8-3503-0413-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Yuzuo Zhang, Xinyuan Tu, Lin Wang, Yuchong Hu, Fang Wang, Ye Wang |
FullRepair: Towards Optimal Repair Pipelining in Erasure-Coded Clustered Storage Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: IEEE International Conference on Cluster Computing, CLUSTER 2023, Santa Fe, NM, USA, October 31 - Nov. 3, 2023, pp. 107-117, 2023, IEEE, 979-8-3503-0792-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Liwei Guo, Wonkyo Choe, Felix Xiaozhu Lin |
STI: Turbocharge NLP Inference at the Edge via Elastic Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS (2) ![In: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2, ASPLOS 2023, Vancouver, BC, Canada, March 25-29, 2023, pp. 791-803, 2023, ACM, 978-1-4503-9916-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Chengning Wang, Dan Feng 0001, Wei Tong 0001, Jingning Liu |
CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2348-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Ophélie Renaud, Naouel Haggui, Karol Desnos, Jean-François Nezan |
Automated Clustering and Pipelining of Dataflow Actors for Controlled Scheduling Complexity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUSIPCO ![In: 31st European Signal Processing Conference, EUSIPCO 2023, Helsinki, Finland, September 4-8, 2023, pp. 1698-1702, 2023, IEEE, 978-9-4645-9360-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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15 | Xin Zhou, Yong Dou, Rongchun Li, Peng Zhang 0035, Yuntao Liu |
A pipelining strategy for accelerating convolution neural networks on ARM CPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 34(2), 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Haiqiao Wu, Wan Du, Peng Gong 0001, Dapeng Oliver Wu |
CPU: Cross-Rack-Aware Pipelining Update for Erasure-Coded Storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Cloud Comput. ![In: IEEE Trans. Cloud Comput. 10(4), pp. 2424-2436, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Chun Chen, Li Ning 0001, Junxue Li, Shengzhong Feng, Hao Zhang, Qiang Zhang, Jinchun Yin |
Dynamic pipelining for the loosely-coupled distributed constraint satisfaction problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 104(Part), pp. 108422, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Mochamad Asri, Andreas Gerstlauer |
CASPHAr: Cache-Managed Accelerator Staging and Pipelining in Heterogeneous System Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11), pp. 4325-4336, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Cunlu Li, Dezun Dong, Xiangke Liao |
MUA-Router: Maximizing the Utility-of-Allocation for On-chip Pipelining Routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 19(3), pp. 33:1-33:23, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Alexei A. Ivankov, G. A. Manuilov |
Data Repository in Framework for Computation Pipelining: Model, Architecture, the Implementation Performance Estimates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Program. Comput. Softw. ![In: Program. Comput. Softw. 48(5), pp. 347-358, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Kazuki Osawa, Shigang Li 0002, Torsten Hoefler |
PipeFisher: Efficient Training of Large Language Models Using Pipelining and Fisher Information Matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2211.14133, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Guyue Huang, Yang Bai, Liu Liu 0017, Yuke Wang, Bei Yu 0001, Yufei Ding, Yuan Xie 0001 |
Enabling Data Movement and Computation Pipelining in Deep Learning Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2210.16691, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Liwei Guo, Wonkyo Choe, Felix Xiaozhu Lin |
Efficient NLP Inference at the Edge via Elastic Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2207.05022, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Cihat Keçeci, Mohammad Shaqfeh, Fawaz S. Al-Qahtani, Muhammad Ismail 0001, Erchin Serpedin |
Clustered Scheduling and Communication Pipelining For Efficient Resource Management Of Wireless Federated Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2206.07631, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Yuke Wang, Boyuan Feng, Zheng Wang, Tong Geng, Kevin J. Barker, Ang Li 0006, Yufei Ding |
Empowering GNNs with Fine-grained Communication-Computation Pipelining on Multi-GPU Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2209.06800, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Jennifer Andreoli-Fang, John T. Chapman |
Latency Reduction for Mobile Backhaul by Pipelining LTE and DOCSIS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2211.09025, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Jackson Melchert, Yuchen Mei, Kalhan Koul, Qiaoyi Liu, Mark Horowitz, Priyanka Raina |
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2211.13182, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos |
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2211.12600, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Hongwu Peng, Shaoyi Huang, Shiyang Chen, Bingbing Li, Tong Geng, Ang Li 0006, Weiwen Jiang, Wujie Wen, Jinbo Bi, Hang Liu 0001, Caiwen Ding |
A Length Adaptive Algorithm-Hardware Co-design of Transformer on FPGA Through Sparse Attention and Dynamic Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2208.03646, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | María Novo-Lourés, Yeray Lage, Reyes Pavón 0001, Rosalía Laza, David Ruano-Ordás, José Ramón Méndez 0001 |
Improving Pipelining Tools for Pre-processing Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Interact. Multim. Artif. Intell. ![In: Int. J. Interact. Multim. Artif. Intell. 7(4), pp. 214, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Adriaan Peetermans, Ingrid Verbauwhede |
An energy and area efficient, all digital entropy source compatible with modern standards based on jitter pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(4), pp. 88-109, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Ziying Ni, Ayesha Khalid, Dur-e-Shahwar Kundi, Máire O'Neill, Weiqiang Liu 0001 |
Efficient Pipelining Exploration for A High-performance CRYSTALS-Kyber Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2022, pp. 1093, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
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15 | Carl Poelking, Felix A. Faber, Bingqing Cheng |
BenchML: an extensible pipelining framework for benchmarking representations of materials and molecules at scale. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mach. Learn. Sci. Technol. ![In: Mach. Learn. Sci. Technol. 3(4), pp. 40501, December 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Nicolai Fiege, Patrick Sittel, Peter Zipf |
Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022, Belfast, United Kingdom, August 29 - Sept. 2, 2022, pp. 262-269, 2022, IEEE, 978-1-6654-7390-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Konstantinos Parasyris, Giorgis Georgakoudis, Johannes Doerfert, Ignacio Laguna, Thomas R. W. Scogland |
Piper: Pipelining OpenMP Offloading Execution Through Compiler Optimization For Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
P3HPC@SC ![In: IEEE/ACM International Workshop on Performance, Portability and Productivity in HPC, P3HPC@SC 2022, Dallas, TX, USA, November 13-18, 2022, pp. 100-110, 2022, IEEE, 978-1-6654-6021-7. The full citation details ...](Pics/full.jpeg) |
2022 |
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