Search results for "wirelength"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Lee, Yao-Wen Chang	Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
10	Jarrod A. Roy, Igor L. Markov	High-Performance Routing at the Nanometer Scale.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
10	Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi	An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty.	DSD	2008	DBLP DOI BibTeX RDF
10	Michael D. Moffitt	MaizeRouter: Engineering an effective global router.	ASP-DAC	2008	DBLP DOI BibTeX RDF
10	Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong	LP based white space redistribution for thermal via planning and performance optimization in 3D ICs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
10	Chaomin Luo, Miguel F. Anjos, Anthony Vannelli	Large-scale fixed-outline floorplanning design using convex optimization techniques.	ASP-DAC	2008	DBLP DOI BibTeX RDF
10	Anand Rajaram, David Z. Pan	MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks.	ASP-DAC	2008	DBLP DOI BibTeX RDF
10	Jason Cong, Guojie Luo	Highly efficient gradient computation for density-constrained analytical placement methods.	ISPD	2008	DBLP DOI BibTeX RDF	force-directed method, mixed-size placement
10	Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang	Metal-density driven placement for cmp variation and routability.	ISPD	2008	DBLP DOI BibTeX RDF	VLSI, placement, physical design, manufacturability
10	Stephen Plaza, Igor L. Markov, Valeria Bertacco	Optimizing non-monotonic interconnect using functional simulation and logic restructuring.	ISPD	2008	DBLP DOI BibTeX RDF
10	Minsik Cho, Yongchan Ban, David Z. Pan	Double patterning technology friendly detailed routing.	ICCAD	2008	DBLP DOI BibTeX RDF
10	Tao Luo 0002, David A. Papa, Zhuo Li 0001, Chin Ngai Sze, Charles J. Alpert, David Z. Pan	Pyramids: an efficient computational geometry-based approach for timing-driven placement.	ICCAD	2008	DBLP DOI BibTeX RDF
10	Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang	Routing for chip-package-board co-design considering differential pairs.	ICCAD	2008	DBLP DOI BibTeX RDF
10	Jin Hu, Jarrod A. Roy, Igor L. Markov	Sidewinder: a scalable ILP-based router.	SLIP	2008	DBLP DOI BibTeX RDF	integer linear programming, global routing
10	Hsin-Hsiung Huang, Hui-Yu Huang, Yu-Cheng Lin, Tsai-Ming Hsieh	Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Kanupriya Gulati, Sunil P. Khatri	Improving FPGA routability using network coding.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	FPGA, network coding
10	Haixia Yan, Qiang Zhou 0001, Xianlong Hong	Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm.	ISQED	2008	DBLP DOI BibTeX RDF	placement, DCT, 3D, thermal
10	Ming-Fang Lai, Hung-Ming Chen	An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign.	ISQED	2008	DBLP DOI BibTeX RDF	Chip-Package Codesign, I/O Placement, Power Integrity
10	Arash Mehdizadeh, Morteza Saheb Zamani	Proposing an efficient method to estimate and reduce crosstalk after placement in VLSI circuits.	AICCSA	2008	DBLP DOI BibTeX RDF
10	Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan	An integrated nonlinear placement framework with congestion and porosity aware buffer planning.	DAC	2008	DBLP DOI BibTeX RDF	VLSI, placement, physical design, buffer
10	Anand Rajaram, David Z. Pan	Robust chip-level clock tree synthesis for SOC designs.	DAC	2008	DBLP DOI BibTeX RDF	chip-level CTS, physical design, clock network
10	Jason Meyer, Fatih Kocan	Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
10	Andrew B. Kahng, Bao Liu 0001, Qinke Wang	Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
10	Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li 0001	Utilizing Redundancy for Timing Critical Interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
10	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
10	Zhen Yang 0006, Anthony Vannelli, Shawki Areibi	An ILP based hierarchical global routing approach for VLSI ASIC design.	Optim. Lett.	2007	DBLP DOI BibTeX RDF	VLSI physical design, Standard cell global routing, Integer Linear Programming
10	Srinivasan Murali, Luca Benini, Giovanni De Micheli	An Application-Specific Design Methodology for On-Chip Crossbar Generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
10	Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang	MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
10	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.	ISVLSI	2007	DBLP DOI BibTeX RDF
10	Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman 0001, Parthasarathi Dasgupta	Minimum-Congestion Placement for Y-interconnects: Some studies and observations.	ISVLSI	2007	DBLP DOI BibTeX RDF
10	Adriel Ziesemer, Cristiano Lazzari	Transistor level automatic layout generator for non-complementary CMOS cells.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
10	Peter Spindler, Frank M. Johannes	Fast and accurate routing demand estimation for efficient routability-driven placement.	DATE	2007	DBLP DOI BibTeX RDF
10	Natarajan Viswanathan, Min Pan, Chris C. N. Chu	FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control.	ASP-DAC	2007	DBLP DOI BibTeX RDF	legalization technique, FastPlace 3.0, multilevel quadratic placement algorithm, placement congestion control, large-scale mixed-size designs, multilevel global placement framework, two-level clustering scheme, iterative local refinement, placement blockages, placement congestion constraints
10	Pei-Ci Wu, Jhih-Rong Gao, Ting-Chi Wang	A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction.	ASP-DAC	2007	DBLP DOI BibTeX RDF
10	Wai-Kei Mak, Jr-Wei Chen	Voltage Island Generation under Performance Requirement for SoC Designs.	ASP-DAC	2007	DBLP DOI BibTeX RDF
10	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
10	Hao Yu 0001, Yu Hu 0002, Chunchen Liu, Lei He 0001	Minimal skew clock embedding considering time variant temperature gradient.	ISPD	2007	DBLP DOI BibTeX RDF	clock tree design, compact parameterization, parameterized perturbation, thermal management
10	Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang	Efficient obstacle-avoiding rectilinear steiner tree construction.	ISPD	2007	DBLP DOI BibTeX RDF	routing, spanning tree, physical design, Steiner tree
10	Shiyan Hu, Jiang Hu	Pattern sensitive placement for manufacturability.	ISPD	2007	DBLP DOI BibTeX RDF	placement, physical design, manufacturability
10	Song Chen 0001, Takeshi Yoshimura	A stable fixed-outline floorplanning method.	ISPD	2007	DBLP DOI BibTeX RDF	floorplanning, sequence pair, fixed-outline
10	Philip Chong, Christian Szegedy	A morphing approach to address placement stability.	ISPD	2007	DBLP DOI BibTeX RDF	incremental placement, stability, morphing
10	Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang	An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning.	ICCAD	2007	DBLP DOI BibTeX RDF
10	Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu	Exploiting STI stress for performance.	ICCAD	2007	DBLP DOI BibTeX RDF
10	Muhammet Mustafa Ozdal, Martin D. F. Wong	Archer: a history-driven global routing algorithm.	ICCAD	2007	DBLP DOI BibTeX RDF
10	Jarrod A. Roy, Igor L. Markov	High-performance routing at the nanometer scale.	ICCAD	2007	DBLP DOI BibTeX RDF
10	Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma	An accurate and efficient probabilistic congestion estimation model in x architecture.	SLIP	2007	DBLP DOI BibTeX RDF	congestion estimation, dynamic resource assignment, the X architecture, routability
10	Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu 0001	Analytical thermal placement for VLSI lifetime improvement and minimum performance variation.	ICCD	2007	DBLP DOI BibTeX RDF
10	Shilpa Bhoj, Dinesh Bhatia	Thermal Modeling and Temperature Driven Placement for FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Wing On Fung, Tughrul Arslan, Sami Khawam	A Hybrid Engine for the Placement of Domain-Specific Reconfigurable Arrays.	AHS	2007	DBLP DOI BibTeX RDF
10	Vyas Krishnan, Srinivas Katkoori	A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
10	Pritha Banerjee 0001, Susmita Sur-Kolay, Arijit Bishnu	Floorplanning in Modern FPGAs.	VLSI Design	2007	DBLP DOI BibTeX RDF
10	Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang	An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design.	DAC	2007	DBLP DOI BibTeX RDF
10	Min Pan, Chris C. N. Chu	IPR: An Integrated Placement and Routing Algorithm.	DAC	2007	DBLP DOI BibTeX RDF
10	Minsik Cho, Hua Xiang 0001, Ruchir Puri, David Z. Pan	TROY: Track Router with Yield-driven Wire Planning.	DAC	2007	DBLP DOI BibTeX RDF
10	Eric Wong 0002, Jacob R. Minz, Sung Kyu Lim	Multi-Objective Module Placement For 3-D System-On-Package.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
10	PariVallal Kannan, Dinesh Bhatia	Interconnect estimation for FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Wei-Kei Mak, C.-L. Lai	On Constrained Pin-Mapping for FPGA-PCB Codesign.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Hung-Ming Chen, I-Min Liu, Martin D. F. Wong	I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim	Profile-guided microarchitectural floor planning for deep submicron processor design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Tung-Chieh Chen, Yao-Wen Chang	Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim	Profile-Driven Instruction Mapping for Dataflow Architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang	Lens aberration aware timing-driven placement.	DATE	2006	DBLP DOI BibTeX RDF
10	Eric Wong 0002, Sung Kyu Lim	3D floorplanning with thermal vias.	DATE	2006	DBLP DOI BibTeX RDF
10	Min-Seok Kim, Jiang Hu	Associative skew clock routing for difficult instances.	DATE	2006	DBLP DOI BibTeX RDF
10	Jacob R. Minz, Somaskanda Thyagaraja, Sung Kyu Lim	Optical routing for 3D system-on-package.	DATE	2006	DBLP DOI BibTeX RDF
10	Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh	Layout driven data communication optimization for high level synthesis.	DATE	2006	DBLP DOI BibTeX RDF
10	Shantanu Dutt, Hasan Arslan	Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations.	DATE	2006	DBLP DOI BibTeX RDF
10	Bin Liu 0007, Yici Cai, Qiang Zhou 0001, Xianlong Hong	Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
10	Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin	A novel framework for multilevel full-chip gridless routing.	ASP-DAC	2006	DBLP DOI BibTeX RDF
10	Natarajan Viswanathan, Min Pan, Chris C. N. Chu	FastPlace 2.0: an efficient analytical placer for mixed-mode designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
10	Love Singhal, Elaheh Bozorgzadeh	Multi-layer Floorplanning on a Sequence of Reconfigurable Designs.	FPL	2006	DBLP DOI BibTeX RDF
10	Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky Ramachandran	Solving hard instances of floorplacement.	ISPD	2006	DBLP DOI BibTeX RDF	floorplacement, benchmarks, placement, floorplanning, RTL, circuit layout
10	Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi, Maogang Wang, Majid Sarrafzadeh	Dragon2006: blockage-aware congestion-controlling mixed-size placer.	ISPD	2006	DBLP DOI BibTeX RDF	placement, physical design
10	Christoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen	Efficient generation of short and fast repeater tree topologies.	ISPD	2006	DBLP DOI BibTeX RDF	inverter tree, repeater tree, buffering, tree topology, rectilinear Steiner tree
10	Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kenton Sze, Min Xie 0004	mPL6: enhanced multilevel mixed-size placement.	ISPD	2006	DBLP DOI BibTeX RDF	mixed-size placement, legalization, Helmholtz equation, force-directed placement, multilevel optimization
10	Eric Wong 0002, Jacob R. Minz, Sung Kyu Lim	Decoupling capacitor planning and sizing for noise and leakage reduction.	ICCAD	2006	DBLP DOI BibTeX RDF	3D floorplanning, power supply noise, decoupling capacitors, leakage power reduction
10	Minsik Cho, David Z. Pan, Hua Xiang 0001, Ruchir Puri	Wire density driven global routing for CMP variation and timing.	ICCAD	2006	DBLP DOI BibTeX RDF	performance, VLSI, manufacturability, global routing
10	Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw	A statistical framework for post-silicon tuning through body bias clustering.	ICCAD	2006	DBLP DOI BibTeX RDF
10	Michael D. Moffitt, Aaron N. Ng, Igor L. Markov, Martha E. Pollack	Constraint-driven floorplan repair.	DAC	2006	DBLP DOI BibTeX RDF	constraints, floorplanning, legalization
10	Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li 0001	Steiner network construction for timing critical nets.	DAC	2006	DBLP DOI BibTeX RDF	Steiner network, routing, redundancy, interconnect
10	Padmini Gopalakrishnan, Xin Li 0001, Lawrence T. Pileggi	Architecture-aware FPGA placement using metric embedding.	DAC	2006	DBLP DOI BibTeX RDF	FPGAs, placement, metric embedding
10	Rishi Chaturvedi, Jiang Hu	An efficient merging scheme for prescribed skew clock routing.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
10	Haoxing Ren, David Zhigang Pan, David S. Kung 0001	Sensitivity guided net weighting for placement-driven synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
10	Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong	Simultaneous power supply planning and noise avoidance in floorplan design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
10	Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao	The Y architecture for on-chip interconnect: analysis and methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
10	Hua Xiang 0001, Xiaoping Tang, Martin D. F. Wong	An algorithm for integrated pin assignment and buffer planning.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	min-cost maximum flow, Buffer insertion, pin assignment
10	Chen Li 0004, Cheng-Kok Koh, Patrick H. Madden	Floorplan management: incremental placement for gate sizing and buffer insertion.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Jason Cong, Yan Zhang	Thermal-driven multilevel routing for 3-D ICs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Zhong-Ching Lu, Ting-Chi Wang	Concurrent flip-flop and buffer insertion with adaptive blockage avoidance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Liang Huang, Yici Cai, Qiang Zhou 0001, Xianlong Hong, Jiang Hu, Yongqiang Lu 0001	Clock network minimization methodology based on incremental placement.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Wai-Ching Douglas Lam, Cheng-Kok Koh	Process variation robust clock tree routing.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Charles J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz	Placement stability metrics.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Natarajan Viswanathan, Min Pan, Chris C. N. Chu	FastPlace: an analytical placer for mixed-mode designs.	ISPD	2005	DBLP DOI BibTeX RDF	mixed-mode placement, floorplanning, analytical placement
10	Tung-Chieh Chen, Yao-Wen Chang	Modern floorplanning based on fast simulated annealing.	ISPD	2005	DBLP DOI BibTeX RDF	simulated annealing, floorplanning
10	Tony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie 0004	mPL6: a robust multilevel mixed-size placement engine.	ISPD	2005	DBLP DOI BibTeX RDF	mixed-size placement, legalization, helmholtz equation, force-directed placement, multilevel optimization
10	Andrew B. Kahng, Sherief Reda, Qinke Wang	APlace: a general analytic placement framework.	ISPD	2005	DBLP DOI BibTeX RDF	mixed size, congestion, multi-level, analytical placement
10	Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten	Routing of analog busses with parasitic symmetry.	ISPD	2005	DBLP DOI BibTeX RDF	analog routing, net bundles, paired nets, virtual terminals, routing, EDA, RF, bus routing, IC-layout
10	Andrew B. Kahng, Bao Liu 0001, Qinke Wang	Supply Voltage Degradation Aware Analytical Placement.	ICCD	2005	DBLP DOI BibTeX RDF
10	Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003, Hsin-Hsien Ho	Modem floorplanning with abutment and fixed-outline constraints.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
10	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen 0001, Chung-Kuan Cheng	Performance constrained floorplanning based on partial clustering [IC layout].	ISCAS (2)	2005	DBLP DOI BibTeX RDF