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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 618 occurrences of 392 keywords
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Results
Found 665 publication records. Showing 665 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
10 | Maizura Mokhtar, David M. Halliday, Andy M. Tyrrell |
Hippocampus-Inspired Spiking Neural Network on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings, pp. 362-371, 2008, Springer, 978-3-540-85856-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bio-inspired Hardware, FPGA, Spiking Neural Network |
10 | David Sheldon, Frank Vahid |
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 155-160, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
BRAM, high-throughput design, pattern counting, redesigning circuit, FPGA, design patterns, stream, memory, ASIC |
10 | Jin Hu, Jarrod A. Roy, Igor L. Markov |
Sidewinder: a scalable ILP-based router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 73-80, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
integer linear programming, global routing |
10 | Marcus Komann, Alexander Kröller, Christiane Schmidt 0001, Dietmar Fey, Sándor P. Fekete |
Emergent algorithms for centroid and orientation detection in high-performance embedded cameras. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008, pp. 221-230, 2008, ACM, 978-1-60558-077-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
emergent algorithms, marching pixels, image processing, object detection, massively-parallel |
10 | Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet |
Silicon-level Solutions to Counteract Passive and Active Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDTC ![In: Fifth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008, FDTC 2008, Washington, DC, USA, 10 August 2008, pp. 3-17, 2008, IEEE Computer Society, 978-0-7695-3314-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Sylvain Saïghi, Laure Buhry, Yannick Bornat, Gilles N'Kaoua, Jean Tomas, Sylvie Renaud |
Adjusting the neurons models in neuromimetic ICs using the voltage-clamp technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1564-1567, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Li Zhang, Shuangfei Li, Zan Yin, Wenyuan Zhao |
A Research on an ASIP Processing Element Architecture Suitable for FPGA Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (3) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 3: Grid Computing / Distributed and Parallel Computing / Information Security, December 12-14, 2008, Wuhan, China, pp. 441-445, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Jens-Peter Kaps |
Chai-Tea, Cryptographic Hardware Implementations of xTEA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INDOCRYPT ![In: Progress in Cryptology - INDOCRYPT 2008, 9th International Conference on Cryptology in India, Kharagpur, India, December 14-17, 2008. Proceedings, pp. 363-375, 2008, Springer, 978-3-540-89753-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
symmetric key algorithms, TEA, XTEA, FPGA, ASIC, Efficient implementation |
10 | Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary F. Margrave |
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 197-202, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | David Dickin, Lesley Shannon |
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 67-72, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Kamran Zarrineh |
Design for Test Challenges of High Performance/Low Power Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 503-503, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Sandeep Gupta, Jaya Singh, Abhijit Roy |
A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 526-530, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Dual-Vt Technology, Cell-Based Approach, Cell-swapping, Leakage Power |
10 | Nidhir Kumar, Senthil N. Velu, Rajan Verma |
Gateway to Chips: High Speed I/O Signalling and Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 3-4, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Min Li 0001, Bruno Bougard, David Novo, Liesbet Van der Perre, Francky Catthoor |
How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 345-346, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
baseband, low power, wireless, SDR |
10 | Michela Becchi, Patrick Crowley |
Efficient regular expression evaluation: theory to practice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2008 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2008, San Jose, California, USA, November 6-7, 2008, pp. 50-59, 2008, ACM, 978-1-60558-346-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Aggelos Ioannou, Manolis Katevenis |
Pipelined heap (priority queue) management for advanced scheduling in high-speed networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 15(2), pp. 450-461, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
high-speed network scheduling, pipelined hard-ware heap, synthesizable core, weighted fair queueing, priority queue, weighted round robin |
10 | Fan-Min Li, An-Yeu Wu |
On the New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 55(11), pp. 5506-5516, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | George Michelogiannakis, Dionisios N. Pnevmatikatos, Manolis Katevenis |
Approaching Ideal NoC Latency with Pre-Configured Routes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 153-162, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Tim Güneysu, Christof Paar, Sven Schäge |
Efficient Hash Collision Search Strategies on Special-Purpose Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WEWoRC ![In: Research in Cryptology, Second Western European Workshop, WEWoRC 2007, Bochum, Germany, July 4-6, 2007, Revised Selected Papers, pp. 39-51, 2007, Springer, 978-3-540-88352-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Crypto Attacks, Hash functions, Special-purpose Hardware |
10 | Jing Fu 0003, Olof Hagsand, Gunnar Karlsson |
Queuing Behavior and Packet Delays in Network Processor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 15th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2007), October 24-26, 2007, Istanbul, Turkey, pp. 217-224, 2007, IEEE Computer Society, 978-1-4244-1854-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
queueing behavior, network processor, router |
10 | Satish Sivaswamy, Kia Bazargan |
Variation-aware routing for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 71-79, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
statistical timing analysis, FPGA routing |
10 | David Slogsnat, Alexander Giese, Ulrich Brüning 0001 |
A versatile, low latency HyperTransport core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 45-52, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
HTX, HyperTransport, FPGA, prototyping, RTL |
10 | Gerald Hempel, Christian Hochberger |
A resource optimized Processor Core for FPGA based SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 51-58, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Yong Li 0006, Zhiying Wang 0003, Jian Ruan, Kui Dai |
A Low-Power Globally Synchronous Locally Asynchronous FFT Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: High Performance Computing and Communications, Third International Conference, HPCC 2007, Houston, USA, September 26-28, 2007, Proceedings, pp. 168-179, 2007, Springer, 978-3-540-75443-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy 0001, Ranjani Narayan |
REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 558-561, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Gerald Hempel, Christian Hochberger |
A resource optimized SoC Kit for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 761-764, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Subhomoy Chattopadhyay |
Low power design techniques for nanometer design processes: 65 nm and smaller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 5, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
65 nm, low power, embedded design |
10 | A. C. H. Ng, Jan-Willem Weijers, Miguel Glassee, Thomas Schuster, Bruno Bougard, Liesbet Van der Perre |
ESL design and HW/SW co-verification of high-end software defined radio platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 191-196, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
verification, emulation, SDR, hardware/software co-design, ESL |
10 | Yong Li 0006, Zhiying Wang 0003, Xue-mi Zhao, Jian Ruan, Kui Dai |
Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings, pp. 354-363, 2007, Springer, 978-3-540-74308-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Wolfgang Puffitsch, Martin Schoeberl |
picoJava-II in an FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JTRES ![In: Proceedings of the 5th International Workshop on Java Technologies for Real-time and Embedded Systems, JTRES 2007, Institute of Computer Engineering, Vienna University of Technology, 26-28 September 2007, Vienna, Austria, pp. 213-221, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, Java processor |
10 | Simone Medardoni, Davide Bertozzi, Enrico Macii |
Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 159-164, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
RTL synthesis, leakage-aware, power management, selection strategy |
10 | Dietmar Fey, Marcus Komann, Frank Schurz, Andreas Loos |
An Organic Computing architecture for visual microprocessors based on Marching Pixels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2686-2689, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Atanu Chattopadhyay, Zeljko Zilic |
Reconfigurable Clock Distribution Circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 877-880, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Hans Kristian Otnes Berge, Philipp Häfliger |
High-Speed Serial AER on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 857-860, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Andrew McCormick |
An Engineering Approach to Solving HPC Problems using FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 295-300, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Eunjung Cho, Anu G. Bourgeois, Feng Tan |
An FPGA Design to Achieve Fast and Accurate Results for Molecular Dynamics Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, 5th International Symposium, ISPA 2007, Niagara Falls, Canada, August 29-31, 2007, Proceedings, pp. 256-267, 2007, Springer, 978-3-540-74741-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | David E. Shaw, Martin M. Deneroff, Ron O. Dror, Jeffrey Kuskin, Richard H. Larson, John K. Salmon, Cliff Young, Brannon Batson, Kevin J. Bowers, Jack C. Chao, Michael P. Eastwood, Joseph Gagliardo, J. P. Grossman, C. Richard Ho, Doug Ierardi, István Kolossváry, John L. Klepeis, Timothy Layman, Christine McLeavey, Mark A. Moraes, Rolf Mueller, Edward C. Priest, Yibing Shan, Jochen Spengler, Michael Theobald, Brian Towles, Stanley C. Wang |
Anton, a special-purpose machine for molecular dynamics simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 1-12, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
biomolecular system simulation, computational drug design, special-purpose machine, bioinformatics, computational biology, molecular dynamics, protein folding, protein structure |
10 | Piti Piyachon, Yan Luo |
Compact State Machines for High Performance Pattern Matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 493-496, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar |
Enhancing FPGA Performance for Arithmetic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 334-337, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Amilcar do Carmo Lucas, Sven Heithecker, Rolf Ernst |
FlexWAFE - A High-end Real-Time Stream Processing Library for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 916-921, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Huai-Yi Hsu, Jih-Chiang Yeo, An-Yeu Wu |
Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(5), pp. 489-500, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Use of Computation-Unit Integrated Memories in High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 1969-1989, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Paul Royal, Mitch Halpin, Ada Gavrilovska, Karsten Schwan |
Utilizing Network Processors in Distributed Enterprise Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCA ![In: Fifth IEEE International Symposium on Network Computing and Applications, NCA 2006, 24-26 July 2006, Cambridge, Massachusetts, USA, pp. 66-76, 2006, IEEE Computer Society, 0-7695-2640-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala |
Software Pipelining Support for Transport Triggered Architecture Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 237-247, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Teemu Pitkänen, Risto Mäkinen, Jari Heikkinen, Tero Partanen, Jarmo Takala |
Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 227-236, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Bastian Ristau, Gerhard P. Fettweis |
An Optimization Methodology for Memory Allocation and Task Scheduling in SoCs Via Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 89-98, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Sunil Shukla, Neil W. Bergmann, Jürgen Becker 0001 |
QUKU: A Two-Level Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 109-116, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Tim Tuan, Sean Kao, Arifur Rahman, Satyaki Das, Steven Trimberger |
A 90nm low-power FPGA for battery-powered applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 3-11, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGAs, field-programmable gate arrays, low-power design, programmable logic |
10 | Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez |
A multilevel hierarchical interconnection structure for FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 225, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer |
Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 36-41, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Yan Zhang, Jussi Roivainen, Aarne Mämmelä |
Clock-Gating in FPGAs: A Novel and Comparative Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 584-590, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Enrique Soto, Elena Lago, Juan J. Rodríguez-Andina |
FPGA Implementation of High-Performance PHM / DPHM Schedulers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera |
A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Mike Hutton, Yan Lin 0001, Lei He 0001 |
Placement and Timing for FPGAs Considering Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-7, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki J. Murakami |
REDEFIS: a system with a redefinable instruction set processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 14-19, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
ISA customization, dynamically reconfigurable processor, low power, SoC, high performance |
10 | Hooman Parizi, Afshin Niktash, Amir Hosein Kamalizad, Nader Bagherzadeh |
A Reconfigurable Architecture for Wireless Communication Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Third International Conference on Information Technology: New Generations (ITNG 2006), 10-12 April 2006, Las Vegas, Nevada, USA, pp. 250-255, 2006, IEEE Computer Society, 0-7695-2497-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones |
A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 309-310, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Declan Hegarty, Steve McDonald |
An FPGA-based Configurable Network Interface System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICN/ICONS/MCL ![In: Fifth International Conference on Networking and the International Conference on Systems (ICN / ICONS / MCL 2006), 23-29 April 2006, Mauritius, pp. 167, 2006, IEEE Computer Society, 0-7695-2552-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | David Sheldon, Rakesh Kumar 0002, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen |
Application-specific customization of parameterized FPGA soft-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 261-268, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet |
Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, pp. 125-130, 2006, IEEE Computer Society, 0-7695-2620-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Mohsin A. Syed, Eberhard Schüler |
Reconfigurable Parallel Computing Architecture for On-Board Data Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 15-18 June 2006, Istanbul, Turkey, pp. 229-236, 2006, IEEE Computer Society, 0-7695-2614-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Gabriella Kókai, Tonia Christ, Hans Holm Frühauf |
Using Hardware-Based Particle Swarm Method for Dynamic Optimization of Adaptive Array Antennas. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 15-18 June 2006, Istanbul, Turkey, pp. 51-58, 2006, IEEE Computer Society, 0-7695-2614-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Rashed Zafar Bhatti, Monty Denneau, Jeff Draper |
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 198-203, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection |
10 | Vijay K. Jain, Glenn H. Chapman |
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 157-165, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
3D Heterogeneous sensor, redundancy and reconfiguration, energy economization, heterogeneous SOC, J-platform, defect tolerance |
10 | Aaron R. Kunze, Stephen D. Goglin, Erik J. Johnson |
Symerton--using virtualization to accelerate packet processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2006, San Jose, California, USA, December 3-5, 2006, pp. 133-142, 2006, ACM, 1-59593-580-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
networking, virtualization, communications systems |
10 | Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha |
Memory binding for performance optimization of control-flow intensive behavioral descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(5), pp. 513-524, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | David E. Taylor, Andreas Herkersdorf, Andreas C. Döring, Gero Dittmann |
Robust header compression (ROHC) in next-generation network processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 13(4), pp. 755-768, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ROHC, hardware assist, FPGA, ASIC, network processor, ASIP, reconfigurable hardware, header compression |
10 | Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou |
Charge-Recovery Computing on Silicon. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(6), pp. 651-659, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Energy-recovering circuits, resonant systems, energy efficient computing, voltage scaling, reversible logic, adiabatic computing |
10 | Harm Peters, Ramanathan Sethuraman, Aleksandar Beric, Patrick Meuwissen, Srinivasan Balakrishnan, Carlos A. Alba Pinto, W. M. Kruijtzer, Fabian Ernst, Ghiath Alkadi, Jef L. van Meerbergen, Gerard de Haan |
Application Specific Instruction-Set Processor Template for Motion Estimation in Video Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 15(4), pp. 508-527, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Holger Blume, H. T. Feldkämper, Tobias G. Noll |
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 40(1), pp. 19-34, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
heterogeneous systems on chip, partitioning and mapping, reconfigurable platforms, design space exploration, cost models |
10 | Claudio Talarico, Aseem Gupta, Ebenezer Peter, Jerzy W. Rozenblit |
Embedded System Engineering Using C/C++ Based Design Methodologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 12th IEEE International Conference on the Engineering of Computer-Based Systems (ECBS 2005), 4-7 April 2005, Greenbelt, MD, USA, pp. 81-88, 2005, IEEE Computer Society, 0-7695-2308-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Pankaj Golani, Peter A. Beerel |
Back Annotation in High Speed Asynchronous Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 227-236, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee |
SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 273, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti 0001 |
FPGA based Agile Algorithm-On-Demand Co-Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 82-83, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers |
Optimized Generation of Data-Path from C Codes for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 112-117, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Panu Hämäläinen, Jari Heikkinen, Marko Hännikäinen, Timo D. Hämäläinen |
Design of Transport Triggered Architecture Processors for Wireless Encryption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 144-152, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu |
LFF algorithm for heterogeneous FPGA floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1123-1126, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Rajarshi Mukherjee, Seda Ogrenci Memik |
Evaluation of dual VDD fabrics for low power FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1240-1243, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Guangyu Chen, Feihui Li, Mahmut T. Kandemir, I. Demirkiran |
Increasing FPGA resilience against soft errors using task duplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 924-927, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Sasikumar Cherubal |
Challenges in Next Generation Mixed-Signal IC Production Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 466, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Indradeep Ghosh |
High Level Test Generation for Custom Hardware: An Industrial Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 458, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Andrés David García García, Luis Fernando González Pérez, Reynaldo Félix Acuña |
Power Consumption Management on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONIELECOMP ![In: 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005 - 2 March 2005, Puebla, Mexico, pp. 240-245, 2005, IEEE Computer Society, 0-7695-2283-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Genetic Algorithms, Field Programmable Gate Array, Power Consumption, Partial Reconfiguration, Circuit Design |
10 | Pascal T. Wolkotte, Gerard J. M. Smit, Gerard K. Rauwerda, Lodewijk T. Smit |
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Mahdi Fazeli, Reza Farivar 0003, Shaahin Hessabi, Seyed Ghassem Miremadi |
A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LADC ![In: Dependable Computing, Second Latin-American Symposium, LADC 2005, Salvador, Brazil, October 25-28, 2005, Proceedings, pp. 143-153, 2005, Springer, 3-540-29572-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik |
Peak temperature control and leakage reduction during binding in high level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 251-256, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
switching, leakage, temperature, binding |
10 | Balasubramanian Sethuraman, Prasun Bhattacharya, Jawad Khan, Ranga Vemuri |
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 452-457, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
SoCRouter, FPGA, networks-on-chip |
10 | François-Xavier Standaert, Eric Peeters, Jean-Jacques Quisquater |
On the Masking Countermeasure and Higher-Order Power Analysis Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC (1) ![In: International Symposium on Information Technology: Coding and Computing (ITCC 2005), Volume 1, 4-6 April 2005, Las Vegas, Nevada, USA, pp. 562-567, 2005, IEEE Computer Society, 0-7695-2315-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso |
Is methodology the highway out of verification hell? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 521-522, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
verification, formal verification, methodology, assertions |
10 | V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi |
Design methodology for IC manufacturability based on regular logic-bricks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 353-358, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
regularity, manufacturability, integrated circuits, RET |
10 | Bin Wu, Jianwen Zhu, Farid N. Najm |
A non-parametric approach for dynamic range estimation of nonlinear systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 841-844, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dynamic range estimation, non-gaussian, independent component analysis, nonlinear, non-parametric |
10 | Alexander G. Dean |
Efficient Real-Time Fine-Grained Concurrency on Low-Cost Microcontrollers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 24(4), pp. 10-22, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Will Eatherton, George Varghese, Zubin Dittia |
Tree bitmap: hardware/software IP lookups with incremental updates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Commun. Rev. ![In: Comput. Commun. Rev. 34(2), pp. 97-122, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu 0011 |
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(11), pp. 1436-1448, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Data communications devices, application studies resulting in better multiple-processor systems, reconfigurable hardware, wireless systems, special-purpose and application-based systems, adaptable architectures, heterogeneous (hybrid) systems, design studies, signal processing systems |
10 | Kanad Chakraborty |
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(1), pp. 89-108, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
multiport RAM, BIST (built-in self-test), BISR (built-in self-repair), column-multiplexed addressing, fault tolerance, reliability, bandwidth |
10 | Wei Qin, Subramanian Rajagopalan, Sharad Malik |
A formal concurrency model based architecture description language for synthesis of software development tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 47-56, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Hendrik Seidel, Emil Matús, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard P. Fettweis |
Generated DSP Cores for Implementation of an OFDM Communication System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 353-362, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Ioannis Papaefstathiou, George Kornaros, Nicholaos Zervos |
Software Processing Performance in Network Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 186-191, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Marc Quax, Jos Huisken, Jef L. van Meerbergen |
A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 230-235, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | B. Hecker, M. Chavassieux, M. Laflutte, E. Beguin, L. Lagasse, Jean Oudinot |
VHDL-AMS Library Development for Pacemaker Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 338-341, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi |
An Interconnect Channel Design Methodology for High Performance Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1138-1143, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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