Search results for "ASICs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Maizura Mokhtar, David M. Halliday, Andy M. Tyrrell	Hippocampus-Inspired Spiking Neural Network on FPGA.	ICES	2008	DBLP DOI BibTeX RDF	Bio-inspired Hardware, FPGA, Spiking Neural Network
10	David Sheldon, Frank Vahid	Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	BRAM, high-throughput design, pattern counting, redesigning circuit, FPGA, design patterns, stream, memory, ASIC
10	Jin Hu, Jarrod A. Roy, Igor L. Markov	Sidewinder: a scalable ILP-based router.	SLIP	2008	DBLP DOI BibTeX RDF	integer linear programming, global routing
10	Marcus Komann, Alexander Kröller, Christiane Schmidt 0001, Dietmar Fey, Sándor P. Fekete	Emergent algorithms for centroid and orientation detection in high-performance embedded cameras.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	emergent algorithms, marching pixels, image processing, object detection, massively-parallel
10	Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet	Silicon-level Solutions to Counteract Passive and Active Attacks.	FDTC	2008	DBLP DOI BibTeX RDF
10	Sylvain Saïghi, Laure Buhry, Yannick Bornat, Gilles N'Kaoua, Jean Tomas, Sylvie Renaud	Adjusting the neurons models in neuromimetic ICs using the voltage-clamp technique.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Li Zhang, Shuangfei Li, Zan Yin, Wenyuan Zhao	A Research on an ASIP Processing Element Architecture Suitable for FPGA Implementation.	CSSE (3)	2008	DBLP DOI BibTeX RDF
10	Jens-Peter Kaps	Chai-Tea, Cryptographic Hardware Implementations of xTEA.	INDOCRYPT	2008	DBLP DOI BibTeX RDF	symmetric key algorithms, TEA, XTEA, FPGA, ASIC, Efficient implementation
10	Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary F. Margrave	A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator.	ASAP	2008	DBLP DOI BibTeX RDF
10	David Dickin, Lesley Shannon	Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms.	ASAP	2008	DBLP DOI BibTeX RDF
10	Kamran Zarrineh	Design for Test Challenges of High Performance/Low Power Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
10	Sandeep Gupta, Jaya Singh, Abhijit Roy	A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs.	ISQED	2008	DBLP DOI BibTeX RDF	Dual-Vt Technology, Cell-Based Approach, Cell-swapping, Leakage Power
10	Nidhir Kumar, Senthil N. Velu, Rajan Verma	Gateway to Chips: High Speed I/O Signalling and Interface.	VLSI Design	2008	DBLP DOI BibTeX RDF
10	Min Li 0001, Bruno Bougard, David Novo, Liesbet Van der Perre, Francky Catthoor	How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach.	DAC	2008	DBLP DOI BibTeX RDF	baseband, low power, wireless, SDR
10	Michela Becchi, Patrick Crowley	Efficient regular expression evaluation: theory to practice.	ANCS	2008	DBLP DOI BibTeX RDF
10	Aggelos Ioannou, Manolis Katevenis	Pipelined heap (priority queue) management for advanced scheduling in high-speed networks.	IEEE/ACM Trans. Netw.	2007	DBLP DOI BibTeX RDF	high-speed network scheduling, pipelined hard-ware heap, synthesizable core, weighted fair queueing, priority queue, weighted round robin
10	Fan-Min Li, An-Yeu Wu	On the New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
10	George Michelogiannakis, Dionisios N. Pnevmatikatos, Manolis Katevenis	Approaching Ideal NoC Latency with Pre-Configured Routes.	NOCS	2007	DBLP DOI BibTeX RDF
10	Tim Güneysu, Christof Paar, Sven Schäge	Efficient Hash Collision Search Strategies on Special-Purpose Hardware.	WEWoRC	2007	DBLP DOI BibTeX RDF	Crypto Attacks, Hash functions, Special-purpose Hardware
10	Jing Fu 0003, Olof Hagsand, Gunnar Karlsson	Queuing Behavior and Packet Delays in Network Processor Systems.	MASCOTS	2007	DBLP DOI BibTeX RDF	queueing behavior, network processor, router
10	Satish Sivaswamy, Kia Bazargan	Variation-aware routing for FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	statistical timing analysis, FPGA routing
10	David Slogsnat, Alexander Giese, Ulrich Brüning 0001	A versatile, low latency HyperTransport core.	FPGA	2007	DBLP DOI BibTeX RDF	HTX, HyperTransport, FPGA, prototyping, RTL
10	Gerald Hempel, Christian Hochberger	A resource optimized Processor Core for FPGA based SoCs.	DSD	2007	DBLP DOI BibTeX RDF
10	Yong Li 0006, Zhiying Wang 0003, Jian Ruan, Kui Dai	A Low-Power Globally Synchronous Locally Asynchronous FFT Processor.	HPCC	2007	DBLP DOI BibTeX RDF
10	A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy 0001, Ranjani Narayan	REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures.	FPL	2007	DBLP DOI BibTeX RDF
10	Gerald Hempel, Christian Hochberger	A resource optimized SoC Kit for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
10	Subhomoy Chattopadhyay	Low power design techniques for nanometer design processes: 65 nm and smaller.	SBCCI	2007	DBLP DOI BibTeX RDF	65 nm, low power, embedded design
10	A. C. H. Ng, Jan-Willem Weijers, Miguel Glassee, Thomas Schuster, Bruno Bougard, Liesbet Van der Perre	ESL design and HW/SW co-verification of high-end software defined radio platforms.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	verification, emulation, SDR, hardware/software co-design, ESL
10	Yong Li 0006, Zhiying Wang 0003, Xue-mi Zhao, Jian Ruan, Kui Dai	Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
10	Wolfgang Puffitsch, Martin Schoeberl	picoJava-II in an FPGA.	JTRES	2007	DBLP DOI BibTeX RDF	FPGA, Java processor
10	Simone Medardoni, Davide Bertozzi, Enrico Macii	Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	RTL synthesis, leakage-aware, power management, selection strategy
10	Dietmar Fey, Marcus Komann, Frank Schurz, Andreas Loos	An Organic Computing architecture for visual microprocessors based on Marching Pixels.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Atanu Chattopadhyay, Zeljko Zilic	Reconfigurable Clock Distribution Circuitry.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Hans Kristian Otnes Berge, Philipp Häfliger	High-Speed Serial AER on FPGA.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Andrew McCormick	An Engineering Approach to Solving HPC Problems using FPGAs.	AHS	2007	DBLP DOI BibTeX RDF
10	Eunjung Cho, Anu G. Bourgeois, Feng Tan	An FPGA Design to Achieve Fast and Accurate Results for Molecular Dynamics Simulations.	ISPA	2007	DBLP DOI BibTeX RDF
10	David E. Shaw, Martin M. Deneroff, Ron O. Dror, Jeffrey Kuskin, Richard H. Larson, John K. Salmon, Cliff Young, Brannon Batson, Kevin J. Bowers, Jack C. Chao, Michael P. Eastwood, Joseph Gagliardo, J. P. Grossman, C. Richard Ho, Doug Ierardi, István Kolossváry, John L. Klepeis, Timothy Layman, Christine McLeavey, Mark A. Moraes, Rolf Mueller, Edward C. Priest, Yibing Shan, Jochen Spengler, Michael Theobald, Brian Towles, Stanley C. Wang	Anton, a special-purpose machine for molecular dynamics simulation.	ISCA	2007	DBLP DOI BibTeX RDF	biomolecular system simulation, computational drug design, special-purpose machine, bioinformatics, computational biology, molecular dynamics, protein folding, protein structure
10	Piti Piyachon, Yan Luo	Compact State Machines for High Performance Pattern Matching.	DAC	2007	DBLP DOI BibTeX RDF
10	Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar	Enhancing FPGA Performance for Arithmetic Circuits.	DAC	2007	DBLP DOI BibTeX RDF
10	Amilcar do Carmo Lucas, Sven Heithecker, Rolf Ernst	FlexWAFE - A High-end Real-Time Stream Processing Library for FPGAs.	DAC	2007	DBLP DOI BibTeX RDF
10	Huai-Yi Hsu, Jih-Chiang Yeo, An-Yeu Wu	Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
10	Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Use of Computation-Unit Integrated Memories in High-Level Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Paul Royal, Mitch Halpin, Ada Gavrilovska, Karsten Schwan	Utilizing Network Processors in Distributed Enterprise Environments.	NCA	2006	DBLP DOI BibTeX RDF
10	Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala	Software Pipelining Support for Transport Triggered Architecture Processors.	SAMOS	2006	DBLP DOI BibTeX RDF
10	Teemu Pitkänen, Risto Mäkinen, Jari Heikkinen, Tero Partanen, Jarmo Takala	Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform.	SAMOS	2006	DBLP DOI BibTeX RDF
10	Bastian Ristau, Gerhard P. Fettweis	An Optimization Methodology for Memory Allocation and Task Scheduling in SoCs Via Linear Programming.	SAMOS	2006	DBLP DOI BibTeX RDF
10	Sunil Shukla, Neil W. Bergmann, Jürgen Becker 0001	QUKU: A Two-Level Reconfigurable Architecture.	ISVLSI	2006	DBLP DOI BibTeX RDF
10	Tim Tuan, Sean Kao, Arifur Rahman, Satyaki Das, Steven Trimberger	A 90nm low-power FPGA for battery-powered applications.	FPGA	2006	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, programmable logic
10	Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez	A multilevel hierarchical interconnection structure for FPGA.	FPGA	2006	DBLP DOI BibTeX RDF
10	Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer	Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
10	Yan Zhang, Jussi Roivainen, Aarne Mämmelä	Clock-Gating in FPGAs: A Novel and Comparative Evaluation.	DSD	2006	DBLP DOI BibTeX RDF
10	Enrique Soto, Elena Lago, Juan J. Rodríguez-Andina	FPGA Implementation of High-Performance PHM / DPHM Schedulers.	FPL	2006	DBLP DOI BibTeX RDF
10	Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera	A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.	FPL	2006	DBLP DOI BibTeX RDF
10	Mike Hutton, Yan Lin 0001, Lei He 0001	Placement and Timing for FPGAs Considering Variations.	FPL	2006	DBLP DOI BibTeX RDF
10	Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki J. Murakami	REDEFIS: a system with a redefinable instruction set processor.	SBCCI	2006	DBLP DOI BibTeX RDF	ISA customization, dynamically reconfigurable processor, low power, SoC, high performance
10	Hooman Parizi, Afshin Niktash, Amir Hosein Kamalizad, Nader Bagherzadeh	A Reconfigurable Architecture for Wireless Communication Systems.	ITNG	2006	DBLP DOI BibTeX RDF
10	Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones	A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture.	FCCM	2006	DBLP DOI BibTeX RDF
10	Declan Hegarty, Steve McDonald	An FPGA-based Configurable Network Interface System.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF
10	David Sheldon, Rakesh Kumar 0002, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen	Application-specific customization of parameterized FPGA soft-core processors.	ICCAD	2006	DBLP DOI BibTeX RDF
10	Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet	Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor.	IOLTS	2006	DBLP DOI BibTeX RDF
10	Mohsin A. Syed, Eberhard Schüler	Reconfigurable Parallel Computing Architecture for On-Board Data Processing.	AHS	2006	DBLP DOI BibTeX RDF
10	Gabriella Kókai, Tonia Christ, Hans Holm Frühauf	Using Hardware-Based Particle Swarm Method for Dynamic Optimization of Adaptive Array Antennas.	AHS	2006	DBLP DOI BibTeX RDF
10	Rashed Zafar Bhatti, Monty Denneau, Jeff Draper	2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection
10	Vijay K. Jain, Glenn H. Chapman	Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC.	DFT	2006	DBLP DOI BibTeX RDF	3D Heterogeneous sensor, redundancy and reconfiguration, energy economization, heterogeneous SOC, J-platform, defect tolerance
10	Aaron R. Kunze, Stephen D. Goglin, Erik J. Johnson	Symerton--using virtualization to accelerate packet processing.	ANCS	2006	DBLP DOI BibTeX RDF	networking, virtualization, communications systems
10	Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha	Memory binding for performance optimization of control-flow intensive behavioral descriptions.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
10	David E. Taylor, Andreas Herkersdorf, Andreas C. Döring, Gero Dittmann	Robust header compression (ROHC) in next-generation network processors.	IEEE/ACM Trans. Netw.	2005	DBLP DOI BibTeX RDF	ROHC, hardware assist, FPGA, ASIC, network processor, ASIP, reconfigurable hardware, header compression
10	Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou	Charge-Recovery Computing on Silicon.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Energy-recovering circuits, resonant systems, energy efficient computing, voltage scaling, reversible logic, adiabatic computing
10	Harm Peters, Ramanathan Sethuraman, Aleksandar Beric, Patrick Meuwissen, Srinivasan Balakrishnan, Carlos A. Alba Pinto, W. M. Kruijtzer, Fabian Ernst, Ghiath Alkadi, Jef L. van Meerbergen, Gerard de Haan	Application Specific Instruction-Set Processor Template for Motion Estimation in Video Applications.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
10	Holger Blume, H. T. Feldkämper, Tobias G. Noll	Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	heterogeneous systems on chip, partitioning and mapping, reconfigurable platforms, design space exploration, cost models
10	Claudio Talarico, Aseem Gupta, Ebenezer Peter, Jerzy W. Rozenblit	Embedded System Engineering Using C/C++ Based Design Methodologies.	ECBS	2005	DBLP DOI BibTeX RDF
10	Pankaj Golani, Peter A. Beerel	Back Annotation in High Speed Asynchronous Design.	PATMOS	2005	DBLP DOI BibTeX RDF
10	Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee	SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
10	Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti 0001	FPGA based Agile Algorithm-On-Demand Co-Processor.	DATE	2005	DBLP DOI BibTeX RDF
10	Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers	Optimized Generation of Data-Path from C Codes for FPGAs.	DATE	2005	DBLP DOI BibTeX RDF
10	Panu Hämäläinen, Jari Heikkinen, Marko Hännikäinen, Timo D. Hämäläinen	Design of Transport Triggered Architecture Processors for Wireless Encryption.	DSD	2005	DBLP DOI BibTeX RDF
10	Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu	LFF algorithm for heterogeneous FPGA floorplanning.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Rajarshi Mukherjee, Seda Ogrenci Memik	Evaluation of dual VDD fabrics for low power FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Guangyu Chen, Feihui Li, Mahmut T. Kandemir, I. Demirkiran	Increasing FPGA resilience against soft errors using task duplication.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Sasikumar Cherubal	Challenges in Next Generation Mixed-Signal IC Production Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
10	Indradeep Ghosh	High Level Test Generation for Custom Hardware: An Industrial Perspective.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
10	Andrés David García García, Luis Fernando González Pérez, Reynaldo Félix Acuña	Power Consumption Management on FPGAs.	CONIELECOMP	2005	DBLP DOI BibTeX RDF	Genetic Algorithms, Field Programmable Gate Array, Power Consumption, Partial Reconfiguration, Circuit Design
10	Pascal T. Wolkotte, Gerard J. M. Smit, Gerard K. Rauwerda, Lodewijk T. Smit	An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip.	IPDPS	2005	DBLP DOI BibTeX RDF
10	Mahdi Fazeli, Reza Farivar 0003, Shaahin Hessabi, Seyed Ghassem Miremadi	A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems.	LADC	2005	DBLP DOI BibTeX RDF
10	Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik	Peak temperature control and leakage reduction during binding in high level synthesis.	ISLPED	2005	DBLP DOI BibTeX RDF	switching, leakage, temperature, binding
10	Balasubramanian Sethuraman, Prasun Bhattacharya, Jawad Khan, Ranga Vemuri	LiPaR: A light-weight parallel router for FPGA-based networks-on-chip.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	SoCRouter, FPGA, networks-on-chip
10	François-Xavier Standaert, Eric Peeters, Jean-Jacques Quisquater	On the Masking Countermeasure and Higher-Order Power Analysis Attacks.	ITCC (1)	2005	DBLP DOI BibTeX RDF
10	Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso	Is methodology the highway out of verification hell?	DAC	2005	DBLP DOI BibTeX RDF	verification, formal verification, methodology, assertions
10	V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi	Design methodology for IC manufacturability based on regular logic-bricks.	DAC	2005	DBLP DOI BibTeX RDF	regularity, manufacturability, integrated circuits, RET
10	Bin Wu, Jianwen Zhu, Farid N. Najm	A non-parametric approach for dynamic range estimation of nonlinear systems.	DAC	2005	DBLP DOI BibTeX RDF	dynamic range estimation, non-gaussian, independent component analysis, nonlinear, non-parametric
10	Alexander G. Dean	Efficient Real-Time Fine-Grained Concurrency on Low-Cost Microcontrollers.	IEEE Micro	2004	DBLP DOI BibTeX RDF
10	Will Eatherton, George Varghese, Zubin Dittia	Tree bitmap: hardware/software IP lookups with incremental updates.	Comput. Commun. Rev.	2004	DBLP DOI BibTeX RDF
10	Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu 0011	Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Data communications devices, application studies resulting in better multiple-processor systems, reconfigurable hardware, wireless systems, special-purpose and application-based systems, adaptable architectures, heterogeneous (hybrid) systems, design studies, signal processing systems
10	Kanad Chakraborty	Testing and Reliability Techniques for High-Bandwidth Embedded RAMs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	multiport RAM, BIST (built-in self-test), BISR (built-in self-repair), column-multiplexed addressing, fault tolerance, reliability, bandwidth
10	Wei Qin, Subramanian Rajagopalan, Sharad Malik	A formal concurrency model based architecture description language for synthesis of software development tools.	LCTES	2004	DBLP DOI BibTeX RDF
10	Hendrik Seidel, Emil Matús, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard P. Fettweis	Generated DSP Cores for Implementation of an OFDM Communication System.	SAMOS	2004	DBLP DOI BibTeX RDF
10	Ioannis Papaefstathiou, George Kornaros, Nicholaos Zervos	Software Processing Performance in Network Processors.	DATE	2004	DBLP DOI BibTeX RDF
10	Marc Quax, Jos Huisken, Jef L. van Meerbergen	A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver.	DATE	2004	DBLP DOI BibTeX RDF
10	B. Hecker, M. Chavassieux, M. Laflutte, E. Beguin, L. Lagasse, Jean Oudinot	VHDL-AMS Library Development for Pacemaker Applications.	DATE	2004	DBLP DOI BibTeX RDF
10	Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi	An Interconnect Channel Design Methodology for High Performance Integrated Circuits.	DATE	2004	DBLP DOI BibTeX RDF