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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6285 occurrences of 1975 keywords
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Results
Found 21486 publication records. Showing 21486 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
31 | Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek |
Low energy FPGA interconnect design. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Khaled Benkrid, S. Sukhsawas, Danny Crookes, Samir Belkacemi |
A single-FPGA implementation of image connected component labelling. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Frank Honoré, Benton H. Calhoun, Anantha P. Chandrakasan |
Power-aware architectures and circuits for FPGA-based signal processing. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Soheil Ghiasi, Karlene Nguyen, Elaheh Bozorgzadeh, Majid Sarrafzadeh |
On computation and resource management in an FPGA-based computation environment. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
31 | M. A. Hannan Bin Azhar, Keith R. Dimond |
FPGA-based design of an evolutionary controller for collision-free robot navigation. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Yongquan Fan, Zeljko Zilic |
Testing for bit error rate in FPGA communication interfaces. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Li Shang, Alireza Kaviani, Kusuma Bathala |
Dynamic power consumption in Virtex[tm]-II FPGA family. |
FPGA |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Ryan N. Schneider, Laurence E. Turner, Michal M. Okoniewski |
Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method. |
FPGA |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Alireza Kaviani, Stephen Dean Brown |
Technology mapping issues for an FPGA with lookup tables and PLA-like blocks. |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Elias Ahmed, Jonathan Rose |
The effect of LUT and cluster size on deep-submicron FPGA performance and density. |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Amit Singh 0001, Luca Macchiarulo, Arindam Mukherjee 0001, Malgorzata Marek-Sadowska |
A novel high throughput reconfigurable FPGA architecture. |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Hyuk-Jun Lee, Michael J. Flynn |
Coarse-grained carry architecture for FPGA (poster abstract). |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
31 | James R. Anderson 0001, Siddharth Sheth, Kaushik Roy 0001 |
A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering. |
FPGA |
1998 |
DBLP DOI BibTeX RDF |
finite impluse response filtering, field programmable gate array, architecture, digital signal processing |
31 | Mohammed A. S. Khalid, Jonathan Rose |
A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems. |
FPGA |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Shashidhar Thakur, D. F. Wong 0001 |
On Designing ULM-based FPGA Logic Modules. |
FPGA |
1995 |
DBLP DOI BibTeX RDF |
|
31 | Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois 0001 |
The Design of RPM: An FPGA-based Multiprocessor Emulator. |
FPGA |
1995 |
DBLP DOI BibTeX RDF |
field-programmable gate arrays, VHDL, rapid prototyping, shared-memory multiprocessors, logic emulation, message-passing multicomputers |
31 | Jason Cong, Yuzheng Ding |
On Nominal Delay Minimization in LUT-based FPGA Technology Mapping. |
FPGA |
1995 |
DBLP DOI BibTeX RDF |
|
30 | Uday Bondhugula, J. Ramanujam, P. Sadayappan |
Automatic mapping of nested loops to FPGAS. |
PPoPP |
2007 |
DBLP DOI BibTeX RDF |
FPGA compilation, control signals, regular processor arrays, scheduling, FPGA, resource constraints, nested loops, linear transformation |
29 | Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro |
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. |
J. Electron. Test. |
2007 |
DBLP DOI BibTeX RDF |
reliability, fault tolerant systems, SEU, SRAM-based FPGA |
29 | Roman L. Lysecky, Greg Stitt, Frank Vahid |
Warp Processors. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
FPGA, dynamic optimization, hardware/software codesign, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation |
29 | Xuejun Liang |
Computation core binding in GTM mapping on reconfigurable computers. |
ACM Southeast Regional Conference |
2006 |
DBLP DOI BibTeX RDF |
FPGA, combinatorial optimization, high-level synthesis, reconfigurable computing, template matching |
29 | R. Manimegalai, E. Siva Soumya, Vaishnavi Muralidharan, Balaraman Ravindran, V. Kamakoti 0001, D. Bhatia |
Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
Three-Dimensional FPGA, Reinforcement Learning (RL), Two-opt algorithm, Support Vector Machines (SVMs), Placement and Routing |
29 | Srihari Cadambi, Chandra Mulpuri, Pranav Ashar |
A fast, inexpensive and scalable hardware acceleration technique for functional simulation. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
FPGA, hardware acceleration, VLIW, functional simulation |
29 | Lijun Gao, Sarvesh Shrivastava, Gerald E. Sobelman |
Elliptic Curve Scalar Multiplier Design Using FPGAs. |
CHES |
1999 |
DBLP DOI BibTeX RDF |
FPGA, public-key cryptography, elliptic curves, reconfigurable hardware, scalar multiplication, Galois field, coprocessor |
29 | Koichi Shimizu, Daisuke Suzuki, Toyohiro Tsurumaru |
High-Speed Search System for PGP Passphrases. |
CANS |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Kostas Siozios, Dimitrios Soudris |
A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Xiaojun Wang, Miriam Leeser |
K-means Clustering for Multispectral Images Using Floating-Point Divide. |
FCCM |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Fei Li 0003, Yizhou Lin, Lei He 0001, Deming Chen, Jason Cong |
Power modeling and characteristics of field programmable gate arrays. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Diana Göhringer, Michael Hübner 0001, Michael Benz, Jürgen Becker 0001 |
A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only). |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
designflow, toolchain, fpga, partitioning, reconfigurable computing, mpsoc, hardware/software co-design |
28 | Chen Chen 0018, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra |
Efficient FPGAs using nanoelectromechanical relays. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
CMOS-NEM FPGA, nanoelectromechanical relay |
28 | Jan R. Frigo, Eric Y. Raby, Sean M. Brennan, Christophe Wolinski, Charles Wagner, François Charot, Edward Rosten, Vinod Kulathumani |
Energy efficient sensor node implementations. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
distributed sensor network (dsn), seismic, fpga, video, acoustic, vehicle classification, dsp |
28 | Alan Mishchenko, Robert K. Brayton, Stephen Jang |
Global delay optimization using structural choices. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
technology mpping, FPGA, interpolation, windowing, boolean satisfiability, logic optimization |
28 | Mike Brugge, Mohammed A. S. Khalid |
Design and evaluation of a parameterizable NoC router for FPGAs (abstract only). |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
fpga, architecture, system-on-chip, network-on-chip, design space exploration, router |
28 | Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro |
Programming high performance signal processing systems in high level languages. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
high level programming models, fpga, signal processing, dsp |
28 | David B. Thomas, Lee W. Howes, Wayne Luk |
A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
mppa, fpga, monte-carlo, random numbers, gpu |
28 | Cristinel Ababei |
Parallel placement for FPGAs revisited. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
fpga placement, multithreading, parallel simulated annealing |
28 | Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang |
Scalable don't-care-based logic optimization and resynthesis. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
fpga, interpolation, windowing, technology mapping, boolean satisfiability, logic optimization |
28 | Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger |
CMOS vs Nano: comrades or rivals? |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
fpga, nanotechnology |
28 | Sumanta Chaudhuri |
Diagonal tracks in FPGAs: a performance evaluation. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
diagonal tracks, octagonal, fpga, hexagonal |
28 | Johnny Tsung Lin Ho, Guy G. Lemieux |
PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
fpga, pattern matching, regular expression, antivirus |
28 | Jason Cong, Karthik Gururaj, Bin Liu 0006, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou |
Revisiting bitwidth optimizations. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
fixed-poin, fpga, arithmetic, bitwidth |
28 | Paul Edward McKechnie, Nathan A. Lindop, Wim Vanderbauwhede |
A type system for static typing of a domain-specific language. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
static type checking, FPGA, type system |
28 | Guy G. Lemieux, Tarek A. El-Ghazawi |
Designing with extreme parallelism. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
custom compute engine, high-level electronic design, FPGA, parallel processing, reconfigurable computing, hardware description language |
28 | Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera |
Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
FPGA, routing, variation, yield enhancement |
28 | Tarek A. El-Ghazawi, Guy G. Lemieux |
Extreme parallel architectures for the masses. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
custom compute engine, FPGA, parallel processing, reconfigurable computing |
28 | Yan Lin 0001, Lei He 0001 |
Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation. |
FPGA |
2007 |
DBLP DOI BibTeX RDF |
FPGA, uncertainty, process variation, stochastic, physical synthesis |
28 | Kenneth Eguro, Scott Hauck |
Armada: timing-driven pipeline-aware routing for FPGAs. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
pipeline FPGA, pipeline routing, reconfigurable computing |
28 | Michael DeLorimier, André DeHon |
Floating-point sparse matrix-vector multiply for FPGAs. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
compressed sparse row, FPGA, reconfigurable architecture, floating point, sparse matrix |
28 | David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose |
The Stratix II logic and routing architecture. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
logic module, FPGA, routing |
28 | Keith D. Underwood |
FPGAs vs. CPUs: trends in peak floating-point performance. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
FPGA, supercomputing, floating point, trends |
28 | Paul Kohlbrenner, Kris Gaj |
An embedded true random number generator for FPGAs. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
TRNG, FPGA, random numbers, RNG, cryptographic |
28 | Arifur Rahman, Vijay Polavarapuv |
Evaluation of low-leakage design techniques for field programmable gate arrays. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
FPGA, leakage power, multiplexer |
28 | Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter |
A reconfigurable unit for a clustered programmable-reconfigurable processor. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
FPGA, technology scaling, reconfigurable processor |
28 | Chen Chang, Kimmo Kuusilinna, Brian C. Richards, Robert W. Brodersen |
Implementation of BEE: a real-time large-scale hardware emulation engine. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
hardware emulation, FPGA, rapid-prototyping |
28 | Andrea Lodi 0002, Mario Toma, Fabio Campi |
A pipelined configurable gate array for embedded processors. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
FPGA, pipeline, energy, reconfigurable processor |
28 | Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton |
Architectures and algorithms for synthesizable embedded programmable logic cores. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
programmable logic cores, FPGA, standard cells, system-on-chip design |
28 | Jason Cong, Yizhou Lin, Wangning Long |
SPFD-based global rewiring. |
FPGA |
2002 |
DBLP DOI BibTeX RDF |
FPGA synthesis, SPFD, SPFD-based global rewiring, logical re-synthesis |
28 | Shawn Phillips, Scott Hauck |
Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip. |
FPGA |
2002 |
DBLP DOI BibTeX RDF |
automatic layout generation, domain-specific FPGA, system-on a-chip, standard cells |
28 | Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev |
Interconnect enhancements for a high-speed PLD architecture. |
FPGA |
2002 |
DBLP DOI BibTeX RDF |
FPGA, architecture, interconnect, programmable logic |
28 | Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang |
Performance-driven mapping for CPLD architectures. |
FPGA |
2001 |
DBLP DOI BibTeX RDF |
PLA-style logic cells, FPGA, technology mapping, CPLD, delay optimization |
28 | Peter Hallschmid, Steven J. E. Wilton |
Detailed routing architectures for embedded programmable logic IP cores. |
FPGA |
2001 |
DBLP DOI BibTeX RDF |
FPGA, programmable logic, detailed routing, SoC design, embedded cores |
28 | Peter Kollig, Bashir M. Al-Hashimi |
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs. |
FPGA |
1999 |
DBLP DOI BibTeX RDF |
bit-level pipelined, circuit latency, FPGA, recursive algorithms |
28 | Alan Marshall, Tony Stansfield, Igor Kostarnov, Jean Vuillemin, Brad L. Hutchings |
A Reconfigurable Arithmetic Array for Multimedia Application. |
FPGA |
1999 |
DBLP DOI BibTeX RDF |
4-bit ALU, FPGA, multimedia, reconfigurable computing |
28 | Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar |
Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. |
FPGA |
1999 |
DBLP DOI BibTeX RDF |
conflict-directed search, Boolean satisfiability, FPGA routing |
28 | Jeffrey A. Jacob, Paul Chow |
Memory Interfacing and Instruction Specification for Reconfigurable Processors. |
FPGA |
1999 |
DBLP DOI BibTeX RDF |
memory interfacing, FPGA, reconfigurable computer, reconfigurable processor, memory coherence |
28 | Ray Bittner, Peter M. Athanas |
Wormhole Run-Time Reconfiguration. |
FPGA |
1997 |
DBLP DOI BibTeX RDF |
FPGA, VLSI, digital signal processing, data flow, configurable computing |
28 | Jason Lee, Lesley Shannon |
Predicting the performance of application-specific NoCs implemented on FPGAs. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
performance, FPGAs, topologies, heterogeneous, NoCs, homogeneous, application-specific, routability |
28 | Jing Yan, Ningyi Xu, Xiongfei Cai, Rui Gao, Yu Wang 0002, Rong Luo, Feng-Hsiung Hsu |
LambdaRank acceleration for relevance ranking in web search engines (abstract only). |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
lambdarank algorithms |
28 | Raphael Rubin, André DeHon |
Choose-your-own-adventure routing: lightweight load-time defect avoidance. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
bitstream load, in-field repair, defect tolerance, alternatives, programmable interconnect |
28 | Qiang Wang, Subodh Gupta, Jason Helge Anderson |
Clock power reduction for virtex-5 FPGAs. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking |
28 | Narges Bani Asadi, Teresa H. Meng, Wing Hung Wong |
Reconfigurable computing for learning Bayesian networks. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
Bayesian networks, reconfigurable computing, Markov chain Monte Carlo |
28 | Wenyi Feng, Jonathan W. Greene |
Post-placement interconnect entropy. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shibata, Keiichi Yasumoto, Minoru Ito |
Flexible implementation of genetic algorithms on FPGAs. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Vikas Aggarwal, Alan D. George, K. Clint Slatton |
Reconfigurable computing with multiscale data fusion for remote sensing. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Heidi E. Ziegler, Mary W. Hall |
Evaluating heuristics in automatically mapping multi-loop applications to FPGAs. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
high-level and architectural synthesis, parallelizing compiler analysis techniques, synthesis techniques for configurable computing, FPGAs, pipelining, rapid prototyping, hardware design |
28 | Satish Sivaswamy, Gang Wang 0015, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh |
HARP: hard-wired routing pattern FPGAs. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Mohamed Taher, Esam El-Araby, Tarek A. El-Ghazawi, Kris Gaj |
Image processing library for reconfigurable computers (abstract only). |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Song Peng, David Fang, John Teifel, Rajit Manohar |
Automated synthesis for asynchronous FPGAs. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
asychronous circuits, programmable logic, automated synthesis |
28 | Phan Cong Vinh, Jonathan P. Bowen |
An algorithmic approach by heuristics to dynamical reconfiguration of logic resources on reconfigurable FPGAs. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Bret Woz, Andreas E. Savakis |
A VHDL MPEG-7 shape descriptor extractor. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
28 | André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica |
What is the right model for programming and using modern FPGAs? |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi |
SPFD-based one-to-many rewiring. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Bo Yang 0010, Ramesh Karri, David A. McGrew |
Divide and concatenate: a scalable hardware architecture for universal MAC. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Remy Eskinazi Sant'Anna, Manoel Eusébio de Lima, Paulo Romero Martins Maciel |
A left-edge algorithm approach for scheduling and allocation of hardware contexts in dynamically reconfigurable architectures. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Alex K. Jones, Prithviraj Banerjee |
An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Katherine Compton, Scott Hauck |
Track placement: orchestrating routing structures to maximize routability. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Pedro C. Diniz, Joonseok Park |
Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structures. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Mehdi Baradaran Tahoori |
Application-dependent testing of FPGAs for bridging faults. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Zhiyuan Li 0008, Scott Hauck |
Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. |
FPGA |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Deshanand P. Singh, Stephen Dean Brown |
Integrated retiming and placement for field programmable gate arrays. |
FPGA |
2002 |
DBLP DOI BibTeX RDF |
|
28 | K. K. Lee, D. F. Wong 0001 |
LRoute: a delay minimal router for hierarchical CPLDs. |
FPGA |
2001 |
DBLP DOI BibTeX RDF |
complex programmable logic devices, routing, hierarchical model, Lagrangian relaxation |
28 | Lorenz Huelsbergen |
A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms. |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
28 | John W. Lockwood, Jonathan S. Turner, David E. Taylor |
Field programmable port extender (FPX) for distributed routing and queuing. |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Yu-Chung Lin, Su-Feng Tseng, Tsai-Ming Hsieh |
Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract). |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Eric K. Pauer, Paul D. Fiore, John M. Smith, Cory S. Myers |
Algorithm analysis and mapping environment for adaptive computing systems (poster abstract). |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Zhi Alex Ye, U. Nagaraj Shenoy, Prithviraj Banerjee |
A C compiler for a processor with a reconfigurable functional unit. |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Stephan W. Gehring, Stefan H.-M. Ludwig |
Fast Integrated Tools for Circuit Design with FPGAs. |
FPGA |
1998 |
DBLP DOI BibTeX RDF |
|
28 | Larry McMurchie, Carl Ebeling |
PathFinder: A Negotiation-based Performance-driven Router for FPGAs. |
FPGA |
1995 |
DBLP DOI BibTeX RDF |
|
28 | Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic |
Architecture of Centralized Field-Configurable Memory. |
FPGA |
1995 |
DBLP DOI BibTeX RDF |
|
28 | Kang Yi, Seong Yong Ohm |
A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
Cell Matching, FPGA Technology Mapping, FPGA Synthesis |
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