Search results for "Semiconductors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
13	Meigen Shen, Li-Rong Zheng 0001, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen	Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach.	ISQED	2005	DBLP DOI BibTeX RDF
13	María del Milagro Bolado, Hector Posadas, Javier Castillo, Pablo Huerta, Pablo Sánchez, Carlos Sánchez, Häkan Fouren, Francisco Blasco	Platform Based on Open-Source Cores for Industrial Applications.	DATE	2004	DBLP DOI BibTeX RDF
13	José Mariano Fernández Nava, Pedro Bañuelos Sánchez	Stacked Multicell Converter Controlled by DSP.	CONIELECOMP	2004	DBLP DOI BibTeX RDF
13	Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor	The State-of-Art and Future Trends in Testing Embedded Memories.	MTDT	2004	DBLP DOI BibTeX RDF
13	Ho-Ick Suk	Information Security in Korea IT839 Strategy.	ASIACRYPT	2004	DBLP DOI BibTeX RDF
13	Kikuo Okuyama, Wuled Lenggoro, Toru Iwaki	Nanoparticle Preparation and Its Application - A Nanotechnology Particle Project in Japan.	ICMENS	2004	DBLP DOI BibTeX RDF
13	Chintan Patel, Abhishek Singh 0001, Jim Plusquellic	Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement.	ITC	2004	DBLP DOI BibTeX RDF
13	Sandip Kundu, T. M. Mak, Rajesh Galivanche	Trends in manufacturing test methods and their implications.	ITC	2004	DBLP DOI BibTeX RDF
13	Cor Claeys	Technological Challenges of Advanced CMOS Processing and Their Impact on Design Aspects.	VLSI Design	2004	DBLP DOI BibTeX RDF
13	Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah	Is statistical timing statistically significant?	DAC	2004	DBLP DOI BibTeX RDF
13	Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif	Optimal decoupling capacitor sizing and placement for standard-cell layout designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
13	Ming-Yueh Tsay, Hong Xu, Chia-wen Wu	Author co-citation analysis of semiconductor literature.	Scientometrics	2003	DBLP DOI BibTeX RDF
13	Ming-Yueh Tsay, Hong Xu, Chia-wen Wu	Journal co-citation analysis of semiconductor literature.	Scientometrics	2003	DBLP DOI BibTeX RDF
13	Thierry J.-F. Omnés, Gerard Postuma, Jos Verhaegh, Marleen Boonen, Nick Gatherer	Using SSDE for USB2.0 conformance co-verification.	MEMOCODE	2003	DBLP DOI BibTeX RDF
13	Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose	Automatic transistor and physical design of FPGA tiles from an architectural specification.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
13	Sergey Smirnov, Hans Kosina, Mihail Nedjalkov, Siegfried Selberherr	A Zero Field Monte Carlo Algorithm Accounting for the Pauli Exclusion Principle.	LSSC	2003	DBLP DOI BibTeX RDF
13	Roger Barth	ITRS Commodity Memory Roadmap.	MTDT	2003	DBLP DOI BibTeX RDF
13	Giacomo Giorgi, Filippo De Angelis, Nazzareno Re, Antonio Sgamellotti	Theoretical Analysis on Mechanisms Implied in Hybrid Integrated Circuit Building.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF
13	Arzu Sardarli, Igor M. Filanovsky, R. M. Sardarli, O. A. Samedov, I. Sh. Sadigov, A. I. Aslanov	Translation of the Phase Transition Temperature in TlInS2 Crystals with Cationic Impurity Doping.	ICMENS	2003	DBLP DOI BibTeX RDF
13	Miguel Ângelo M. Madureira, Paulo M. P. Monteiro, Rui L. Aguiar, Manuel Violas, M. Gloanec, E. Leclerc, Bernard Lefebvre	Broad-band transimpedance amplifier for multigigabit-per-second (40 Gbps) optical communication systems in 0.135µm PHEMT technology.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
13	Abhijit Prasad, D. M. H. Walker	Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors.	DFT	2003	DBLP DOI BibTeX RDF
13	Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger	Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model.	VTS	2003	DBLP DOI BibTeX RDF
13	Kaushik Roy 0001, T. M. Mak, Kwang-Ting Cheng	Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits.	VTS	2003	DBLP DOI BibTeX RDF
13	A. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, James D. Meindl	Electrical and optical clock distribution networks for gigascale microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
13	Stefan Schoen, Helmut Degen, Nuray M. Aykin, Arnold Rudorfer, Xiaowei Yuan	Siemens AG.	Interactions	2002	DBLP DOI BibTeX RDF
13	Kaustav Banerjee, Amit Mehrotra	Analysis of on-chip inductance effects for distributed RLC interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
13	Chih-Wen Lu, Chung-Len Lee 0001, Chauchin Su, Jwu-E Chen	Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	VLSI, IDDQ testing, deep sub-micron
13	Rajesh Gupta 0001	Sustaining an Industry Obsession.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
13	Juan Antonio Carballo, Sani R. Nassif	Impact of Technology in Power-Grid-Induced Noise.	PATMOS	2002	DBLP DOI BibTeX RDF
13	Geoffrey C.-F. Yeap	Leakage current in low standby power and high performance devices: trends and challenges.	ISPD	2002	DBLP DOI BibTeX RDF	gate tunneling leakage, low standby power, off-state sub-threshold leakage, system-on-a-ship (SoC), high performance, CMOS technology, leakage current
13	Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif	An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.	ISPD	2002	DBLP DOI BibTeX RDF	adjoint sensitivity, optimization, placement, ASICs, decoupling capacitor, power grid noise
13	Matthew M. Ziegler, Mircea R. Stan	A Case for CMOS/nano co-design.	ICCAD	2002	DBLP DOI BibTeX RDF
13	Sani R. Nassif, Onsi Fakhouri	Technology trends in power-grid-induced noise.	SLIP	2002	DBLP DOI BibTeX RDF	power grid noise
13	Todor V. Gurov, Paula A. Whitlock, Ivan Dimov 0001	Monte Carlo and Quasi-Monte Carlo Algorithms for the Barker-Ferry Equation with Low Complexity.	Numerical Methods and Application	2002	DBLP DOI BibTeX RDF
13	Santanu Dutta	Architecture and design of NX-2700: a programmable single-chip HDTV all-format-decode-and-display processor.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
13	Peter Meuris, Wim Schoenmaker, Wim Magnus	Strategy for electromagnetic interconnect modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
13	Hai Zhou 0001, Adnan Aziz	Buffer minimization in pass transistor logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
13	Santanu Dutta, Rune Jensen, Alf Rieckmann	Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
13	Ralf Brederlow, Werner Weber, Joseph Sauerer, Stéphane Donnay, Piet Wambacq, Maarten Vertregt	A Mixed-Signal Design Roadmap.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
13	Thomas L. Sterling	An Introduction to the Gilgamesh PIM Architecture.	Euro-Par	2001	DBLP DOI BibTeX RDF
13	Renato P. Ribas, F. Rudge Barbosa, N. Turatti	Integrated Circuits Design Teaching Using Professional CAD Environments.	MSE	2001	DBLP DOI BibTeX RDF
13	Stanislaw P. Maj, D. Veal, Rick Duley	A proposed new high level abstraction for computer technology.	SIGCSE	2001	DBLP DOI BibTeX RDF	computer technology education, constructivisim, modeling
13	Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl	A minimum total power methodology for projecting limits on CMOS GSI.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
13	Dennis Sylvester, Kurt Keutzer	A global wiring paradigm for deep submicron design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
13	Santanu Dutta	Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip.	PATMOS	2000	DBLP DOI BibTeX RDF
13	Kees Veelenturf	The Road to Better Reliability and Yield Embedded DfM Tools.	DATE	2000	DBLP DOI BibTeX RDF	wire spreading, yield prediction, yield improvement, DfM
13	Chih-Wen Lu, Chauchin Su, Chung-Len Lee 0001, Jwu E. Chen	Is IDDQ testing not applicable for deep submicron VLSI in year 2011?	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	deep submicron VLSI, IDDQ current estimation, random process deviations, IDDQ distributions, VLSI, statistical analysis, integrated circuit testing, CMOS integrated circuits, leakage currents, IDDQ testing, statistical approach, standard deviation, input vectors, circuit size
13	Aart J. de Geus	Slap it Together and Ship it!	ISQED	2000	DBLP DOI BibTeX RDF
13	John M. Cohn, Rob A. Rutenbar, Steve J. Young, Chris Malachowsky, Luis Aldaz	Case studies: Chip design on the bleeding edge (panel session abstract).	DAC	2000	DBLP DOI BibTeX RDF
13	Carl Pixley, Vigyan Singhal	Model Checking: A Hardware Design Perspective.	Int. J. Softw. Tools Technol. Transf.	1999	DBLP DOI BibTeX RDF	Automated mathematical methods, Model checking, Formal Verification, Binary decision diagrams, Integrated circuits, Hardware verification
13	Octavian-Dumitru Mocanu, Joan Oliver	Fault-Tolerant Memory Architecture Against Radiation-Dependent Errors: A Mixed Error Control Approach.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	hamming SEC code, latch-up, memory system, single event upset, built-in current sensor
13	M. Giangi, Daniela Mansutti, G. Richelli	Steady 3D Flow Configurations for the Horizontal Thermal Convection with Thermocapillary Effects.	J. Sci. Comput.	1999	DBLP DOI BibTeX RDF	Numerical simulation, Navier-Stokes, heat-transfer, convection
13	Theo A. C. M. Claasen	The Changing Semiconductor Industry: From Components to Silicon Systems.	EUROMICRO	1999	DBLP DOI BibTeX RDF
13	Hoda S. Abdel-Aty-Zohdy, Mahmoud Al-Nsour	Digital Neural Processing Unit for Electronic Nose.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Neural Networks, Reinforcement Learning, ASIC, Digital Design, Electronic Nose
13	Hugo De Man	Design Technology Research and Education for Deep-Submicron Systems of the Next Century.	VTS	1999	DBLP DOI BibTeX RDF
13	Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl	Minimum supply voltage for bulk Si CMOS GSI.	ISLPED	1998	DBLP DOI BibTeX RDF
13	Xinghai Tang, Vivek De, James D. Meindl	Intrinsic MOSFET parameter fluctuations due to random dopant placement.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
13	Wayne Wei-Ming Dai	Chip Parasitic Extraction and Signal Integrity Verification (Extended Abstract).	DAC	1997	DBLP DOI BibTeX RDF
13	Aurelio Pellegrini, Luigi Colalongo, Marina Valdinoci, Massimo Rudan	AC analysis of amorphous silicon devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
13	Steven D. Millman	Improving quality: Yield versus test coverage.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	quality, Fault modeling, yield, test economics, physical defects
13	Gerhard K. M. Wachutka	Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF