Search results for "Virtex"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
8	Miquel Pericàs, Ricardo Chaves, Georgi Gaydadjiev, Stamatis Vassiliadis, Mateo Valero	Vectorized AES Core for High-throughput Secure Environments.	VECPAR	2008	DBLP DOI BibTeX RDF	Encryption, Parallel and Distributed Computing
8	Andrea Cuoccio, Paolo Roberto Grassi, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto	A Generation Flow for Self-Reconfiguration Controllers Customization.	DELTA	2008	DBLP DOI BibTeX RDF	Reconfiguration Controller, Reconfiguration, Customization
8	Oliver A. Pfänder, Reinhard Nopper, Hans-Jörg Pfleiderer, Shun Zhou, Amine Bermak	Configurable Blocks for Multi-precision Multiplication.	DELTA	2008	DBLP DOI BibTeX RDF	reconfigurable multipliers, embedded blocks, multi-precision, FPGA, multiplication
8	Xun Zhang 0002, Hassan Rabah, Serge Weber	Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC.	DELTA	2008	DBLP DOI BibTeX RDF	adaptability, scalability, energy, partial reconfiguration, slowdown
8	Fatiha Alim-Ferhat, Hamid Bessalah, Hassen Salhi, S. Seddiki, Mohamed Issad, Oussama Kerdjidj	WT-SOM network implementation on FPGA for the medical images compression.	CSTST	2008	DBLP DOI BibTeX RDF	wavelet transform, images compression, vector quantization, Kohonen networks
8	Ricardo Chaves, Blagomir Donchev, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	BRAM-LUT Tradeoff on a Polymorphic DES Design.	HiPEAC	2008	DBLP DOI BibTeX RDF
8	Tim Güneysu, Christof Paar	Ultra High Performance ECC over NIST Primes on Commercial FPGAs.	CHES	2008	DBLP DOI BibTeX RDF	FPGA, High-Performance, Elliptic Curve Cryptosystems
8	Tam Phuong Cao, Guang Deng	Real-Time Vision-Based Stop Sign Detection System on FPGA.	DICTA	2008	DBLP DOI BibTeX RDF
8	Salvatore Vitabile, Salvatore Bono, Filippo Sorbello	An Embedded Real-Time Lane-Keeper for Automatic Vehicle Driving.	CISIS	2008	DBLP DOI BibTeX RDF
8	Kensuke Kawakami, Koji Shigemoto, Koji Nakano	Redundant Radix-2r Number System for Accelerating Arithmetic Operations on the FPGAs.	PDCAT	2008	DBLP DOI BibTeX RDF
8	Yi-Hua E. Yang, Weirong Jiang, Viktor K. Prasanna	Compact architecture for high-throughput regular expression matching on FPGA.	ANCS	2008	DBLP DOI BibTeX RDF	BRAM, FPGA, intrusion detection, finite state machine, regular expression, NFA
8	Faisal Khan, Lihua Yuan, Chen-Nee Chuah, Soheil Ghiasi	A programmable architecture for scalable and real-time network traffic measurements.	ANCS	2008	DBLP DOI BibTeX RDF
8	Issam W. Damaj	Higher-Level Hardware Synthesis of the KASUMI Algorithm.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	parallel algorithms, methodology, formal models, data encryption, gate array
8	Ray C. C. Cheung, Dong-U Lee, Wayne Luk, John D. Villasenor	Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
8	Zhongfeng Wang 0001, Zhiqiang Cui	Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
8	Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee	An Overview of a Compiler for Mapping Software Binaries to Hardware.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
8	Dong-U Lee, Ray C. C. Cheung, John D. Villasenor	A Flexible Architecture for Precise Gamma Correction.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
8	Issam W. Damaj	Parallel Algorithms Development for Programmable Devices with Application from Cryptography.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	Parallel algorithms, methodologies, formal models, data encryption, gate array
8	Francisco Rodríguez-Henríquez, Guillermo Morales-Luna, Nazar Abbas Saqib, Nareli Cruz Cortés	Parallel Itoh-Tsujii multiplicative inversion algorithm for a special class of trinomials.	Des. Codes Cryptogr.	2007	DBLP DOI BibTeX RDF	AMS Classifications 11A25, 11T99, 11T71, 05B05
8	Rodolfo Pellizzoni, Marco Caccamo	Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Reconfigurable devices, real-time resource management, online admission control, hardware and software tasks
8	Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna	High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	G.1.0.g Parallel algorithms, C.3.e Reconfigurable hardware
8	Ling Zhuo, Viktor K. Prasanna	Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on Reconfigurable Computing Systems.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	computations on matrices, field-programmable gate arrays, parallel algorithms, Scientific computing, reconfigurable hardware
8	Lerong Cheng, Fei Li 0003, Yan Lin 0001, Phoebe Wong, Lei He 0001	Device and Architecture Cooptimization for FPGA Power Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
8	Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong	Performance Benefits of Monolithically Stacked 3-D FPGA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
8	Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis	The Molen compiler for reconfigurable processors.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	FPGA, reconfigurable computing, Instruction scheduling
8	Maria Stepanova, Feng Lin 0002, Valerie C.-L. Lin	A Hopfield Neural Classifier and Its FPGA Implementation for Identification of Symmetrically Structured DNA Motifs.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	DNA motifs, sequence structure identification, hopfield classifier, field-programmable gate arrays, recurrent neural network
8	Messaoud Ahmed Ouameur, Daniel Massicotte	Real-time DSP and FPGA Implementation of Wiener LMS Based Multipath Channel Estimation in 3G CDMA Systems.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	delay acquisition, Wiener LMS, FPGA, VLSI, FFT, DSP, WCDMA, channel estimation, cdma2000
8	Kumara Ratnayake, Aishy Amer	Sequential, Irregular and Complex Object Contour Tracing on FPGA.	ICIP (5)	2007	DBLP DOI BibTeX RDF
8	Eze Kamanu, Pratapa Reddy, Kenneth Hsu, Marcin Lukowiak	A New Architecture for Single-Event Detection & Reconfiguration of SRAM-based FPGAs.	HASE	2007	DBLP DOI BibTeX RDF
8	Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch	A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing.	SAMOS	2007	DBLP DOI BibTeX RDF
8	Humberto Calderon, Carlo Galuzzi, Georgi Gaydadjiev, Stamatis Vassiliadis	High-Bandwidth Address Generation Unit.	SAMOS	2007	DBLP DOI BibTeX RDF
8	David Arditti, Côme Berbain, Olivier Billet, Henri Gilbert	Compact FPGA implementations of QUAD.	AsiaCCS	2007	DBLP DOI BibTeX RDF
8	Eric Simpson, Pengyuan Yu, Patrick Schaumont, Sumit Ahuja, Sandeep K. Shukla	VT Matrix Multiply Design for MEMOCODE '07.	MEMOCODE	2007	DBLP DOI BibTeX RDF
8	Arun Janarthanan, Vijay Swaminathan, Karen A. Tomko	MoCReS: an Area-Efficient Multi-Clock On-Chip Network for Reconfigurable Systems.	ISVLSI	2007	DBLP DOI BibTeX RDF
8	Bruno Zatt, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi	Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder.	ISVLSI	2007	DBLP DOI BibTeX RDF
8	Nan Jiang 0009, David Money Harris	Parallelized radix-2 scalable Montgomery multiplier.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
8	Ilker Hamzaoglu, Ozgur Tasdizen, Esra Sahin	An efficient H.264 intra frame coder system design.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
8	Jason Cong, Guoling Han, Wei Jiang	Synthesis of an application-specific soft multiprocessor system.	FPGA	2007	DBLP DOI BibTeX RDF	clustering, multiprocessor, pipeline, labeling, design space
8	Nicholas Weaver, Vern Paxson, José M. González	The shunt: an FPGA-based accelerator for network intrusion prevention.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, intrusion detection, hardware acceleration, NIC
8	Isabelle LaRoche, Sébastien Roy 0002	An Efficient VLSI Architecture of a Layered Space-Time Receiver.	VTC Spring	2007	DBLP DOI BibTeX RDF
8	Sung-Soo Kim, Seung-Woo Nam 0001, In-Ho Lee	Fast Ray-Triangle Intersection Computation Using Reconfigurable Hardware.	MIRAGE	2007	DBLP DOI BibTeX RDF	Intersection Testing, Ray Tracing, Collision Detection, Graphics Hardware
8	Christopher Claus, Johannes Zeppenfeld, Florian Helmut Müller, Walter Stechele	Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system.	DATE	2007	DBLP DOI BibTeX RDF
8	Timo Alho, Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen	Compact hardware design of Whirlpool hashing core.	DATE	2007	DBLP DOI BibTeX RDF
8	Esra Sahin, Ilker Hamzaoglu	Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm.	DATE	2007	DBLP DOI BibTeX RDF
8	Akash Kumar 0001, Andreas Hansson 0001, Jos Huisken, Henk Corporaal	Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip.	DATE	2007	DBLP DOI BibTeX RDF
8	Ramanathan Narayanan, Daniel Honbo, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno	Interactive presentation: An FPGA implementation of decision tree classification.	DATE	2007	DBLP DOI BibTeX RDF
8	Serkan Oktem, Ilker Hamzaoglu	An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation.	DSD	2007	DBLP DOI BibTeX RDF
8	Emanuele Sciagura, Paolo Zicari, Stefania Perri, Pasquale Corsonello	An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector.	DSD	2007	DBLP DOI BibTeX RDF
8	Martin Novotný, Jan Schmidt	General Digit-Serial Normal Basis Multiplier with Distributed Overlap.	DSD	2007	DBLP DOI BibTeX RDF
8	Ying Wang 0032, Weinan Chen, Xiao-Wei Wang, Hong-Jun You, Chenglian Peng	Enabling Reconfigurable SoC in Multimedia Processing.	CIT	2007	DBLP DOI BibTeX RDF
8	Zeghid Medien, Belgacem Bouallegue, Adel Baganne, Mohsen Machhout, Rached Tourki	A Reconfigurable Implementation of the New Secure Hash Algorithm.	ARES	2007	DBLP DOI BibTeX RDF
8	Wen-Chih Kan, Gerald E. Sobelman	High Speed Look-Ahead LMS Detector for MIMO Systems.	SiPS	2007	DBLP DOI BibTeX RDF
8	Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross	An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding.	SiPS	2007	DBLP DOI BibTeX RDF
8	Zdenek Vasícek, Lukás Sekanina	An area-efficient alternative to adaptive median filtering in FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
8	Micha Nelissen, Kees van Berkel 0001, Sergei Sawitzki	Mapping A VLIWxSIMD Processor on an FPGA: Scalability and Performance.	FPL	2007	DBLP DOI BibTeX RDF
8	Panagiotis D. Vouzis, Caroline Collange, Mark G. Arnold, Mayuresh V. Kothare	Monte Carlo Logarithmic Number System for Model Predictive Control.	FPL	2007	DBLP DOI BibTeX RDF
8	José L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler	Dynamic Voltage Scaling in a FPGA-based System-on-Chip.	FPL	2007	DBLP DOI BibTeX RDF
8	Michael Wisdom, Peter Lee 0002	An Efficient Implementation of a 2D DWT on FPGA.	FPL	2007	DBLP DOI BibTeX RDF
8	Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood	Adaptive Thermoregulation for Applications on Reconfigurable Devices.	FPL	2007	DBLP DOI BibTeX RDF
8	Vinay Sriram, David Kearney	A high throughput area time efficient pseudo uniform random number generator based on the TT800 algorithm.	FPL	2007	DBLP DOI BibTeX RDF
8	Gaye Lightbody, Roger F. Woods, Jonathan Francey	Soft IP core implementation of recursive least squares filter using only multplicative and additive operators.	FPL	2007	DBLP DOI BibTeX RDF
8	Tamer Güdü	A New Scalable Hardware Architecture for RSA Algorithm.	FPL	2007	DBLP DOI BibTeX RDF
8	Andreas Ehliar, Dake Liu	An fpga based open source network-on-chip architecture.	FPL	2007	DBLP DOI BibTeX RDF
8	Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz	RAMP Blue: A Message-Passing Manycore System in FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
8	Harding Djakou Chati, Felix Mühlbauer, Tim Braun, Christophe Bobda, Karsten Berns	SoPC architecture for a Key Point Detector.	FPL	2007	DBLP DOI BibTeX RDF
8	Pavel Zemcík, Martin Zádník	AdaBoost Engine.	FPL	2007	DBLP DOI BibTeX RDF
8	Jens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario Porrmann	A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
8	Kevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, Satish Mummareddy	A Unified Streaming Architecture for Real Time Face Detection and Gender Classification.	FPL	2007	DBLP DOI BibTeX RDF
8	Lars Braun, Michael Hübner 0001, Jürgen Becker 0001, Thomas Perschke, Volker Schatz, Stefan Bach	Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications.	FPL	2007	DBLP DOI BibTeX RDF
8	Nachiket Kapre, André DeHon	Optimistic Parallelization of Floating-Point Accumulation.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
8	Gayatri Mehta, Justin Stander, Mustafa Baz, Brady Hunsaker, Alex K. Jones	Interconnect Customization for a Coarse-grained Reconfigurable Fabric.	IPDPS	2007	DBLP DOI BibTeX RDF
8	Jixiang Zhu, Yuanxiang Li 0001, Guoliang He, Xuewen Xia	An Intrinsic Evolvable Hardware Based on Multiplexer Module Array.	ICES	2007	DBLP DOI BibTeX RDF	intrinsic, FPGA, digital, multiplexer
8	Jin Wang, Chang Hao Piao, Chong Ho Lee	Implementing Multi-VRC Cores to Evolve Combinational Logic Circuits in Parallel.	ICES	2007	DBLP DOI BibTeX RDF	Intrinsic evolvable hardware, scalability, parallel evolutionary algorithm, incremental evolution
8	Glenn Leary, Krishna Mehta, Karam S. Chatha	Performance and resource optimization of NoC router architecture for master and slave IP cores.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	FPGA, network-on-chip
8	Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung	A Hybrid Memory Sub-system for Video Coding Applications.	FCCM	2007	DBLP DOI BibTeX RDF
8	I. Faik Baskaya, Brian Gestner, Christopher M. Twigg, Sung Kyu Lim, David V. Anderson, Paul E. Hasler	Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array.	FCCM	2007	DBLP DOI BibTeX RDF
8	Paolo D'Alberto, Peter A. Milder, Aliaksei Sandryhaila, Franz Franchetti, James C. Hoe, José M. F. Moura, Markus Püschel, Jeremy R. Johnson	Generating FPGA-Accelerated DFT Libraries.	FCCM	2007	DBLP DOI BibTeX RDF
8	Harding Djakou Chati, Felix Mühlbauer, Tim Braun, Christophe Bobda, Karsten Berns	Hardware/Software co-design of a key point detector on FPGA.	FCCM	2007	DBLP DOI BibTeX RDF
8	David B. Thomas, Wayne Luk, Michael Stumpf	Reconfigurable Hardware Acceleration of Canonical Graph Labelling.	ARC	2007	DBLP DOI BibTeX RDF
8	Mazen A. R. Saghir, Rawan Naous	A Configurable Multi-ported Register File Architecture for Soft Processor Cores.	ARC	2007	DBLP DOI BibTeX RDF
8	Jae Young Hur, Todor P. Stefanov, Stephan Wong, Stamatis Vassiliadis	Systematic Customization of On-Chip Crossbar Interconnects.	ARC	2007	DBLP DOI BibTeX RDF
8	Francisco Rodríguez-Henríquez, Guillermo Morales-Luna, Nazar Abbas Saqib, Nareli Cruz Cortés	A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm.	ARC	2007	DBLP DOI BibTeX RDF
8	Jin Wang, Chang Hao Piao, Chong Ho Lee	FPGA Implementation of Evolvable Characters Recognizer with Self-adaptive Mutation Rates.	ICANNGA (1)	2007	DBLP DOI BibTeX RDF
8	Ming Z. Zhang, Vijayan K. Asari	A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	2D convolution, log-domain computation, multiplier-less architecture, quadrant symmetric kernels, modularized optimization, FPGA based architecture
8	Salvatore Vitabile, Salvatore Bono, Filippo Sorbello	An Embedded Real-Time Automatic Lane-Keeping System.	KES (1)	2007	DBLP DOI BibTeX RDF
8	Jason Schlessman, Mark Lodato, I. Burak Özer, Wayne H. Wolf	Heterogeneous MPSoC Architectures for Embedded Computer Vision.	ICME	2007	DBLP DOI BibTeX RDF
8	Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle	A Lightweight Framework for Runtime Reconfigurable System Prototyping.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
8	Vagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger Endrigo Carvalho Porto, Luciano Volcan Agostini, Sergio Bampi, Altamiro Amadeu Susin	FPGA Prototyping Strategy for a H.264/AVC Video Decoder.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
8	Masayuki Hiromoto, Kentaro Nakahara, Hiroki Sugano, Yukihiro Nakamura, Ryusuke Miyamoto	A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features.	CVPR	2007	DBLP DOI BibTeX RDF
8	Thinh Ngoc Tran, Surin Kittitornkun	FPGA-Based Cuckoo Hashing for Pattern Matching in NIDS/NIPS.	APNOMS	2007	DBLP DOI BibTeX RDF	NIPS, FPGA, Pattern Matching, NIDS, Cuckoo Hashing
8	Hou-Jen Ko, Chun-Jen Tsai	A Double-Issue Java Processor Design for Embedded Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
8	Zhuo Xu, Junyan Ren, Xuejing Wang, Fan Ye 0001	Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication System.	ISCAS	2007	DBLP DOI BibTeX RDF
8	Wen-Chih Kan, Gerald E. Sobelman	MIMO Transceiver Design Based on a Modified Geometric Mean Decomposition.	ISCAS	2007	DBLP DOI BibTeX RDF
8	Shrutisagar Chandrasekaran, Abbes Amira	Novel Sparse OBC based Distributed Arithmetic Architecture for Matrix Transforms.	ISCAS	2007	DBLP DOI BibTeX RDF
8	Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel	Towards Gb/s turbo decoding of product code onto an FPGA device.	ISCAS	2007	DBLP DOI BibTeX RDF
8	Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi	MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV.	ISCAS	2007	DBLP DOI BibTeX RDF
8	Yaling Ma, Mingjie Lin	Collaborative Routing Architecture for FPGA.	ISCAS	2007	DBLP DOI BibTeX RDF
8	Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi	An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding.	IOLTS	2007	DBLP DOI BibTeX RDF
8	Mustafa Parlak, Ilker Hamzaoglu	A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm.	AHS	2007	DBLP DOI BibTeX RDF
8	Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala	A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications.	AHS	2007	DBLP DOI BibTeX RDF