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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 786 occurrences of 438 keywords
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Results
Found 2158 publication records. Showing 2157 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Hussain Al-Asaad, John P. Hayes, Brian T. Murray |
Scalable Test Generators for High-Speed Datapath Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 111-125, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
datapath circuits, scalability, built-in self-test, test generation, on-line testing, carry lookahead |
16 | Yuke Wang, Xiaoyu Song, El Mostapha Aboulhamid |
Residue to Binary Number Converters for (2n-1, 2n, 2n+1). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 174-178, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
algorithm, adders, residue number system, circuit, arithmetic |
16 | Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. Ayoubi |
Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 168-, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
non-refreshing static storage, on-chip learning neural networks, analog learning |
16 | Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas |
C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 155-163, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
robustly delay fault testable circuits, path delay faults, C-testability, Iterative-logic-arrays |
16 | David W. Matula, Asger Munk Nielsen |
Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 140-147, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
pipelined packet forwarding floating point, packet forwarding floating point format, rounder design, packet forwarding format, standard binary IEEE 754 floating point format, multiplication algorithms, ALU pipeline paradigm, data hazards, pipelined floating point operations, execution phases, multiplier packet forwarding pipelines, execution phase, logic levels, multiplier pipelines, forwarding pipelines, IEEE 754 binary floating point compatibility, pipeline arithmetic, data dependent operations |
16 | Yamin Li, Wanming Chu |
Implementation of single precision floating point square root on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 226-233, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho |
Delay-Insensitive Carry-Lookahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 322-328, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Uming Ko, T. Balsara, Wai Lee |
Low-power design techniques for high-performance CMOS adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(2), pp. 327-333, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Bernd Becker 0001, Rolf Drechsler, Paul Molitor |
On the generation of area-time optimal testable adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9), pp. 1049-1066, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Feng Zhou, Peter Kornerup |
High Speed DCT/IDCT Using a Pipelined CORDIC Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 180-187, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Jalil Fadavi-Ardekani |
M×N Booth encoded multiplier generator using optimized Wallace trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(2), pp. 120-125, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Paolo Montuschi, Luigi Ciminiera |
n × n carry-save multipliers without final addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings., pp. 54-61, 1993, IEEE Computer Society/, 0-8186-3862-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Kurt Keutzer, Sharad Malik, Alexander Saldanha |
Is redundancy necessary to reduce delay? ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4), pp. 427-435, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Kurt Keutzer, Sharad Malik, Alexander Saldanha |
Is Redundancy Necessary to Reduce Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 228-234, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | Paruvachi V. R. Raja |
Novel Design Techniques for RNS Systolic VLSI Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Computer Science Conference ![In: Computing in the 90's, The First Great Lakes Computer Science Conference, Kalamazzo, Michigan, USA, October 18-20, 1989, Proceedings, pp. 206-212, 1989, Springer, 3-540-97628-0. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
16 | Mahmoud A. Manzoul, Jia-Yuan Han |
Realization of a multi-valued inner product step processor using CCD's (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Conference on Computer Science ![In: Proceedings of the 15th ACM Annual Conference on Computer Science, St. Louis, Missouri, USA, February 16-19, 1987, pp. 433, 1987, ACM, 0-89791-218-7. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
15 | Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin 0001 |
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 59(5), pp. 694-706, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Adder/subtractor, redundant format, computer arithmetic, floating point, rounding, signed-digit number system |
15 | Qingzheng Li, Guixuan Liang, Amine Bermak |
A High-speed 32-bit Signed/Unsigned Pipelined Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 207-211, 2010, IEEE Computer Society, 978-0-7695-3978-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
signed/unsigned multiplier, fast adder, Booth Encoding, Wallace Tree |
15 | Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu, Arun Bhanu |
Modeling of Probabilistic Ripple-Carry Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 201-206, 2010, IEEE Computer Society, 978-0-7695-3978-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
ripple-carry adder, noies modeling, error propagation, Probabilistic computation |
15 | Saroja V. Siddamal, R. M. Banakar, B. C. Jinaga |
Design of High-Speed Floating Point Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 285-289, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FP operations, Fast Carry look ahead adder (MCLA), CSD algorithm, Booth algorithm |
15 | Christophe Philemotte, Hugues Bersini |
Intrinsic emergence boosts adaptive capacity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2005, Proceedings, Washington DC, USA, June 25-29, 2005, pp. 559-560, 2005, ACM, 1-59593-010-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
intrinsic emergence, genetic algorithm, heuristics, cellular automata, speedup technique, binary adder |
15 | Daniel J. Deleganes, Micah Barany, George L. Geannopoulos, Kurt Kreitzer, Anant P. Singh, Sapumal B. Wijeratne |
Low voltage swing logic circuits for a Pentium 4 processor integer core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 678-680, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
LVS, Pentium® 4 processor, integer core, low voltage swing, sense-amp, microprocessor, rotator, adder |
15 | Jiun-In Guo, Jui-Cheng Yen |
An Efficient IDCT Processor Design for HDTV Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(1-2), pp. 147-155, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
inverse discrete cosine transform (IDCT), adder-based implementation, common sub-expression sharing, HDTV, cyclic convolution |
15 | Katarzyna Leijten-Nowak, Jef L. van Meerbergen |
An FPGA architecture with enhanced datapath functionality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 195-204, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
adder inverting property, application-domain tuning, logic block architectures, FPGAs, DSP, symmetry |
15 | John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan Zhou, John F. McDonald 0001, Russell P. Kraft |
3D direct vertical interconnect microprocessors test vehicle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 141-146, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
SiGe HBT, direct vertical integration, finite state machine, interconnect, microprocessor, adder, register file, 3D integration, current mode logic |
15 | Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama |
Fully Source-Coupled Logic Based Multiple-Valued VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, pp. 270-275, 2002, IEEE Computer Society, 0-7695-1462-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
source-coupled logic, differential-pair circuit, current-source control, radix-2 signed-digit adder, multiple-valued logic, current-mode logic |
15 | Tomás Lang, Javier D. Bruguera |
Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 73-79, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Most significant carry, prefix tree, carry look-ahead adder |
15 | James C. Ellenbogen |
Advances Toward Molecular-Scale Electronic Digital Logic Circuits: A Review and Prospectus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 392-, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
nanocomputer architectures, molecular circuit designs, molecular adder, nanoelectronics, molecular electronics |
15 | Albrecht P. Stroele |
BIST Pattern Generators Using Addition and Subtraction Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(1), pp. 69-80, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
built-in self-test, adder, accumulator, pattern generator, subtracter |
15 | Paul F. Stelling, Vojin G. Oklobdzija |
Implementing Multiply-Accumulate Operation in Multiplication Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 99-, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
multiply-accumulate operation, multiplication time, optimal delays, instruction time, optimal multiply-accumulate circuit, RISC CPU, partial product reduction tree, final adder, digital signal processing, power savings, multiplying circuits, circuit design, VLSI circuits, parallel multiplier, processor performance, video applications, graphics applications, clock speed |
15 | Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang |
Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 492-499, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams |
15 | Zhan Chen, Israel Koren |
Techniques for Yield Enhancement of VLSI Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 222-229, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
VLSI yield, VLSI adder, defect tolerance, VLSI layout |
15 | K. Vijayan Asari, C. Eswaran |
An Optimization Technique for the Design of Multiple Valued PLA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(1), pp. 118-122, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
multiple valued PLA design, output encoding, binary output, multiple function literal circuits, PLA size, encoding, minimization, programmable logic arrays, adders, adder, many-valued logics, minimisation, multiple valued logic, logic arrays, optimization technique, network synthesis |
15 | Michael J. Schulte, Earl E. Swartzlander Jr. |
Hardware Designs for Exactly Rounded Elemantary Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(8), pp. 964-973, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
Chebyshev approximation, summing circuits, exactly rounded elementary functions, multi-operand adder, Chebyshev series approximation, single-precision floating point numbers, chip area, 1.0-micron CMOS technology, computational delay, exact rounding, argument reduction, computer arithmetic, digital arithmetic, polynomials, CMOS integrated circuits, multiplying circuits, square-root, hardware designs, reciprocal, approximation theory, polynomial approximation, special-purpose hardware, parallel multiplier, 1 micron |
15 | Shambhu J. Upadhyaya, Hoang Pham |
Analysis of Noncoherent Systems and an Architecture for the Computation of the System Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(4), pp. 484-493, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
noncoherent systems, k-to-l-out-of-n systems, transportation system environments, coherent systems, cellular implementation, optimal configurations, communication, VLSI, fault tolerant computing, computer-aided-design, multiprocessor, computer architecture, adder, multiplier, system reliability, N-modular-redundancy |
15 | Eric M. Schwarz, Michael J. Flynn |
Parallel High-Radix Nonrestoring Division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(10), pp. 1234-1246, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
parallel high-radix nonrestoring division, quotient estimation, generalized partial remainder, carry propagate adder, high-radix division, logic design, logic design, latency, computer arithmetic, digital arithmetic, combinatorial algorithm, SRT division |
15 | Nhon T. Quach, Michael J. Flynn |
High-Speed Addition in CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(12), pp. 1612-1615, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
high speed addition, static complementary metal-oxide semiconductor, Ling-type 32-bit adder, serial transistors, worst-case critical path, carry look-ahead, CMOS, adders, CMOS integrated circuits, gate delay, 32 bit |
15 | Milos D. Ercegovac, Tomás Lang |
Fast Multiplication Without Carry-Propagate Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(11), pp. 1385-1390, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
fast multiplication, carry-propagate adder, LRCF scheme, general radix r, radix-4 signed-digit implementation, digital arithmetic |
15 | Israel Koren, Ofra Zinaty |
Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(8), pp. 1030-1037, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
high-precision floating-point numbers, extended double precision format, IEEE standard P754, floating-point numeric coprocessor, fast adder, digital arithmetic, execution time, microprocessor chips, approximation theory, elementary functions, function evaluation, rational approximations, silicon area, fast multiplier |
15 | Binay Sugla, David A. Carlson |
Extreme Area-Time Tradeoffs in VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(2), pp. 251-257, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
bounded fan-in, fan-out prefix computation graphs, area requirements, constant factor reduction, area-time tradeoff, VLSI, lower bounds, digital arithmetic, layout, circuit layout CAD, carry look-ahead adder |
15 | Shinji Nakamura, Kai-Yu Chu |
A Single Chip Parallel Multiplier by MOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(3), pp. 274-282, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
single chip parallel multiplier, MOS technology, five-counter cell, logic design level, full adder cell design, logic design, integrated logic circuits, multiplying circuits, design optimization, field effect integrated circuits |
15 | Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima |
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 34(9), pp. 789-796, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
binary integer multiplication, carry-propagation-free adder, high-speed multiplier, redundant binary representation, VLSI, Arithmetic operations, hardware algorithm, signed-digit number representation |
15 | Tsutomu Sasao |
Input Variable Assignment and Output Phase Optimization of PLA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(10), pp. 879-894, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
complexity of logic circuits, decoder assignment, essential prime implicants, output phase optimization, logic design, programmable logic array, Adder, switching theory |
15 | Hung Chi Lai, Saburo Muroga |
Logic Networks of Carry-Save Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(9), pp. 870-882, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders |
15 | S. A. Kent |
A High-Speed Threshold Gate Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 26(12), pp. 1279-1283, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
High-speed adder, threshold logic, propagation delay, partial product, parallel multiplication |
15 | J. A. Bate, Jon C. Muzio |
Three Cell Structures for Ternary Cellular Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 26(12), pp. 1191-1202, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
combinational switching functions, ternary full adder, universal arrays, Cellular arrays, symmetric functions, ternary logic |
15 | Francisco J. O. Dias |
Truth-Table Verification of an Iterative Logic Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 25(6), pp. 605-613, 1976. The full citation details ...](Pics/full.jpeg) |
1976 |
DBLP DOI BibTeX RDF |
test, fault detection, Adder, multiple fault, cell, checking experiment, truth table, iterative array |
15 | John A. Gibson, R. W. Gibbard |
Synthesis and Comparison of Two's Complement Parallel Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(10), pp. 1020-1027, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
Algorithm syntheses, full adder arrays, multiplier comparisons, parallel binary multiplication, two's complement formulation |
13 | R. Nishanth, C. Helen Sulochana |
A novel lightweight CNN-based error-reduced carry prediction approximate full adder design for multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 36(12), pp. 6421-6440, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Hemanshi Chugh, Sonal Singh |
Efficient co-planar adder designs in quantum dot cellular automata: Energy and cost optimization with crossover elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 94, pp. 102103, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Sriram Sundar S, Mahendran G |
CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 95, pp. 102132, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Melika Amiri, Massoud Dousti, Majid Mohammadi |
Design and implementation of carry-save adder using quantum-dot cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 80(2), pp. 1554-1567, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Fang Wang, Jie Bai, Linlin Liu, Tianyuan Ye |
Temporal noisy-adder of bayesian network for scalable consecutive-k-out-of-n:F system reliability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Reliab. Eng. Syst. Saf. ![In: Reliab. Eng. Syst. Saf. 242, pp. 109733, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Chaojie He, Zi Wang, Feibin Xiang, Zhuoyu Dai, Yifan He, Jinshan Yue, Yongpan Liu |
LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 71(2), pp. 852-856, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
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13 | Samane Asgari, Mohammad Reza Reshadinezhad, Seyed Erfan Fatemieh |
Energy-efficient and fast IMPLY-based approximate full adder applying NAND gates for image processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 113, pp. 109053, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
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13 | Ahmad Karimi, Keivan Navi |
The design of adder, subtractor, and derivative circuits without the use of op-amp in CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 113, pp. 109047, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
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13 | S. Lakshmanachari, Sadulla Shaik, G. S. R. Satyanarayana, Inapudi Vasavi, Vallabhuni Vijay, Chandra Shaker Pittala |
1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Syst. Assur. Eng. Manag. ![In: Int. J. Syst. Assur. Eng. Manag. 15(3), pp. 950-956, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
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13 | Manish Srivastava, Alessandro Ferro, Aleksandr Sidun, José M. de la Rosa 0001, Kilian O'Donoghue, Pádraig Cantillon-Murphy, Daniel O'Hare |
A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Open J. Circuits Syst. ![In: IEEE Open J. Circuits Syst. 5, pp. 42-54, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
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13 | Gerardo Bandera, Javier Salamero, Miquel Moretó, Julio Villalba |
Floating Point HUB Adder for RISC-V Sargantana Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.09464, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
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13 | Kihwan Kim, Hyuk-Jae Lee, Xuan Truong Nguyen |
Reconfigurable One-Adder Multiplication for CNN Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEIC ![In: International Conference on Electronics, Information, and Communication, ICEIC 2024, Taipei, Taiwan, January 28-31, 2024, pp. 1-3, 2024, IEEE, 979-8-3503-7188-8. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Ho-Sung Lee, Joo-Hyung Chae |
A 1-Kb 6T 1C XNOR-DRAM Compute-In-Memory Macro With Signed Bit Adder Block for CNN Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEIC ![In: International Conference on Electronics, Information, and Communication, ICEIC 2024, Taipei, Taiwan, January 28-31, 2024, pp. 1-4, 2024, IEEE, 979-8-3503-7188-8. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si |
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 570-572, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Yathin Kumar Attuluri, Ruchit Chudasama, Kailash Prasad, Joycee Mekie |
FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, VLSID 2024, Kolkata, India, January 6-10, 2024, pp. 247-252, 2024, IEEE, 979-8-3503-8440-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | S. Senthilkumar, V. Samuthira Pandi, T. Sripriya, N. Pragadish |
Design of recustomize finite impulse response filter using truncation based scalable rounding approximate multiplier and error reduced carry prediction approximate adder for image processing application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 35(8), 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Perumal Mahendran, M. S. Kavitha, R. Radhika, C. Kotteeswaran |
Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 35(6), pp. 1, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
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13 | Ayoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri |
High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 15(1), pp. 33-36, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
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13 | Qi-Yue Yu, Ke-Xun Song |
Uniquely Decodable Multi-Amplitude Sequence for Grant-Free Multiple-Access Adder Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 22(12), pp. 8999-9012, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
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13 | D. Rebecca Florance, B. Prabhakar |
Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 88, pp. 32-42, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Afshin Khaksari, Omid Akbari, Behzad Ebrahimi |
BEAD: Bounded error approximate adder with carry and sum speculations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 88, pp. 353-361, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Jeyakumar Ponraj, R. Jeyabharath, P. Veena, Tharumar Srihari |
High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 93, pp. 102055, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Jie Xu 0019, Gensheng Hu, Dingjun Qian |
A quantum-based building block for designing a nanoscale full adder circuit with power analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 92, pp. 77-82, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Sueyeon Kim, Insoo Choi, Sangki Cho, Myounggon Kang, Seungjae Baik, Changho Ra, Jongwook Jeon |
Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 97778-97785, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Abdelsalam Al Share, Fadi Nessir Zghoul, Osama Daifallah Al-Khaleel, Mohammad Al-Khaleel, Christos A. Papachristou |
Design of High Speed BCD Adder Using CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 141628-141639, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Vineet Jaiswal, Trailokya Nath Sasamal |
Novel approach for the design of efficient full adder in MQCA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 79(7), pp. 7900-7915, May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
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13 | Hyoju Seo, Yongtae Kim |
A Low Latency Approximate Adder Design Based on Dual Sub-Adders With Error Recovery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 11(3), pp. 811-816, July - September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
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13 | Umberto Garlando, Qi Wang, Oleksandr V. Dobrovolskiy, Andrii V. Chumak, Fabrizio Riente |
Numerical Model for 32-Bit Magnonic Ripple Carry Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 11(3), pp. 679-688, July - September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
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13 | Farshid Ahmadi, Mohammad R. Semati, Hassan Daryanavard |
A Low-Power Improved-Accuracy Approximate Error-Report-Propagate Adder for DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 42(6), pp. 3744-3769, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Vasundhara Trivedi, Khushbu Lalwani, Gopal Raut, Avikshit Khomane, Neha Ashar, Santosh Kumar Vishvakarma |
Hybrid ADDer: A Viable Solution for Efficient Design of MAC in DNNs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 42(12), pp. 7596-7614, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
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13 | Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee |
A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 42(4), pp. 2283-2304, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
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13 | T. Nirmalraj, S. K. Pandiyan, Rakesh Kumar Karan, R. Sivaraman 0001, Rengarajan Amirtharajan |
Design of Low-Power 10-Transistor Full Adder Using GDI Technique for Energy-Efficient Arithmetic Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 42(6), pp. 3649-3667, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | K. Saritha Raj, P. Rajesh Kumar, M. Satyanarayana |
Capricious Digital Filter Design and Implementation Using Baugh-Wooley Multiplier and Error Reduced Carry Prediction Approximate Adder for ECG Noise Removal Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 42(11), pp. 6726-6748, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Ning Zhang, Guoqing Wang, Jue Wang 0011, He Chen, Wenchao Liu 0001, Liang Chen 0004 |
All Adder Neural Networks for On-Board Remote Sensing Scene Classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Geosci. Remote. Sens. ![In: IEEE Trans. Geosci. Remote. Sens. 61, pp. 1-16, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Hamid Tavakolaee, Gholamreza Ardeshir, Yasser Baleghi 0001 |
Design and analysis of a novel fast adder using logical effort method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 17(3-4), pp. 195-208, May-July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Yonatan Pugachov, Moria Gulitski, Omri Mizrahi, Dror Malka |
Design of All-Optical Logic Half-Adder Based on Photonic Crystal Multi-Ring Resonator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Symmetry ![In: Symmetry 15(5), pp. 1063, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Yiming Chen, Guodong Yin, Mufeng Zhou, Wenjun Tang, Zekun Yang, Mingyen Lee, Xirui Du, Jinshan Yue, Jiaxin Liu, Huazhong Yang, Yongpan Liu, Xueqing Li |
SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(7), pp. 2762-2773, July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Charalampos Eleftheriadis, Georgios Karakonstantis |
Optimal Adder-Multiplexer Co-Optimization for Time-Multiplexed Multiplierless Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(9), pp. 3598-3611, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Yifan He, Jinshan Yue, Xiaoyu Feng, Yuxuan Huang, Hongyang Jia, Jingyu Wang, Lu Zhang, Wenyu Sun, Huazhong Yang, Yongpan Liu |
An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(2), pp. 416-420, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Ghassem Jaberipur, Dariush Badri, Jeong-A Lee |
A Parallel Prefix Modulo-(2q + 2q-1 + 1) Adder via Diminished-1 Representation of Residues. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(8), pp. 3104-3108, August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Ximing Li 0003, Xing Jin, Weichong Chen, Ningyuan Yin, Zhiyi Yu |
Parallel-Prefix Adder in Spin-Orbit Torque Magnetic RAM for High Bit-Width Non-Volatile Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(2), pp. 761-765, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Jongho Yoon, Seunghan Baek, Sunmean Kim, Seokhyeong Kang |
Optimizing Ternary Multiplier Design With Fast Ternary Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(2), pp. 766-770, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Aibin Yan, Runqi Liu, Jie Cui 0004, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen, Jiliang Zhang 0002 |
Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(6), pp. 2256-2260, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Mina Raouf, Somayeh Timarchi |
Non-Volatile and High-Performance Cascadable Spintronic Full-Adder With No Sensitivity to Input Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(6), pp. 2236-2240, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Gerson D. Andrade, Matheus Silva, Cínthia Schneider, Guilherme Paim, Sergio Bampi, Eduardo Costa 0001, Alexandra L. Zimpeck |
Robustness Analysis of 3-2 Adder Compressor Designed in 7-nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(3), pp. 1264-1268, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Xing Jin, Weichong Chen, Ximing Li 0003, Ningyuan Yin, Caihua Wan, Mingkun Zhao, Xiufeng Han, Zhiyi Yu |
High-Reliability, Reconfigurable, and Fully Non-volatile Full-Adder Based on SOT-MTJ for Image Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(2), pp. 781-785, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Forouzan Bahrami, Nabiollah Shiri, Farshad Pesaran |
Imprecise Subtractor Using a New Efficient Approximate-Based Gate Diffusion Input Full Adder for Bioimages Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 108, pp. 108729, May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | B. Jeevan, K. Bikshalu, E. Hari Krishna, Kosaraju Sivani |
Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 99, pp. 104846, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Senthil Pitchai, Saravanan Pitchai |
Area-latency efficient floating point adder using interleaved alignment and normalization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 99, pp. 104842, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | A. Venkatesan, P. T. Vanathi, M. Elangovan |
Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7 nm FINFET Technology for MIMO Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 32(8), pp. 2350134:1-2350134:19, May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | A. Venkatesan, P. T. Vanathi, M. Elangovan |
Erratum: Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7nm FINFET Technology for MIMO Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 32(13), pp. 2392003:1, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | A. Niyas Ahamed, M. Madheswaran |
Hybrid Brent Kung Adder with Modified Sum Generator for Energy Efficient Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 32(12), pp. 2350212:1-2350212:14, August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
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