Search results for "adder"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Hussain Al-Asaad, John P. Hayes, Brian T. Murray	Scalable Test Generators for High-Speed Datapath Circuits.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	datapath circuits, scalability, built-in self-test, test generation, on-line testing, carry lookahead
16	Yuke Wang, Xiaoyu Song, El Mostapha Aboulhamid	Residue to Binary Number Converters for (2n-1, 2n, 2n+1).	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	algorithm, adders, residue number system, circuit, arithmetic
16	Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. Ayoubi	Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	non-refreshing static storage, on-chip learning neural networks, analog learning
16	Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas	C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications.	DFT	1998	DBLP DOI BibTeX RDF	robustly delay fault testable circuits, path delay faults, C-testability, Iterative-logic-arrays
16	David W. Matula, Asger Munk Nielsen	Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, packet forwarding floating point format, rounder design, packet forwarding format, standard binary IEEE 754 floating point format, multiplication algorithms, ALU pipeline paradigm, data hazards, pipelined floating point operations, execution phases, multiplier packet forwarding pipelines, execution phase, logic levels, multiplier pipelines, forwarding pipelines, IEEE 754 binary floating point compatibility, pipeline arithmetic, data dependent operations
16	Yamin Li, Wanming Chu	Implementation of single precision floating point square root on FPGAs.	FCCM	1997	DBLP DOI BibTeX RDF
16	Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho	Delay-Insensitive Carry-Lookahead Adders.	VLSI Design	1997	DBLP DOI BibTeX RDF
16	Uming Ko, T. Balsara, Wai Lee	Low-power design techniques for high-performance CMOS adders.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
16	Bernd Becker 0001, Rolf Drechsler, Paul Molitor	On the generation of area-time optimal testable adders.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
16	Feng Zhou, Peter Kornerup	High Speed DCT/IDCT Using a Pipelined CORDIC Algorithm.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF
16	Jalil Fadavi-Ardekani	M×N Booth encoded multiplier generator using optimized Wallace trees.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
16	Paolo Montuschi, Luigi Ciminiera	n × n carry-save multipliers without final addition.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
16	Kurt Keutzer, Sharad Malik, Alexander Saldanha	Is redundancy necessary to reduce delay?	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
16	Kurt Keutzer, Sharad Malik, Alexander Saldanha	Is Redundancy Necessary to Reduce Delay.	DAC	1990	DBLP DOI BibTeX RDF
16	Paruvachi V. R. Raja	Novel Design Techniques for RNS Systolic VLSI Arrays.	Great Lakes Computer Science Conference	1989	DBLP DOI BibTeX RDF
16	Mahmoud A. Manzoul, Jia-Yuan Han	Realization of a multi-valued inner product step processor using CCD's (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
15	Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin 0001	Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Adder/subtractor, redundant format, computer arithmetic, floating point, rounding, signed-digit number system
15	Qingzheng Li, Guixuan Liang, Amine Bermak	A High-speed 32-bit Signed/Unsigned Pipelined Multiplier.	DELTA	2010	DBLP DOI BibTeX RDF	signed/unsigned multiplier, fast adder, Booth Encoding, Wallace Tree
15	Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu, Arun Bhanu	Modeling of Probabilistic Ripple-Carry Adders.	DELTA	2010	DBLP DOI BibTeX RDF	ripple-carry adder, noies modeling, error propagation, Probabilistic computation
15	Saroja V. Siddamal, R. M. Banakar, B. C. Jinaga	Design of High-Speed Floating Point Multiplier.	DELTA	2008	DBLP DOI BibTeX RDF	FP operations, Fast Carry look ahead adder (MCLA), CSD algorithm, Booth algorithm
15	Christophe Philemotte, Hugues Bersini	Intrinsic emergence boosts adaptive capacity.	GECCO	2005	DBLP DOI BibTeX RDF	intrinsic emergence, genetic algorithm, heuristics, cellular automata, speedup technique, binary adder
15	Daniel J. Deleganes, Micah Barany, George L. Geannopoulos, Kurt Kreitzer, Anant P. Singh, Sapumal B. Wijeratne	Low voltage swing logic circuits for a Pentium 4 processor integer core.	DAC	2004	DBLP DOI BibTeX RDF	LVS, Pentium® 4 processor, integer core, low voltage swing, sense-amp, microprocessor, rotator, adder
15	Jiun-In Guo, Jui-Cheng Yen	An Efficient IDCT Processor Design for HDTV Applications.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	inverse discrete cosine transform (IDCT), adder-based implementation, common sub-expression sharing, HDTV, cyclic convolution
15	Katarzyna Leijten-Nowak, Jef L. van Meerbergen	An FPGA architecture with enhanced datapath functionality.	FPGA	2003	DBLP DOI BibTeX RDF	adder inverting property, application-domain tuning, logic block architectures, FPGAs, DSP, symmetry
15	John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan Zhou, John F. McDonald 0001, Russell P. Kraft	3D direct vertical interconnect microprocessors test vehicle.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	SiGe HBT, direct vertical integration, finite state machine, interconnect, microprocessor, adder, register file, 3D integration, current mode logic
15	Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama	Fully Source-Coupled Logic Based Multiple-Valued VLSI.	ISMVL	2002	DBLP DOI BibTeX RDF	source-coupled logic, differential-pair circuit, current-source control, radix-2 signed-digit adder, multiple-valued logic, current-mode logic
15	Tomás Lang, Javier D. Bruguera	Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition.	ICCD	1999	DBLP DOI BibTeX RDF	Most significant carry, prefix tree, carry look-ahead adder
15	James C. Ellenbogen	Advances Toward Molecular-Scale Electronic Digital Logic Circuits: A Review and Prospectus.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	nanocomputer architectures, molecular circuit designs, molecular adder, nanoelectronics, molecular electronics
15	Albrecht P. Stroele	BIST Pattern Generators Using Addition and Subtraction Operations.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	built-in self-test, adder, accumulator, pattern generator, subtracter
15	Paul F. Stelling, Vojin G. Oklobdzija	Implementing Multiply-Accumulate Operation in Multiplication Time.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	multiply-accumulate operation, multiplication time, optimal delays, instruction time, optimal multiply-accumulate circuit, RISC CPU, partial product reduction tree, final adder, digital signal processing, power savings, multiplying circuits, circuit design, VLSI circuits, parallel multiplier, processor performance, video applications, graphics applications, clock speed
15	Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang	Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers.	ICCD	1996	DBLP DOI BibTeX RDF	pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams
15	Zhan Chen, Israel Koren	Techniques for Yield Enhancement of VLSI Adders.	ASAP	1995	DBLP DOI BibTeX RDF	VLSI yield, VLSI adder, defect tolerance, VLSI layout
15	K. Vijayan Asari, C. Eswaran	An Optimization Technique for the Design of Multiple Valued PLA's.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	multiple valued PLA design, output encoding, binary output, multiple function literal circuits, PLA size, encoding, minimization, programmable logic arrays, adders, adder, many-valued logics, minimisation, multiple valued logic, logic arrays, optimization technique, network synthesis
15	Michael J. Schulte, Earl E. Swartzlander Jr.	Hardware Designs for Exactly Rounded Elemantary Functions.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	Chebyshev approximation, summing circuits, exactly rounded elementary functions, multi-operand adder, Chebyshev series approximation, single-precision floating point numbers, chip area, 1.0-micron CMOS technology, computational delay, exact rounding, argument reduction, computer arithmetic, digital arithmetic, polynomials, CMOS integrated circuits, multiplying circuits, square-root, hardware designs, reciprocal, approximation theory, polynomial approximation, special-purpose hardware, parallel multiplier, 1 micron
15	Shambhu J. Upadhyaya, Hoang Pham	Analysis of Noncoherent Systems and an Architecture for the Computation of the System Reliability.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	noncoherent systems, k-to-l-out-of-n systems, transportation system environments, coherent systems, cellular implementation, optimal configurations, communication, VLSI, fault tolerant computing, computer-aided-design, multiprocessor, computer architecture, adder, multiplier, system reliability, N-modular-redundancy
15	Eric M. Schwarz, Michael J. Flynn	Parallel High-Radix Nonrestoring Division.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	parallel high-radix nonrestoring division, quotient estimation, generalized partial remainder, carry propagate adder, high-radix division, logic design, logic design, latency, computer arithmetic, digital arithmetic, combinatorial algorithm, SRT division
15	Nhon T. Quach, Michael J. Flynn	High-Speed Addition in CMOS.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	high speed addition, static complementary metal-oxide semiconductor, Ling-type 32-bit adder, serial transistors, worst-case critical path, carry look-ahead, CMOS, adders, CMOS integrated circuits, gate delay, 32 bit
15	Milos D. Ercegovac, Tomás Lang	Fast Multiplication Without Carry-Propagate Addition.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	fast multiplication, carry-propagate adder, LRCF scheme, general radix r, radix-4 signed-digit implementation, digital arithmetic
15	Israel Koren, Ofra Zinaty	Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	high-precision floating-point numbers, extended double precision format, IEEE standard P754, floating-point numeric coprocessor, fast adder, digital arithmetic, execution time, microprocessor chips, approximation theory, elementary functions, function evaluation, rational approximations, silicon area, fast multiplier
15	Binay Sugla, David A. Carlson	Extreme Area-Time Tradeoffs in VLSI.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	bounded fan-in, fan-out prefix computation graphs, area requirements, constant factor reduction, area-time tradeoff, VLSI, lower bounds, digital arithmetic, layout, circuit layout CAD, carry look-ahead adder
15	Shinji Nakamura, Kai-Yu Chu	A Single Chip Parallel Multiplier by MOS Technology.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	single chip parallel multiplier, MOS technology, five-counter cell, logic design level, full adder cell design, logic design, integrated logic circuits, multiplying circuits, design optimization, field effect integrated circuits
15	Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima	High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	binary integer multiplication, carry-propagation-free adder, high-speed multiplier, redundant binary representation, VLSI, Arithmetic operations, hardware algorithm, signed-digit number representation
15	Tsutomu Sasao	Input Variable Assignment and Output Phase Optimization of PLA's.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	complexity of logic circuits, decoder assignment, essential prime implicants, output phase optimization, logic design, programmable logic array, Adder, switching theory
15	Hung Chi Lai, Saburo Muroga	Logic Networks of Carry-Save Adders.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders
15	S. A. Kent	A High-Speed Threshold Gate Multiplier.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	High-speed adder, threshold logic, propagation delay, partial product, parallel multiplication
15	J. A. Bate, Jon C. Muzio	Three Cell Structures for Ternary Cellular Arrays.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	combinational switching functions, ternary full adder, universal arrays, Cellular arrays, symmetric functions, ternary logic
15	Francisco J. O. Dias	Truth-Table Verification of an Iterative Logic Array.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	test, fault detection, Adder, multiple fault, cell, checking experiment, truth table, iterative array
15	John A. Gibson, R. W. Gibbard	Synthesis and Comparison of Two's Complement Parallel Multipliers.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Algorithm syntheses, full adder arrays, multiplier comparisons, parallel binary multiplication, two's complement formulation
13	R. Nishanth, C. Helen Sulochana	A novel lightweight CNN-based error-reduced carry prediction approximate full adder design for multimedia applications.	Neural Comput. Appl.	2024	DBLP DOI BibTeX RDF
13	Hemanshi Chugh, Sonal Singh	Efficient co-planar adder designs in quantum dot cellular automata: Energy and cost optimization with crossover elimination.	Integr.	2024	DBLP DOI BibTeX RDF
13	Sriram Sundar S, Mahendran G	CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications.	Integr.	2024	DBLP DOI BibTeX RDF
13	Melika Amiri, Massoud Dousti, Majid Mohammadi	Design and implementation of carry-save adder using quantum-dot cellular automata.	J. Supercomput.	2024	DBLP DOI BibTeX RDF
13	Fang Wang, Jie Bai, Linlin Liu, Tianyuan Ye	Temporal noisy-adder of bayesian network for scalable consecutive-k-out-of-n:F system reliability analysis.	Reliab. Eng. Syst. Saf.	2024	DBLP DOI BibTeX RDF
13	Chaojie He, Zi Wang, Feibin Xiang, Zhuoyu Dai, Yifan He, Jinshan Yue, Yongpan Liu	LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
13	Samane Asgari, Mohammad Reza Reshadinezhad, Seyed Erfan Fatemieh	Energy-efficient and fast IMPLY-based approximate full adder applying NAND gates for image processing.	Comput. Electr. Eng.	2024	DBLP DOI BibTeX RDF
13	Ahmad Karimi, Keivan Navi	The design of adder, subtractor, and derivative circuits without the use of op-amp in CNFET Technology.	Comput. Electr. Eng.	2024	DBLP DOI BibTeX RDF
13	S. Lakshmanachari, Sadulla Shaik, G. S. R. Satyanarayana, Inapudi Vasavi, Vallabhuni Vijay, Chandra Shaker Pittala	1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages.	Int. J. Syst. Assur. Eng. Manag.	2024	DBLP DOI BibTeX RDF
13	Manish Srivastava, Alessandro Ferro, Aleksandr Sidun, José M. de la Rosa 0001, Kilian O'Donoghue, Pádraig Cantillon-Murphy, Daniel O'Hare	A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing.	IEEE Open J. Circuits Syst.	2024	DBLP DOI BibTeX RDF
13	Gerardo Bandera, Javier Salamero, Miquel Moretó, Julio Villalba	Floating Point HUB Adder for RISC-V Sargantana Processor.	CoRR	2024	DBLP DOI BibTeX RDF
13	Kihwan Kim, Hyuk-Jae Lee, Xuan Truong Nguyen	Reconfigurable One-Adder Multiplication for CNN Acceleration.	ICEIC	2024	DBLP DOI BibTeX RDF
13	Ho-Sung Lee, Joo-Hyung Chae	A 1-Kb 6T 1C XNOR-DRAM Compute-In-Memory Macro With Signed Bit Adder Block for CNN Operations.	ICEIC	2024	DBLP DOI BibTeX RDF
13	An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si	34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Yathin Kumar Attuluri, Ruchit Chudasama, Kailash Prasad, Joycee Mekie	FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing.	VLSID	2024	DBLP DOI BibTeX RDF
13	S. Senthilkumar, V. Samuthira Pandi, T. Sripriya, N. Pragadish	Design of recustomize finite impulse response filter using truncation based scalable rounding approximate multiplier and error reduced carry prediction approximate adder for image processing application.	Concurr. Comput. Pract. Exp.	2023	DBLP DOI BibTeX RDF
13	Perumal Mahendran, M. S. Kavitha, R. Radhika, C. Kotteeswaran	Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application.	Concurr. Comput. Pract. Exp.	2023	DBLP DOI BibTeX RDF
13	Ayoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri	High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures.	IEEE Embed. Syst. Lett.	2023	DBLP DOI BibTeX RDF
13	Qi-Yue Yu, Ke-Xun Song	Uniquely Decodable Multi-Amplitude Sequence for Grant-Free Multiple-Access Adder Channels.	IEEE Trans. Wirel. Commun.	2023	DBLP DOI BibTeX RDF
13	D. Rebecca Florance, B. Prabhakar	Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies.	Integr.	2023	DBLP DOI BibTeX RDF
13	Afshin Khaksari, Omid Akbari, Behzad Ebrahimi	BEAD: Bounded error approximate adder with carry and sum speculations.	Integr.	2023	DBLP DOI BibTeX RDF
13	Jeyakumar Ponraj, R. Jeyabharath, P. Veena, Tharumar Srihari	High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system.	Integr.	2023	DBLP DOI BibTeX RDF
13	Jie Xu 0019, Gensheng Hu, Dingjun Qian	A quantum-based building block for designing a nanoscale full adder circuit with power analysis.	Integr.	2023	DBLP DOI BibTeX RDF
13	Sueyeon Kim, Insoo Choi, Sangki Cho, Myounggon Kang, Seungjae Baik, Changho Ra, Jongwook Jeon	Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET).	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Abdelsalam Al Share, Fadi Nessir Zghoul, Osama Daifallah Al-Khaleel, Mohammad Al-Khaleel, Christos A. Papachristou	Design of High Speed BCD Adder Using CMOS Technology.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Vineet Jaiswal, Trailokya Nath Sasamal	Novel approach for the design of efficient full adder in MQCA.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
13	Hyoju Seo, Yongtae Kim	A Low Latency Approximate Adder Design Based on Dual Sub-Adders With Error Recovery.	IEEE Trans. Emerg. Top. Comput.	2023	DBLP DOI BibTeX RDF
13	Umberto Garlando, Qi Wang, Oleksandr V. Dobrovolskiy, Andrii V. Chumak, Fabrizio Riente	Numerical Model for 32-Bit Magnonic Ripple Carry Adder.	IEEE Trans. Emerg. Top. Comput.	2023	DBLP DOI BibTeX RDF
13	Farshid Ahmadi, Mohammad R. Semati, Hassan Daryanavard	A Low-Power Improved-Accuracy Approximate Error-Report-Propagate Adder for DSP Applications.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
13	Vasundhara Trivedi, Khushbu Lalwani, Gopal Raut, Avikshit Khomane, Neha Ashar, Santosh Kumar Vishvakarma	Hybrid ADDer: A Viable Solution for Efficient Design of MAC in DNNs.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
13	Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee	A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
13	T. Nirmalraj, S. K. Pandiyan, Rakesh Kumar Karan, R. Sivaraman 0001, Rengarajan Amirtharajan	Design of Low-Power 10-Transistor Full Adder Using GDI Technique for Energy-Efficient Arithmetic Applications.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
13	K. Saritha Raj, P. Rajesh Kumar, M. Satyanarayana	Capricious Digital Filter Design and Implementation Using Baugh-Wooley Multiplier and Error Reduced Carry Prediction Approximate Adder for ECG Noise Removal Application.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
13	Ning Zhang, Guoqing Wang, Jue Wang 0011, He Chen, Wenchao Liu 0001, Liang Chen 0004	All Adder Neural Networks for On-Board Remote Sensing Scene Classification.	IEEE Trans. Geosci. Remote. Sens.	2023	DBLP DOI BibTeX RDF
13	Hamid Tavakolaee, Gholamreza Ardeshir, Yasser Baleghi 0001	Design and analysis of a novel fast adder using logical effort method.	IET Comput. Digit. Tech.	2023	DBLP DOI BibTeX RDF
13	Yonatan Pugachov, Moria Gulitski, Omri Mizrahi, Dror Malka	Design of All-Optical Logic Half-Adder Based on Photonic Crystal Multi-Ring Resonator.	Symmetry	2023	DBLP DOI BibTeX RDF
13	Yiming Chen, Guodong Yin, Mufeng Zhou, Wenjun Tang, Zekun Yang, Mingyen Lee, Xirui Du, Jinshan Yue, Jiaxin Liu, Huazhong Yang, Yongpan Liu, Xueqing Li	SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
13	Charalampos Eleftheriadis, Georgios Karakonstantis	Optimal Adder-Multiplexer Co-Optimization for Time-Multiplexed Multiplierless Architectures.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
13	Yifan He, Jinshan Yue, Xiaoyu Feng, Yuxuan Huang, Hongyang Jia, Jingyu Wang, Lu Zhang, Wenyu Sun, Huazhong Yang, Yongpan Liu	An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Ghassem Jaberipur, Dariush Badri, Jeong-A Lee	A Parallel Prefix Modulo-(2q + 2q-1 + 1) Adder via Diminished-1 Representation of Residues.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Ximing Li 0003, Xing Jin, Weichong Chen, Ningyuan Yin, Zhiyi Yu	Parallel-Prefix Adder in Spin-Orbit Torque Magnetic RAM for High Bit-Width Non-Volatile Computation.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Jongho Yoon, Seunghan Baek, Sunmean Kim, Seokhyeong Kang	Optimizing Ternary Multiplier Design With Fast Ternary Adder.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Aibin Yan, Runqi Liu, Jie Cui 0004, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen, Jiliang Zhang 0002	Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Mina Raouf, Somayeh Timarchi	Non-Volatile and High-Performance Cascadable Spintronic Full-Adder With No Sensitivity to Input Scheduling.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Gerson D. Andrade, Matheus Silva, Cínthia Schneider, Guilherme Paim, Sergio Bampi, Eduardo Costa 0001, Alexandra L. Zimpeck	Robustness Analysis of 3-2 Adder Compressor Designed in 7-nm FinFET Technology.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Xing Jin, Weichong Chen, Ximing Li 0003, Ningyuan Yin, Caihua Wan, Mingkun Zhao, Xiufeng Han, Zhiyi Yu	High-Reliability, Reconfigurable, and Fully Non-volatile Full-Adder Based on SOT-MTJ for Image Processing Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Forouzan Bahrami, Nabiollah Shiri, Farshad Pesaran	Imprecise Subtractor Using a New Efficient Approximate-Based Gate Diffusion Input Full Adder for Bioimages Processing.	Comput. Electr. Eng.	2023	DBLP DOI BibTeX RDF
13	B. Jeevan, K. Bikshalu, E. Hari Krishna, Kosaraju Sivani	Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
13	Senthil Pitchai, Saravanan Pitchai	Area-latency efficient floating point adder using interleaved alignment and normalization.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
13	A. Venkatesan, P. T. Vanathi, M. Elangovan	Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7 nm FINFET Technology for MIMO Applications.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
13	A. Venkatesan, P. T. Vanathi, M. Elangovan	Erratum: Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7nm FINFET Technology for MIMO Applications.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
13	A. Niyas Ahamed, M. Madheswaran	Hybrid Brent Kung Adder with Modified Sum Generator for Energy Efficient Applications.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF