Search results for "faults"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
24	Irith Pomeranz, Sudhakar M. Reddy	Test compaction for transition faults under transparent-scan.	DATE	2006	DBLP DOI BibTeX RDF
24	Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng	Off-Line Testing of Delay Faults in NoC Interconnects.	DSD	2006	DBLP DOI BibTeX RDF
24	David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil	Fast Emulation of Permanent Faults in VLSI Systems.	FPL	2006	DBLP DOI BibTeX RDF
24	Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski	Scan Tests with Multiple Fault Activation Cycles for Delay Faults.	VTS	2006	DBLP DOI BibTeX RDF
24	Zacharias Gketsis, Michalis E. Zervakis, George S. Stavrakakis	Early Detection of Winding Faults in Windmill Generators Using Wavelet Transform and ANN Classification.	ICANN (2)	2006	DBLP DOI BibTeX RDF
24	Gang Chen 0011, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski	New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic.	VLSI Design	2006	DBLP DOI BibTeX RDF
24	James Chien-Mo Li	Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Fault diagnosis, ATPG, scan chain
24	Yannick Monnet, Marc Renaudin, Régis Leveugle	Hardening Techniques against Transient Faults for Asynchronous Circuits.	IOLTS	2005	DBLP DOI BibTeX RDF
24	Toshimitsu Masuzawa, Sébastien Tixeuil	A Self-stabilizing Link-Coloring Protocol Resilient to Unbounded Byzantine Faults in Arbitrary Networks.	OPODIS	2005	DBLP DOI BibTeX RDF	link-coloring, fault tolerance, self-stabilization, distributed protocol, Byzantine fault, fault containment
24	Cecilia Metra, Martin Omaña 0001, Daniele Rossi 0001, José Manuel Cazeaux, T. M. Mak	The Other Side of the Timing Equation: a Result of Clock Faults.	DFT	2005	DBLP DOI BibTeX RDF
24	Ashraf M. Abdelbar, Plínio Roberto Souza Vilela, Mário Jino	Mapping faults to failures in SQL manipulation commands.	AICCSA	2005	DBLP DOI BibTeX RDF
24	Irith Pomeranz, Sudhakar M. Reddy	Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality.	VLSI Design	2005	DBLP DOI BibTeX RDF
24	Michele Favalli, Cecilia Metra	TMR voting in the presence of crosstalk faults at the voter inputs.	IEEE Trans. Reliab.	2004	DBLP DOI BibTeX RDF
24	João Durães, Henrique Madeira	Generic Faultloads Based on Software Faults for Dependability Benchmarking.	DSN	2004	DBLP DOI BibTeX RDF
24	Chunsheng Liu, Kumar N. Dwarakanath, Krishnendu Chakrabarty, Ronald D. Blanton	Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST.	ISVLSI	2004	DBLP DOI BibTeX RDF
24	Chuan-Ching Sue, Jun-Ying Yeh, Chin-Yu Huang	Full Restoration of Multiple Faults in WDM Networks without Wavelength Conversion.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
24	Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz	Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
24	Daniel Barros Jr., Fabian Vargas 0001, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	Modeling and Simulation of Time Domain Faults in Digital Systems.	IOLTS	2004	DBLP DOI BibTeX RDF
24	Eric F. Weglarz, Kewal K. Saluja, T. M. Mak	Testing of Hard Faults in Simultaneous Multithreaded Processors.	IOLTS	2004	DBLP DOI BibTeX RDF
24	Yusuke Sakurai, Fukuhito Ooshita, Toshimitsu Masuzawa	A Self-stabilizing Link-Coloring Protocol Resilient to Byzantine Faults in Tree Networks.	OPODIS	2004	DBLP DOI BibTeX RDF
24	Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya	Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults.	VLSI Design	2004	DBLP DOI BibTeX RDF
24	Baris Arslan, Alex Orailoglu	Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
24	Andrzej Krasniewski	Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices.	FPL	2003	DBLP DOI BibTeX RDF
24	Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri	Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard.	DFT	2003	DBLP DOI BibTeX RDF
24	Maria K. Michael, Spyros Tragoudas	ATPG tools for delay faults at the functional level.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	functional-level testing, path delay fault simulation (coverage), testing digital circuits, Automatic test pattern generation, Binary Decision Diagrams, delay testing, Boolean Satisfiability, path delay fault testing
24	Peter G. Bishop	Estimating Residual Faults from Code Coverage.	SAFECOMP	2002	DBLP DOI BibTeX RDF
24	Andrzej Krasniewski	Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
24	Peter Sobe	Checking a Non-Byzantine FT Scheme against Byzantine Faults.	IPDPS	2002	DBLP DOI BibTeX RDF
24	Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal	Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects.	ITC	2002	DBLP DOI BibTeX RDF
24	Sun-Yuan Hsieh, Gen-Huey Chen, Chin-Wen Ho	Longest Fault-Free Paths in Star Graphs with Edge Faults.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	fault tolerance, embedding, Bipartite graph, star graph, Hamiltonicity, longest path
24	Irith Pomeranz, Sudhakar M. Reddy	On diagnosis and diagnostic test generation for pattern-dependenttransition faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
24	Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu	Test Generation for Double Stuck-at Faults.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
24	Hossam M. A. Fahmy, Salma A. Ghoneim	Fault-Tolerant Communication with Partitioned Dimension-Order Routers with Complex Faults.	ICOIN	2001	DBLP DOI BibTeX RDF
24	Said Hamdioui, Ad J. van de Goor, Mike Rodgers, David Eastwick	March Tests for Realistic Faults in Two-Port Memories.	MTDT	2000	DBLP DOI BibTeX RDF
24	Max Breitling	Modeling Faults of Distributed, Reactive Systems.	FTRTFT	2000	DBLP DOI BibTeX RDF
24	Tong Liu 0007, Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi	Test generation and scheduling for layout-based detection of bridge faults in interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
24	Yukio Ohsawa, Masahiko Yachida	Discover Risky Active Faults by Indexing an Earthquake Sequence.	Discovery Science	1999	DBLP DOI BibTeX RDF
24	Sudip Chakrabarti, Abhijit Chatterjee	Fault modeling and fault sampling for isolating faults in analog and mixed-signal circuits.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
24	Diamantino Costa, Henrique Madeira	Experimental Assessment of COTS DBMS Robustness under Transient Faults.	PRDC	1999	DBLP DOI BibTeX RDF
24	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu	Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
24	Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya	Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
24	Miquel Roca 0001, Antonio Rubio 0001	Current testability analysis of feedback bridging faults in CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
24	Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	An advanced diagnostic method for delay faults in combinational faulty circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	simulation, diagnosis, delay fault, critical path tracing
24	Suresh Chalasani, Rajendra V. Boppana	Communication in Multicomputers with Nonconvex Faults.	Euro-Par	1995	DBLP DOI BibTeX RDF
24	Antonio Rubio 0001, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita	An approach to the analysis and detection of crosstalk faults in digital VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
24	S. Wayne Bollinger, Scott F. Midkiff	Test generation for IDDQ testing of bridging faults in CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
24	Chen-Pin Kung, Chen-Shang Lin	HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faults.	ICCAD	1994	DBLP DOI BibTeX RDF
24	Hyung Ki Lee, Dong Sam Ha	SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits.	DAC	1990	DBLP DOI BibTeX RDF
24	Weiwei Mao, Michael D. Ciletti	A Variable Observation Time Method for Testing Delay Faults.	DAC	1990	DBLP DOI BibTeX RDF
24	Niraj K. Jha	Testing for multiple faults in domino-CMOS logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
24	Sarma Sastry, Melvin A. Breuer	Detectability of CMOS stuck-open faults using random and pseudorandom test sequences.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
23	Seda Postalcioglu, Kadir Erkan	Soft computing and signal processing based active fault tolerant control for benchmark process.	Neural Comput. Appl.	2009	DBLP DOI BibTeX RDF	Fault detection and identification, Self-organizing map, Wavelet analysis, Fuzzy logic controller, Fault tolerant control
23	Chihoon Lee, Doohyung Lee, Jahwan Koo, Jin-Wook Chung	Proactive Fault Detection Schema for Enterprise Information System Using Statistical Process Control.	HCI (8)	2009	DBLP DOI BibTeX RDF	Proactive Fault detection, EWMA, System management, Statistical Process Control, Early Detection
23	Siva Kumar Sastry Hari, Man-Lap Li, Pradeep Ramachandran, Byn Choi, Sarita V. Adve	mSWAT: low-cost hardware fault detection and diagnosis for multicore systems.	MICRO	2009	DBLP DOI BibTeX RDF	architecture, error detection, fault injection, multicore processors
23	Andreas Haeberlen, Petr Kuznetsov	The Fault Detection Problem.	OPODIS	2009	DBLP DOI BibTeX RDF	fault detection problem, lower bounds, message complexity, Fault classes
23	Gregor von Bochmann, Stefan Haar, Claude Jard, Guy-Vincent Jourdan	Testing Systems Specified as Partial Order Input/Output Automata.	TestCom/FATES	2008	DBLP DOI BibTeX RDF	Testing distributed systems, conformance relations, partial order automata, HMSC, partial order, finite state automata
23	Shideh Shahidi, Sandeep Gupta 0001	Multi-Vector Tests: A Path to Perfect Error-Rate Testing.	DATE	2008	DBLP DOI BibTeX RDF
23	Alex Edwards, Sean Tucker, Sébastien Worms, Rahul Vaidya, Brian Demsky	AFID: an automated fault identification tool.	ISSTA	2008	DBLP DOI BibTeX RDF	fault collection
23	Caihua Wu, Xiaodong Zhu, Juntao Liu	The SRGM Framework of Integrated Fault Detection Process and Correction Process.	CSSE (2)	2008	DBLP DOI BibTeX RDF
23	Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.	DFT	2008	DBLP DOI BibTeX RDF
23	Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sahoo, Sarita V. Adve, Vikram S. Adve, Yuanyuan Zhou	Understanding the propagation of hard errors to software and implications for resilient system design.	ASPLOS	2008	DBLP DOI BibTeX RDF	architecture, error detection, fault injection, permanent fault
23	John Marty Emmert, Charles E. Stroud, Miron Abramovici	Online Fault Tolerance for FPGA Logic Blocks.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
23	Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang 0011, Michael Orshansky	Architecting a reliable CMP switch architecture.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	CMP switch, reliability, defect-tolerance
23	Jon Arvid Børretzen, Jostein Dyre-Hansen	Investigating the Software Fault Profile of Industrial Projects to Determine Process Improvement Areas: An Empirical Study.	EuroSPI	2007	DBLP DOI BibTeX RDF
23	Erdal Kiliç, Okan Ozgonenel, Mustafa Ulutas	Fault Identification in Transformers through a Fuzzy Discrete Event System Approach.	FUZZ-IEEE	2007	DBLP DOI BibTeX RDF
23	Christian J. Hescott, Drew C. Ness, David J. Lilja	Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault Environment.	DSD	2007	DBLP DOI BibTeX RDF
23	Barbara Pernici, Anna Maria Rosati	Automatic Learning of Repair Strategies for Web Services.	ECOWS	2007	DBLP DOI BibTeX RDF
23	C.-Y. Huang, C.-T. Lin	Software Reliability Analysis by Considering Fault Dependency and Debugging Time Lag.	IEEE Trans. Reliab.	2006	DBLP DOI BibTeX RDF
23	Mohammad Gh. Mohammad, Kewal K. Saluja	Optimizing program disturb fault tests using defect-based testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
23	Man Fai Lau, Yuen-Tak Yu	An extended fault class hierarchy for specification-based testing.	ACM Trans. Softw. Eng. Methodol.	2005	DBLP DOI BibTeX RDF	Fault class analysis, software testing, test case generation, specification-based testing
23	Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu	Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
23	Allen P. Nikora, John C. Munson	The Effects of Fault Counting Methods on Fault Model Quality.	COMPSAC	2004	DBLP DOI BibTeX RDF	defect content estimation techniques, software measurement, software modeling, fault prediction
23	Cristian Constantinescu	Experimental evaluation of error-detection mechanisms.	IEEE Trans. Reliab.	2003	DBLP DOI BibTeX RDF
23	Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu	Testing and Diagnosis Methodologies for Embedded Content Addressable Memories.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	march test algorithm, memory diagnostics, BIST, memory testing, CAM
23	Tomas Berling, Thomas Thelin	An Industrial Case Study of the Verification and Validation Activities.	IEEE METRICS	2003	DBLP DOI BibTeX RDF	fault detection technique, software process metrics, software testing, case study, software process improvement, incremental development, software validation
23	Ching-Tien Ho, Larry J. Stockmeyer	A New Approach to Fault-Tolerant Wormhole Routing for Mesh-Connected Parallel Computers.	IPDPS	2002	DBLP DOI BibTeX RDF
23	Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu	Testing and Diagnosing Embedded Content Addressable Memories.	VTS	2002	DBLP DOI BibTeX RDF
23	Yuen-Tak Yu, Man Fai Lau	Prioritization of Test Cases in MUMCUT Test Sets: An Empirical Study.	Ada-Europe	2002	DBLP DOI BibTeX RDF
23	Ulrich Schmid 0001	How to Model Link Failures: A Perception-Based Fault Model.	DSN	2001	DBLP DOI BibTeX RDF	consistent broadcasting, fault models, clock synchronization, link failures, Fault-tolerant distributed systems
23	A. B. M. Harun-ur Rashid, Mazuhidul Karim, Syed Mahfuzul Aziz	Testing complementary pass-transistor logic circuits.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
23	Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi	Testing SRAM-Based Content Addressable Memories.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	March C algorithm, fault detection, fault modeling, memory testing, Content addressable memory
23	John Marty Emmert, Dinesh K. Bhatia	A Fault Tolerant Technique for FPGAs.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	incremental reconfiguration, incremental routing, incremental placement, fault tolerance, FPGA
23	Michael S. Hsiao, Srimat T. Chakradhar	Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	static test set compaction, vector-reordering, fault coverage curve, partitioning, ATPG
23	Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey	Fault Escapes in Duplex Systems.	VTS	2000	DBLP DOI BibTeX RDF	Duplex systems, Common-Mode Failures (CMFs), Test points, User-programmable logic, Data Integrity, Availability, Diversity
23	Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi	Adaptive Fault Detection and Diagnosis of RAM Interconnects.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	interconnect, memory, diagnosis, detection, wiring
23	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Nobuhiro Yanagida	Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	single/multiple fault simulators, EB tester, fault diagnosis, combinational circuit, multiple stuck-at fault
23	Michael L. Bushnell, John Giraldi	A Functional Decomposition Method for Redundancy Identification and Test Generation.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	redundancy identification, logic testing, automatic test generation, backtracing
23	Hin-Sing Siu, Yeh-Hao Chin, Wei-Pang Yang	A Note on Consensus on Dual Failure Modes.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	dual failure modes, fault tolerance, distributed systems, Byzantine Agreement, consensus problem, hybrid fault model
23	Nabanita Das 0001, Jayasree Dattagupta	A fault location technique and alternate routing in Benes network.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	fault location technique, single switch fault, recirculation, source-destination path, routing technique, exact locations, multiple switch fault detection, one bit test vectors, equivalent fault set, fault diagnosis, fault tolerant computing, reconfiguration, reconfigurable architectures, multistage interconnection networks, multistage interconnection networks, network routing, Benes network, rearrangeable network, alternate routing
23	Henrique Madeira, Mário Zenha Rela, Francisco Moreira 0001, João Gabriel Silva	RIFLE: A General Purpose Pin-level Fault Injector.	EDCC	1994	DBLP DOI BibTeX RDF
23	Kwang-Ting Cheng	Transition fault testing for sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
23	A. Jefferson Offutt	Investigations of the Software Testing Coupling Effect.	ACM Trans. Softw. Eng. Methodol.	1992	DBLP DOI BibTeX RDF	software testing, unit testing, mutation, fault-based testing
23	Jwu E. Chen, Chung-Len Lee 0001, Wen-Zen Shen	Single-fault fault-collapsing analysis in sequential logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
23	Kyriakos Christou, Maria K. Michael, Spyros Tragoudas	On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Zero-suppressed binary decision diagram, Irredundant sum-of-products, Critical path delay faults, Compact test generation, Delay testing, Path delay faults
23	Martin Biely, Josef Widder, Bernadette Charron-Bost, Antoine Gaillard, Martin Hutle, André Schiper	Tolerating corrupted communication.	PODC	2007	DBLP DOI BibTeX RDF	consensus, transient faults, byzantine fault tolerance, dynamic faults
23	Muhsen Aljada, Adam Osseiran, Kamal E. Alameh	Catastrophic and Parametric Fault Modelling for Photonic Systems.	DELTA	2006	DBLP DOI BibTeX RDF	photonic, photonic testing, fault modelling, fault simulation, parametric faults, catastrophic faults
23	Rajesh Ramadoss, Michael L. Bushnell	Test Generation for Mixed-Signal Devices Using Signal Flow Graphs.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	analog test generation, mixed-signal test generation, back tracing, parametric faults, catastrophic faults
23	Trevor Williams, Jack Tan, Chungti Liang	Efficient implementation strategies for the DRB approach in fault-tolerant hypercubes.	COMPSAC	1997	DBLP DOI BibTeX RDF	distributed recovery block approach, fault-tolerant hypercubes, application tasks graph, processor nodes, primary cost factors, dilation bound, expansion factor, DRB approach, spare processors, hypercube networks, congestion, real-time applications, software faults, implementation strategies, hardware faults
23	Cheng-Ping Wang, Chin-Long Wey	Test Generation Of Analog Switched-Current Circuits.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	switched current circuits, analog switched-current circuits, current switches, voltage switches, noncatastrophic faults, transistor switches, full testability, current copiers, stray inductance, CMOS switch, BIST design, fault model, circuit simulation, macromodel, switched-capacitor circuits, test sequence generation, catastrophic faults
23	Gosta Pada Biswas, Idranil Sen Gupta	Generalized modular design of testable m-out-of-n code checker.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testable m-out-of-n code checker, combinational logic port, combinational logic cells, unidirectional faults, complementary outputs, VLSI, fault diagnosis, logic testing, cellular automata, combinational circuits, fault location, stuck-at faults, logic arrays, cellular automaton, modular design, iterative array, initial state