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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2784 occurrences of 1319 keywords
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Results
Found 4097 publication records. Showing 4097 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | David M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher |
An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt |
Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. |
ISCA |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Mountassar Maamoun, Boualem Laichi, Abdelhalim Benbelkacem, Daoud Berkani |
Interfacing in Microprocessor-based Systems with an Advanced Physical Addressing. |
IWSOC |
2004 |
DBLP DOI BibTeX RDF |
Software/Hardware system, Advanced Physical Addressing, memory integration, Interfacing, DMA |
18 | David S. Kung 0001 |
Timing closure for low-FO4 microprocessor design. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
FO4, synthesis, placement, high performance |
18 | Anshuman S. Nadkarni, Tom Kenville |
TiGeR, the Transmeta Instruction GEneratoR: A Production Based, Pseudo Random Instruction x86 Test Generator. |
MTV |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham |
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. |
MTV |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda |
Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores. |
MTV |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman |
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin |
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. |
MICRO |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Hai Li 0001, Swarup Bhunia, Yiran Chen 0001, T. N. Vijaykumar, Kaushik Roy 0001 |
Deterministic Clock Gating for Microprocessor Power Reduction. |
HPCA |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Yale N. Patt |
The High Performance Microprocessor in the Year 2013: What Will It Look Like? What It Won't Look Like? |
HiPC |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Ling Liu, Wennan Feng, Song Jia, Anping Jiang, Lijiu Ji |
Design Retargetable Platform System for Microprocessor Functional Test. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Ryuichi Takahashi, Hajime Ohiwa |
Situated Learning on FPGA for Superscalar Microprocessor Design Education. |
SBCCI |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Derek B. Gottlieb, Nicholas P. Carter |
Microprocessor Interfacing Laboratory. |
MSE |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Won Jay Song, Won Hee Kim, Bo Gwan Kim, Byung-Ha Ahn, Mun Kee Choi, Minho Kang |
Smart Card Terminal Systems Using ISO/IEC 7816-3 Interface and 8051 Microprocessor Based on the System-on-Chip. |
ISCIS |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies |
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Ákos Zarándy, Csaba Rekeczky, István Szatmári |
Vision systems based on the 128×128 focal plane cellular visual microprocessor chips. |
ISCAS (3) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Teresa L. McLaurin, Frank Frederick, Rich Slobodnik |
The Testability Features of The ARM1026EJ Microprocessor Core. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Scott Erlanger, Dilip K. Bhavsar, Richard A. Davies |
Testability Features of the Alpha 21364 Microprocessor. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir |
A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. |
MTV |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Alexander Klaiber, Sinclair Chau |
Automatic Detection of Logic Bugs in Hardware Designs. |
MTV |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, José-Lorenzo Cruz, Fernando Latorre, Antonio González 0001, Mateo Valero |
Errata on "Measuring Experimental Error in Microprocessor Simulation". |
SIGARCH Comput. Archit. News |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Michael B. Taylor, Jason Sungtae Kim, Jason E. Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffmann, Paul R. Johnson, Jae W. Lee, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matthew I. Frank, Saman P. Amarasinghe, Anant Agarwal |
The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs. |
IEEE Micro |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Forrest Brewer, Steve Haynal |
Symbolic NFA scheduling of a RISC microprocessor. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Mauro Olivieri |
Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Hongshen Ma, Joseph A. Paradiso |
The FindIT Flashlight: Responsive Tagging Based on Optically Triggered Microprocessor Wakeup. |
UbiComp |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Loe M. G. Feijs, Paul Gorissen, Joachim Trescher |
Specification and Simulation of Microprocessor Operations and Parallel Instructions. |
DSD |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Kevin Skadron |
A microprocessor survey course for learning advanced computer architecture. |
SIGCSE |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Lawrence T. Clark, Neil Deutscher, Shay Demmons, Franco Ricci |
Standby power management for a 0.18µm microprocessor. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
body effect, low power, microprocessors |
18 | Rita Yu Chen, Paul Yip, Georgios K. Konstadinidis, Andrew Demas, Fabian Klass, Robert E. Mains, Margaret Schmitt, Dina Bistry |
Timing Window Applications in UltraSPARC-IIIi? Microprocessor Design. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero |
Automatic Test Program Generation from RT-Level Microprocessor Descriptions. |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Mark D. Aagaard, Nancy A. Day, Meng Lou |
Relating Multi-step and Single-Step Microprocessor Correctness Statements. |
FMCAD |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Dawit Belete, Ashutosh Razdan, William Schwarz, Rajesh Raina, Christopher Hawkins, Jeff Morehead |
Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor . |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Timothe Litt |
Support for Debugging in the Alpha 21364 Microprocessor. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Allan Hartstein, Thomas R. Puzak |
The Optimum Pipeline Depth for a Microprocessor. |
ISCA |
2002 |
DBLP DOI BibTeX RDF |
|
18 | T. Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura |
Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. |
APCCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Neal A. Harman |
Verifying a Simple Pipelined Microprocessor Using Maude. |
WADT |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Øyvind Strøm, Einar J. Aas |
An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java Code. |
DSD |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Johan A. Pouwelse, Koen Langendoen, Henk J. Sips |
Dynamic voltage scaling on a low-power microprocessor. |
MobiCom |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Robert H. Klenke |
Design of a 32-Bit Microprocessor in an Undergraduate VLSI Design Course. |
MSE |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Atsuhiro Suga, Kunihiko Matsunami |
Introducing the FR500 Embedded Microprocessor. |
IEEE Micro |
2000 |
DBLP DOI BibTeX RDF |
|
18 | John N. Coleman, E. I. Chester, Christopher I. Softley, Jiri Kadlec |
Arithmetic on the European Logarithmic Microprocessor. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
interpolation, Digital arithmetic, logarithmic number system |
18 | Volkmar Lotz, Volker Kessler, Georg Walter |
A Formal Security Model for Microprocessor Hardware. |
IEEE Trans. Software Eng. |
2000 |
DBLP DOI BibTeX RDF |
Security, hardware, formal security models |
18 | David Van Campenhout, Trevor N. Mudge, John P. Hayes |
Collection and Analysis of Microprocessor Design Errors. |
IEEE Des. Test Comput. |
2000 |
DBLP DOI BibTeX RDF |
|
18 | André Brinkmann, Dominik Langen, Ulrich Rückert 0001 |
A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor. |
FPL |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Subramania Sudharsanan |
MAJC-5200: A High Performance Microprocessor for Multimedia Computing. |
IPDPS Workshops |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Jürgen Teich, Philipp W. Kutter, Ralph Weper |
Description and Simulation of Microprocessor Instruction Sets Using ASMs. |
Abstract State Machines |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Raoul Velazco, Sana Rezgui |
Transient Bitflip Injection in Microprocessor Embedded Applications. |
IOLTW |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Jen-Tien Yen, Qichao Richard Yin |
Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas |
Impact of interconnect variations on the clock skew of a gigahertz microprocessor. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Armin Biere, Edmund M. Clarke, Richard Raimi, Yunshan Zhu |
Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs. |
CAV |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Volkmar Lotz, Volker Kessler, Georg Walter |
A Formal Security Model for Microprocessor Hardware. |
World Congress on Formal Methods |
1999 |
DBLP DOI BibTeX RDF |
security, hardware, formal security models |
18 | Xinghao Chen 0004, Thomas J. Snethen, Joe Swenton, Ron Walther |
A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor. |
Asian Test Symposium |
1999 |
DBLP DOI BibTeX RDF |
ATPG, DFT |
18 | Martin S. Schmookler, Michael Putrino, Anh Mather, Jon Tyler, Huy Van Nguyen, Charles Roth, Mukesh Sharma, Mydung N. Pham, Jeff Lent |
A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension. |
IEEE Symposium on Computer Arithmetic |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Nancy A. Day, Jeffrey R. Lewis, Byron Cook |
Symbolic Simulation of Microprocessor Models using Type Classes in Haskell. |
CHARME |
1999 |
DBLP DOI BibTeX RDF |
|
18 | William Fornaciari, Donatella Sciuto, Cristina Silvano |
Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
|
18 | James K. Huggins, David Van Campenhout |
Specification and verification of pipelining in the ARM2 RISC microprocessor. |
ACM Trans. Design Autom. Electr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
ARM processor, formal verification, pipelining, abstract state machines, design verification, pipelined processors |
18 | Carol Pyron, Javier Prado, James Golab |
Test Strategy for the PowerPC 750 Microprocessor. |
IEEE Des. Test Comput. |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Li-C. Wang, Magdy S. Abadir, Jing Zeng |
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
Design Error Models, Verification, Design Validation |
18 | Claude Ackad |
Statechart-Based HW/SW-Codesign of a Multi-FPGA-Board and a Microprocessor. |
FPL |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Sergej Sawitzki, Achim Gratz, Rainer G. Spallek |
Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays. |
FPL |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Wayne M. Needham, Cheryl Prunty, Yeoh Eng Hong |
High volume microprocessor test escapes, an analysis of defects our tests are missing. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Mary P. Kusko, Bryan J. Robbins, Thomas J. Snethen, Peilin Song, Thomas G. Foote, William V. Huott |
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Young-Jun Kwon, Ben Mathew, Hong Hao |
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Dilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson |
Testability access of the high speed test features in the Alpha 21264 microprocessor. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda |
A fault injection environment for microprocessor-based boards. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Partha S. Roop, Arcot Sowmya |
CFSMcharts: A New Language for Microprocessor Based system Design. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Anthony C. J. Fox, Neal A. Harman |
Algebraic Models of Superscalar Microprocessor Implementations: A Case Study. |
Prospects for Hardware Foundations |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy |
Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
PowerPC |
18 | Nevine Nassif, Madhav P. Desai, Dale H. Hall |
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
reconstruction, emulation, visibility, functional simulation |
18 | Mario Zagar, Danko Basch |
Microprocessor Architecture Design with ATLAS. |
IEEE Des. Test Comput. |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Geoff Barrett, Anthony McIsaac |
Model Checking in a Microprocessor Design Project. |
CAV |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Junji Mori, Ben Mathew, Dave Burns, Yeuk-Hai Mok |
Testability Features of R10000 Microprocessor. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
Lfsr, Observability Register, Clock Stretch, Fault Simulation, Memory Test |
18 | Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul I. Pénzes, Robert Southworth, Uri Cummings |
The Design of an Asynchronous MIPS R3000 Microprocessor. |
ARVLSI |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung |
A C-Based RTL Design Verification Methodology for Complex Microprocessor. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
C |
18 | Zarka Cvetanovic, Dileep Bhandarkar |
Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads. |
HPCA |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Maurizio Damiani, Leonardo Impagliazzo, G. Sartore |
On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications. |
EDCC |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Don Douglas Josephson, Mark Storey, Daniel D. Dixon |
Microprocessor IDDQ Testing: A Case Study. |
IEEE Des. Test Comput. |
1995 |
DBLP DOI BibTeX RDF |
|
18 | Mike Simone, A. Essen, A. Ike, A. Krishnamoorthy, Tak Maruyama, Niteen Patkar, M. Ramaswami, Michael Shebanow, V. Thirumalaiswamy, DeForest Tovey |
Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor. |
ISCA |
1995 |
DBLP DOI BibTeX RDF |
SPARC |
18 | Takashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura |
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor. |
IEEE Des. Test Comput. |
1994 |
DBLP DOI BibTeX RDF |
|
18 | José A. Tierno, Alain J. Martin, Drazen Borkovic, Tak-Kwan Lee |
A 100-MIPS GaAs Asynchronous Microprocessor. |
IEEE Des. Test Comput. |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Krste Asanovic, Nelson Morgan, John Wawrzynek |
Using simulations of reduced precision arithmetic to design a neuro-microprocessor. |
J. VLSI Signal Process. |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Qian Zhang, Herbert Grünbacher |
Petri Nets Modeling in Pipelined Microprocessor Design. |
Application and Theory of Petri Nets |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Robert S. Boyer, Yuan Yu |
Automated Correctness Proofs of Machine Code Programs for a Commercial Microprocessor. |
CADE |
1992 |
DBLP DOI BibTeX RDF |
Nqthm, Boyer-Moore Theorem Prover, Gnu, Ada, C, Automated reasoning, object code, formal program verification |
18 | Gu Qing Zuo, An Zhong Wang |
MPS - An Experimental Multi-Microprocessor Based Parallel System. |
CONPAR |
1990 |
DBLP DOI BibTeX RDF |
|
18 | Mark Bickford, Mandayam K. Srivas |
Verification of a Pipelined Microprocessor Using Clio. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
18 | Alain J. Martin |
The Design of a Delay-Insensitive Microprocessor: An Example of Circuit Synthesis by Program Transformation. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
18 | Francisco J. García-Ugalde, Robert Morelos-Zaragoza |
Design of a Viterbi Decoder with Microprocessor-Based Serial. |
AAECC |
1986 |
DBLP DOI BibTeX RDF |
|
18 | Samuel O. Aletan, William Lively |
Multiprocessor/multiarchitecture microprocessor design (M3D). |
ACM Conference on Computer Science |
1985 |
DBLP DOI BibTeX RDF |
|
18 | Gotaro Odawara, Masahiro Tomita, Ichiro Ogata |
Diagrammatic function description of microprocessor and data-flow processor. |
DAC |
1985 |
DBLP DOI BibTeX RDF |
|
18 | Thomas Philip, Stefan Jeglinski, Richard D. Benton, Robert L. Cook 0003 |
Design of a microprocessor based programmable system to process temperature information from a hot surface. |
ACM Southeast Regional Conference |
1982 |
DBLP DOI BibTeX RDF |
|
18 | Alfred C. Weaver |
A real-time, multi-task programming language for microprocessor-based industrial process control. |
ACM Annual Conference (2) |
1978 |
DBLP DOI BibTeX RDF |
|
18 | John H. Carson, John K. Summers, James S. Welch Jr. |
A microprocessor selective encryption terminal for privacy protection. |
AFIPS National Computer Conference |
1977 |
DBLP DOI BibTeX RDF |
|
18 | Reg A. Kaenel |
MagicScore bowling scorer: a microprocessor application for fun and profit. |
AFIPS National Computer Conference |
1976 |
DBLP DOI BibTeX RDF |
|
13 | Ruhi Sarikaya, Alper Buyuktosunoglu |
A Unified Prediction Method for Predicting Program Behavior. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
Microprocessor performance phase prediction, adaptive dynamic management, application program phase prediction |
13 | Jong Sung Lee, Kevin Skadron, Sung Woo Chung |
Predictive Temperature-Aware DVFS. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
Microprocessor, DVFS, performance counter, dynamic thermal management, thermal sensor |
13 | Daniele Rossi 0001, Martin Omaña 0001, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche |
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. |
Conf. Computing Frontiers |
2010 |
DBLP DOI BibTeX RDF |
microprocessor, on-line testing, control logic |
13 | Hui Zeng, Matt T. Yourst, Kanad Ghose |
An energy-efficient checkpointing mechanism for out of order commit processor. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
checkpoint, microprocessor |
13 | Hui Zeng, Ju-Young Jung, Kanad Ghose, Dmitry Ponomarev 0001 |
Energy-efficient renaming with register versioning. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
microprocessor, register renaming |
13 | Kaisheng Zhang, Jiaan Zhang, Guofa Guo |
Research on Simulating-Human Intelligent Control Method for the Cold-Storage of Fruits and Vegetables. |
HIS (3) |
2009 |
DBLP DOI BibTeX RDF |
control method, simulating-human intelligent control, embedded microprocessor, cold-storage of fruits and vegetables, temperature and humidity |
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