Search results for "PI-Bus"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
25	Ganghee Lee, Seokhyun Lee, Yongjin Ahn, Kiyoung Choi	Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration.	ICSAMOS	2007	DBLP DOI BibTeX RDF
25	Shanq-Jang Ruan, Shang-Fang Tsai, Yu-Ting Pai	Design and Analysis of Low Power Dynamic Bus Based on RLC simulation.	ISVLSI	2007	DBLP DOI BibTeX RDF
25	K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas	Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme.	ISVLSI	2007	DBLP DOI BibTeX RDF
25	Ya-Shu Chen, Song-Jian Tang, Shi-Wu Lo	A priority assignment strategy of processing elements over an on-chip bus.	SAC	2007	DBLP DOI BibTeX RDF	hardware/software codesign, processing elements, priority assignment
25	Thuyen Le, Tilman Glökler, Jason Baumgartner	Formal verification of a pervasive interconnect bus system in a high-performance microprocessor.	DATE	2007	DBLP DOI BibTeX RDF
25	David W. Siljenberg, Steve Baumgartner, Tim Buchholtz, Mark Maxson, Trevor Timpane, Jeff Johnson	Xbox360TM Front Side Bus - A 21.6 GB/s End-to-End Interface Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF
25	Bradley R. Quinton, Steven J. E. Wilton	Embedded Programmable Logic Core Enhancements for System Bus Interfaces.	FPL	2007	DBLP DOI BibTeX RDF
25	Haishan Li, Ming Zhang 0001, Wei Zheng, Dongxiao Li	An Adaptive Arbitration Algorithm for SoC Bus.	IEEE NAS	2007	DBLP DOI BibTeX RDF
25	Alexander Khitun, Mingqiang Bao, Jooyoung Lee, Kang L. Wang, D. W. Lee, S. Wang	Cellular Nonlinear Network with Spin Wave Bus.	ITNG	2007	DBLP DOI BibTeX RDF
25	Cheng-Min Lien, Ya-Shu Chen, Chi-Sheng Shih 0001	On-Chip Bus Architecture Optimization for Multi-core SoC Systems.	SEUS	2007	DBLP DOI BibTeX RDF
25	David O. Savageau, Thomas J. Overbye	Adaptive Influence Distance Algorithm for Contouring Bus-Based Power System Data.	HICSS	2007	DBLP DOI BibTeX RDF
25	Bratislav Predic, Dragan Stojanovic, Slobodanka Djordjevic-Kajan, Aleksandar Milosavljevic, Dejan D. Rancic	Prediction of Bus Motion and Continuous Query Processing for Traveler Information Services.	ADBIS	2007	DBLP DOI BibTeX RDF	Automatic Vehicle Location (AVL), prediction of arrival/travel time, intelligent transportation systems (ITS), information services, continuous query processing
25	Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan	Interframe Bus Encoding Technique for Low Power Video Compression.	VLSI Design	2007	DBLP DOI BibTeX RDF
25	Sungchan Kim, Soonhoi Ha	Efficient exploration of bus-based system-on-chip architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
25	Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn	Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
25	Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou	RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
25	Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli	Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm.	PATMOS	2006	DBLP DOI BibTeX RDF
25	Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim	A systematic IP and bus subsystem modeling for platform-based system design.	DATE	2006	DBLP DOI BibTeX RDF
25	Shang-Fang Tsai, Shanq-Jang Ruan	DS2IS: Dictionary-based Segmented Signal Inversion Scheme for Low Power Dynamic Bus Design.	ICIT	2006	DBLP DOI BibTeX RDF
25	Sujan Pandey, Manfred Glesner	Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture.	FPL	2006	DBLP DOI BibTeX RDF
25	Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen	Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs.	ISPD	2006	DBLP DOI BibTeX RDF	fault-tolerant, reliability, low power, coupling capacitance
25	Avnish R. Brahmbhatt, Jingyi Zhang, Qinru Qiu, Qing Wu 0002	Adaptive low-power bus encoding based on weighted code mapping.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Mircea Popa 0001, Voicu Groza, Alina Botas	Lin Bus Testing Software.	CCECE	2006	DBLP DOI BibTeX RDF
25	Rajeev R. Rao, Harmander Deogun, David T. Blaauw, Dennis Sylvester	Bus encoding for total power reduction using a leakage-aware buffer configuration.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
25	Nizar Bouabdallah, André-Luc Beylot, Emannuel Dotaro, Guy Pujolle	Resolving the Fairness Issues in Bus-Based Optical Access Networks.	IEEE J. Sel. Areas Commun.	2005	DBLP DOI BibTeX RDF
25	Ashutosh Chakraborty, Enrico Macii, Massimo Poncino	Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.	PATMOS	2005	DBLP DOI BibTeX RDF
25	Frank Leymann	The (Service) Bus: Services Penetrate Everyday Life.	ICSOC	2005	DBLP DOI BibTeX RDF
25	Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn	Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design.	IPDPS	2005	DBLP DOI BibTeX RDF
25	Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel	Retargetable generation of TLM bus interfaces for MP-SoC platforms.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	simulation, SystemC, architecture exploration, TLM, retargetability, MP-SoC
25	Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Simona Doboli	Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
25	Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane	Floorplan-aware automated synthesis of bus-based communication architectures.	DAC	2005	DBLP DOI BibTeX RDF	systems-on-chip, communication synthesis
25	Mauro Olivieri, Francesco Pappalardo 0002, Giuseppe Visalli	Bus-switch coding for reducing power dissipation in off-chip buses.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
25	Edgar den Boef, Wim F. J. Verhaegh, Jan H. M. Korst	Bus and Buffer Usage in In-Home Digital Networks: Applying the Dantzig-Wolfe Decomposition.	J. Sched.	2004	DBLP DOI BibTeX RDF	in-home digital network, linear programming, resource management, buffer, transmission schedule, Dantzig-Wolfe decomposition, bandwidth smoothing
25	Nattawut Thepayasuwan, Alex Doboli	Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip.	DATE	2004	DBLP DOI BibTeX RDF
25	Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger	Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards.	DATE	2004	DBLP DOI BibTeX RDF
25	Matheos Lampropoulos, Bashir M. Al-Hashimi, Paul M. Rosinger	Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique.	DATE	2004	DBLP DOI BibTeX RDF
25	Edgar den Boef, Jan H. M. Korst, Wim F. J. Verhaegh	Optimal Bus and Buffer Allocation for a Set of Leaky-Bucket-Controlled Streams.	ICT	2004	DBLP DOI BibTeX RDF	leaky-bucket-traffic characterization, in-home digital network, smoothing variable-bit-rate streams, resource management
25	Zhiqiang Liu, Toru Ishida 0001, Huanye Sheng	Multiagent-Based Demand Bus Simulation for Shanghai.	MMAS	2004	DBLP DOI BibTeX RDF
25	A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson	Tester Architecture For The Source Synchronous Bus.	ITC	2004	DBLP DOI BibTeX RDF
25	Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David T. Blaauw	Leakage-and crosstalk-aware bus encoding for total power reduction.	DAC	2004	DBLP DOI BibTeX RDF	low power, encoding, leakage reduction
25	Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani	Integrated floorplanning with buffer/channel insertion for bus-based designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
25	Edgar den Boef, Wim F. J. Verhaegh, Jan H. M. Korst	Smoothing Streams in an In-Home Digital Network: Optimization of Bus and Buffer Usage.	Telecommun. Syst.	2003	DBLP DOI BibTeX RDF	in-home digital network, resource management, buffer, transmission schedule, bandwidth smoothing
25	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi	A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems.	PATMOS	2003	DBLP DOI BibTeX RDF
25	Byung-Soo Choi, Dong-Ik Lee	Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus.	PATMOS	2003	DBLP DOI BibTeX RDF
25	M. Madhu, V. Srinivasa Murty, V. Kamakoti 0001	Dynamic Coding Technique For Low-Power Data Bus.	ISVLSI	2003	DBLP DOI BibTeX RDF
25	Nicola Drago, Franco Fummi, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino	Estimation of Bus Performance for a Tuplespace in an Embedded Architecture.	DATE	2003	DBLP DOI BibTeX RDF
25	Nattawut Thepayasuwan, Vaishali Damle, Alex Doboli	Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip.	ICCD	2003	DBLP DOI BibTeX RDF
25	Shinsaku Shimizu, Toshimasa Matsuoka, Kenji Taniguchi 0001	Parallel bus systems using code-division multiple access technique.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
25	Jongsun Kim, Zhiwei Xu 0003, Mau-Chung Frank Chang	Reconfigurable memory bus systems using multi-Gbps/pin CDMA I/O transceivers.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
25	D. J. Beauregard, Zbigniew Kalbarczyk, Ravishankar K. Iyer, Savio N. Chau, Leon Alkalai	Error-Injection-Based Failure Characterization of the IEEE 1394 Bus.	IOLTS	2003	DBLP DOI BibTeX RDF
25	Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin	A Low Power-Delay Product Page-Based Address Bus Coding Method.	VLSI Design	2003	DBLP DOI BibTeX RDF
25	Paul-Peter Sotiriadis, Anantha P. Chandrakasan	A bus energy model for deep submicron technology.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
25	Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki	CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	SoC test control, TAPed cores, P1500 wrappers, test access mechanism, I/O bandwidth
25	Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani	Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.	ISPD	2002	DBLP DOI BibTeX RDF	floorplanning, routability, interconnect estimation
25	Chuanjun Zhang, Frank Vahid	A power-configurable bus for embedded systems.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
25	Daniele Rossi 0001, Steven V. E. S. van Dijk, Richard P. Kleihorst, A. H. Nieuwland, Cecilia Metra	Coding Scheme for Low Energy Consumption Fault-Tolerant Bus.	IOLTW	2002	DBLP DOI BibTeX RDF
25	Tony Givargis, Frank Vahid, Jörg Henkel	Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
25	Marcello Lajolo	Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
25	Paul-Peter Sotiriadis, Anantha P. Chandrakasan	Reducing bus delay in submicron technology using coding.	ASP-DAC	2001	DBLP DOI BibTeX RDF
25	Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj	RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits.	ISQED	2001	DBLP DOI BibTeX RDF
25	Koen Danckaert, Chidamber Kulkarni, Francky Catthoor, Hugo De Man, Vivek Tiwari	A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging.	VLSI Design	2001	DBLP DOI BibTeX RDF
25	Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante	Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
25	Wei-Chung Cheng, Massoud Pedram	Power-optimal encoding for DRAM address bus (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
25	Martin Maierhofer, Christopher Bailey 0002	On ATM Cell Batching and Its Effects on Bus Arbitration in a Conventional Multimedia Server.	EUROMICRO	2000	DBLP DOI BibTeX RDF
25	Michael D. Jones, Ganesh Gopalakrishnan	Verifying Transaction Ordering Properties in Unbounded Bus Networks through Combined Deductive/Algorithmic Methods.	FMCAD	2000	DBLP DOI BibTeX RDF
25	Vince E. Boros, Aleksandar D. Rakic, Sri Parameswaran	High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system.	DAC	2000	DBLP DOI BibTeX RDF
25	Preeti Ranjan Panda, Nikil D. Dutt	Low-power memory mapping through reducing address bus activity.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
25	Roberto Giorgi, Cosimo Antonio Prete	PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	performance evaluation, multiprocessor, Cache memory, coherence protocol
25	Shung-Shing Lee, Shi-Jinn Horng, Horng-Ren Tsai	Entropy thresholding and its parallel algorithm on the reconfigurable array of processors with wider bus networks.	IEEE Trans. Image Process.	1999	DBLP DOI BibTeX RDF
25	Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer	Power optimization of core-based systems by address bus encoding.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
25	Mihaela Sighireanu, Radu Mateescu 0001	Verification of the Link Layer Protocol of the IEEE-1394 Serial Bus (FireWire): An Experiment with E-LOTOS.	Int. J. Softw. Tools Technol. Transf.	1998	DBLP DOI BibTeX RDF
25	Eila Niemelä, Harri Perunka, Tomi Korpipää	A Software Bus as a Platform for a Family of Distributed Embedded System Products.	ESPRIT ARES Workshop	1998	DBLP DOI BibTeX RDF
25	Mattias O'Nils, Johnny Öberg, Axel Jantsch	Grammar Based Modelling and Synthesis of Device Drivers and Bus Interfaces.	EUROMICRO	1998	DBLP DOI BibTeX RDF
25	Reuben Schrift	Digital bus faults measuring techniques.	ITC	1998	DBLP DOI BibTeX RDF
25	Giuliana Franceschinis, Andrea Fumagalli, Roberto Grasso	Performance Analysis of a WDM Bus Network Based on GSPN Models.	Computer Performance Evaluation (Tools)	1998	DBLP DOI BibTeX RDF
25	Michael Gasteier, Manfred Glesner	Bus-Based Communication Synthesis on System-Level.	ISSS	1996	DBLP DOI BibTeX RDF
25	James M. Purtilo	The POLYLITH Software Bus.	ACM Trans. Program. Lang. Syst.	1994	DBLP DOI BibTeX RDF	architecture specification
25	Karen Seidel 0002	Case Study: Specification and Refinement of the PI-Bus.	FME	1994	DBLP DOI BibTeX RDF
25	MenChow Chiang, Gurindar S. Sohi	Experience with Mean Value Analysis Models for Evaluating Shared Bus, Throughput-Oriented Multiprocessors.	SIGMETRICS	1991	DBLP DOI BibTeX RDF
25	Hideo Kikuchi, Takashi Yukawa, Kazumitsu Matsuzawa, Tsutomu Ishikawa	Presto: A Bus-Connected Multiprocessor for a Rete-Based Production System.	CONPAR	1990	DBLP DOI BibTeX RDF
25	K. C. Lee	A virtual bus for dynamic parallel processing.	SPDP	1990	DBLP DOI BibTeX RDF
25	Vernon Rego	A comparison of two token-passing bus protocols.	SIGCOMM	1986	DBLP DOI BibTeX RDF
25	John P. Lehoczky, Lui Sha	Performance of Real-Time Bus Scheduling Algorithms.	SIGMETRICS	1986	DBLP DOI BibTeX RDF
24	Armando Astarloa, Jesús Lázaro 0001, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez	DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus.	ICDCS Workshops	2009	DBLP DOI BibTeX RDF
24	Maged Ghoneima, Yehea I. Ismail	Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses.	ISLPED	2004	DBLP DOI BibTeX RDF	low power, interconnects, buses, coupling capacitance
22	Priyalal Kulasinghe, Ahmed El-Amawy	On the Complexity of Optimal Bused Interconnections.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	interconnection function, bus minimization, interface minimization, computational complexity, optimal design, Multiple bus system
22	Anujan Varma, Suresh Chalasani	Fault-Tolerance Analysis of One-Sided Crosspoint Switching Networks.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	one-sided crosspoint switching networks, crosspoint faults, multiple-bus interconnection networks, multiple-bus configurations, fault set, nonblocking switch matrix, fault-tolerance, fault tolerant computing, connectivity, multiprocessor interconnection networks, upper bounds, ports, rearrangeable
22	Helmar Burkhart, Roland Millen	Performance-Measurement Tools in a Multiprocessor Environment.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	synchronization traffic analysis, bus load measurements, performance-measurement tools, monitoring facilities, breakpoint monitor, mailbox monitor, bus monitor, multi-monitor mode, common programming-language interface, integrated monitoring tool, MODULA-2 multiprocessor environment, performance evaluation, user interface, user interfaces, debugging, software tools, multiprocessing systems
22	Larry D. Wittie	Communication Structures for Large Networks of Microcomputers.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	Bus topologies, dual-bus hypercubes, extensible interconnections, hypercube spanning buses, microcomputer architectures, parallel computers, distributed computers, network computers, communication structures, cube- connected-cycles
22	Subrat Kumar Panda, Arnab Roy 0001, P. P. Chakrabarti 0001, Rajeev Kumar 0004	Simulation-based verification using Temporally Attributed Boolean Logic.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Bus verification, instruction semantics verification, interrupt testing, offline-online verification algorithm, simulation based verification, temporal logic, timing verification
22	Liang Zhang 0038, John M. Wilson 0002, Rizwan Bashirullah, Lei Luo 0006, Jian Xu, Paul D. Franzon	Driver pre-emphasis techniques for on-chip global buses.	ISLPED	2005	DBLP DOI BibTeX RDF	current sensing, peak current, pre-emphasis, low-power, crosstalk, differential, on-chip bus
22	Xinping Zhu, Wei Qin, Sharad Malik	Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	on-chip communication architecture, simulator synthesis, multiprocessor system, packet-switching network, design exploration, bus, retargetable simulation
22	Claudia Kretzschmar, Robert Siegmund, Dietmar Müller 0001	Low Power Encoding Techniques for Dynamically Reconfigurable Hardware.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	transition minimizing bus encoding, low power, dynamic reconfiguration
22	Makoto Sugihara, Hiroto Yasuura	Optimization of Test Accesses with a Combined BIST and External Test Scheme.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	external test, CBET, test access, external pins, BIST, test scheduling, test time, test bus
22	Yasuyuki Mimatsu, Haruo Yokota	A performance comparison between the DR-net and a hierarchical RAID system.	PRDC	2000	DBLP DOI BibTeX RDF	disc drives, DR-net, hierarchical RAID system, disk array systems, multiple disk drives, centralized controller, communication path, controller functions, bus setup time, parity calculation load, performance evaluation, scalability, digital simulation, system performance, RAID, performance comparison, scalable architecture, hierarchical system
22	Yang Xia, Pranav Ashar	Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture.	VLSI Design	2000	DBLP DOI BibTeX RDF	Combinational Loop, Model Checking, Formal Verification, Temporal Logic, Time Division Multiplexing, Token Ring, Computational Tree Logic, Bus Protocol
22	Chun Xia, Josep Torrellas	Improving the Data Cache Performance of Multiprocessor Operating Systems.	HPCA	1996	DBLP DOI BibTeX RDF	data cache performance, operating system effect on caches, bus-based multiprocessor, address trace evaluation, block operations, latency hiding
22	Po-Ching Hsu, Sying-Jyan Wang	Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	multiple-board system, bus emulator, wiring interconnect, testing, fault detection, diagnosis, microprocessor, printed circuit board, printed circuit testing, hierarchical testing
22	L. Bisone, A. Scianna	A CAD multiprocessor system for advanced real-time process applications.	PDP	1995	DBLP DOI BibTeX RDF	CAD multiprocessor system, advanced real-time process applications, control diagrams, synoptic pages, control station, symbol editors, parallel VME bus, Field Instrumentation Protocol, real control loops, parallel simulator signals, complex parallel real time architecture, real-time systems, networking, protocols, parallel system, client-server systems, distributed control, trends, automation system, power generation, control system CAD
22	Murali Kadiyala, Laxmi N. Bhuyan	A dynamic cache sub-block design to reduce false sharing.	ICCD	1995	DBLP DOI BibTeX RDF	dynamic cache sub-block design, bus traffic, dynamic sub-block coherence protocol, simulation results, memory architecture, cache storage, false sharing, memory protocols