Search results for "VLSI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
30	Abhijit M. Lele, S. K. Nandy 0001	Architecture of Reconfigurable a Low Power Gigabit AT Switch.	VLSI Design	2001	DBLP DOI BibTeX RDF
30	Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura	Scaling Up Of Wave Pipelines.	VLSI Design	2001	DBLP DOI BibTeX RDF
30	Gary L. Dare, Charles A. Zukowski	Accuracy management for mixed-mode digital VLSI simulation.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
30	Arun K. Majumdar, Nirav Patel	Design of an ASIC for Straight Line Detection in an Image.	VLSI Design	2000	DBLP DOI BibTeX RDF	Hough Transform, CORDIC, ASIC Design
30	Kolin Paul, Dipanwita Roy Chowdhury	Application of GF(2p) CA in Burst Error Correcting Codes.	VLSI Design	2000	DBLP DOI BibTeX RDF
30	Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta 0001	Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits.	VLSI Design	2000	DBLP DOI BibTeX RDF
30	Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta 0001	An ASIC for Cellular Automata Based Message Authentication.	VLSI Design	2000	DBLP DOI BibTeX RDF
30	Mayukh Bhattacharya, Pinaki Mazumder	Convergence Issues in Resonant Tunneling Diode Circuit Simulation.	VLSI Design	2000	DBLP DOI BibTeX RDF	negative differential resistance, convergence, SPICE, circuit simulation, resonant tunneling diode, Newton-Raphson
30	Russell E. Henning, Chaitali Chakrabarti	Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design.	VLSI Design	2000	DBLP DOI BibTeX RDF	statistical parameters, high-level synthesis, Low power design, data models, transition activity
30	Juha Plosila, Tiberiu Seceleanu	Design of Synchronous Action Systems.	VLSI Design	2000	DBLP DOI BibTeX RDF
30	Shiyou Zhao, Kaushik Roy 0001	Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits.	VLSI Design	2000	DBLP DOI BibTeX RDF	switching noise, Ldi/dt noise, maximum switching current, IR voltage drop
30	Ninglong Lu, Ibrahim N. Hajj	An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
30	Michael T. Niemier, Peter M. Kogge	Logic in Wire: Using Quantum Dots to Implement a Microprocessor.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
30	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	test vector ordering, test, low power, switching activity
30	Stefan Hendricx, Luc J. M. Claesen	Symbolic Multi-Level Verification of Refinement.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
30	Jacob Augustine, William E. Lynch, Yuke Wang, Asim J. Al-Khalili	Lossy Compression of Images Using Logic Minimization.	VLSI Design	1999	DBLP DOI BibTeX RDF
30	Bedabrata Pain, Guang Yang 0003, Brita Olson, Timothy Shaw, Monico Ortiz, Julie Heynssens, Chris Wrigley, Charlie Ho	A Low-Power Digital Camera-on-a-Chip Implemented in CMOS Active Pixel Approach.	VLSI Design	1999	DBLP DOI BibTeX RDF
30	Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag	Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures.	VLSI Design	1999	DBLP DOI BibTeX RDF
30	Ashutosh Kulkarni, Navin Chander, Soumya Pillai, Lizy Kurian John	Modeling and Analysis of The Difference-Bit Cache.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	hit access time, cache mapping strategies*, Cache memory, critical path
30	Sudhakar Bobba, Ibrahim N. Hajj	Maximum Current Estimation in Programmable Logic Arrays.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	maximum current, PLA
30	I. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis	Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	voltage-mode latches, voltage-mode master-slave, true-single phase clocked-logic, Multiple-Valued Logic
30	Carlo Samori, Andrea L. Lacaita, Alfio Zanchi, P. Vita	Design Issues of LC Tuned Oscillators for Integrated Transceivers.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	RF integrated circuits, voltage controlled oscillators
30	Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. Ayoubi	Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	non-refreshing static storage, on-chip learning neural networks, analog learning
30	Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González	Circuit Design using Resonant Tunneling Diodes.	VLSI Design	1998	DBLP DOI BibTeX RDF	Quantum device, Pipelining, Multiple-Valued Logic, Nanoelectronics, Resonant Tunneling Diode
30	C. S. Raghu, S. Sundaram	Distributed Logic Simulation Algorithm using Preemption of Inconsistent Events.	VLSI Design	1998	DBLP DOI BibTeX RDF	parallel/distributed simulation, conservative logic simulation algorithm, discrete event simulation, Logic simulation
30	S. Balajee, Ananta K. Majhi	Automated AC (Timing) Characterization for Digital Circuit Testing.	VLSI Design	1998	DBLP DOI BibTeX RDF	Timing Characterization, STIL, Setup and Hold Time
30	S. Srivastava, S. C. Bose, B. P. Mathur, Arti Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, Arindam Karmakar, Chandra Shekhar 0001, Sudhir Kumar, Amit K. Agarwal	Evolution of Architectural Concepts and Design Methods of Microprocessors.	VLSI Design	1998	DBLP DOI BibTeX RDF	Microprocessor Evolution, Synthesis, VHDL, Microprocessor Design
30	Priya Patil, Tan-Li Chou, Kaushik Roy 0001, Rabindra Roy	Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique.	VLSI Design	1997	DBLP DOI BibTeX RDF
30	Eshwar Belani, Ravi Mittal	A General Reconfiguration Technique for Fault Tolerant Processor Architectures.	VLSI Design	1997	DBLP DOI BibTeX RDF
30	R. V. Raj, N. S. Murty, P. S. Nagendra Rao, Lalit M. Patnaik	Effective Heuristics for Timing Driven Constructive Placement.	VLSI Design	1997	DBLP DOI BibTeX RDF
30	Saeid Nooshabadi, Juan A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhuri	Micropipeline Architecture for Multiplier-less FIR Filters.	VLSI Design	1997	DBLP DOI BibTeX RDF
30	Ashley Rasquinha, N. Ranganathan	C3L: A Chip for Connected Component Labeling.	VLSI Design	1997	DBLP DOI BibTeX RDF
30	Gagan Hasteer, Prithviraj Banerjee	Simulated Annealing Based Parallel State Assignment of Finite State Machines.	VLSI Design	1997	DBLP DOI BibTeX RDF
30	Jin-Tai Yan	An Optimal ILP Formulation for Minimixing the Number of Feedthrough Cells in Standard Cell Placement.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
30	Enrico Macii, Massimo Poncino	Exact Computation of the Entropy of a Logic Circuit.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
30	Luc Desormeaux, Valek Szwarc, John H. Lodge	A High-Speed, Real-to-Quadrature Converter with Filtering and Decimation.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
30	Mario Alberto López, Dinesh P. Mehta	Partitioning Algorithms for Corner Stitching.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
30	Arun Balakrishnan, Srimat T. Chakradhar	Sequential Circuits with combinational Test Generation Complexity.	VLSI Design	1996	DBLP DOI BibTeX RDF
30	Ashutosh Singla, Thomas M. Conte	Bipartitioning for Hybrid FPGA-Software Simulatio.	VLSI Design	1996	DBLP DOI BibTeX RDF
30	C. P. Ravikumar, Rajamani Rajarajan	Genetic Algorithms for Scan Path Design.	VLSI Design	1996	DBLP DOI BibTeX RDF
30	Jatan C. Shah, Sachin S. Sapatnekar	Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs.	VLSI Design	1996	DBLP DOI BibTeX RDF	power-delay tradeoffs, dynamic programming, Interconnect, sensitivity, buffer, sizing, repeaters, drivers
30	Natesan Venkateswaran, Dinesh Bhatia	Clock-Skew Constrained Cell Placement.	VLSI Design	1996	DBLP DOI BibTeX RDF
30	Jin-Tai Yan	An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell Placement.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF
30	Alexandre R. S. Romariz, P. U. A. Ferreira, J. V. Campêlo Jr., Marcio L. Graciano Jr., José C. da Costa	Design of a Hybrid Digital-Analog Neural Co-Processor for Signal Processing.	EUROMICRO	1996	DBLP DOI BibTeX RDF	hybrid digital-analog neural co-processor, digitally-controlled multiplexing, CMOS analog circuits, VLSI, signal processing, VLSI design, multilayer perceptrons, VLSI implementation, hybrid architecture, capacitors, analog multipliers
29	Yongji Jiang, Garrett S. Rose	A dual-MOSFET equivalent resistor thermal sensor.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	integrated circuits, dynamic thermal management, vlsi, temperature sensors
29	Ivan D. Castellanos, James E. Stine	Compressor trees for decimal partial product reduction.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	VLSI, decimal arithmetic
29	Vijay Nagarajan, Stefan Laendner, Nikhil Jayakumar, Olgica Milenkovic, Sunil P. Khatri	High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	code construction, fully-parallel VLSI implementation, network of PLAs, iterative decoding, low-density parity-check codes
29	C. Hess, Markus Wenk, Andreas Burg, Peter Luethi, Christoph Studer, Norbert Felber, Wolfgang Fichtner	Reduced-complexity mimo detector with close-to ml error rate performance.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FSD, VLSI, MIMO, sphere decoding
29	Zhan Guo, Peter Nilsson 0001	A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	square root algorithm, VLSI, wireless LAN, ASIC, MIMO, fixed-point, 3G, HSDPA, CORDIC, BLAST
29	Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen	VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	shape-adaptive, boundary extension, discrete wavelet transform, VLSI architecture
29	Wonyong Sung, Youngho Ahn, Eunjoo Hwang	VLSI Implementation of An Adaptive Equalizer for ATSC Digital TV Receivers.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	adaptive equalizer, HDTV receiver, VSB modulation, VLSI implementation
29	Shyamkumar Thoziyoor, Jay B. Brockman, Daniel Rinzler	PIM lite: a multithreaded processor-in-memory prototype.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	multithreading, VLSI design, processing-in-memory
29	Bo-Sung Kim, Jun Dong Cho	Maximizing memory data reuse for lower power motion estimation.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF	low power VLSI, motion estimation, MPEG-2
29	Peter M. Kuhn	Fast MPEG-4 Motion Estimation: Processor Based and Flexible VLSI Implementations.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF	algorithm, VLSI, motion estimation, MPEG-4, processor, complexity analysis
29	Roderick McConnell, Dominique Lavenier	Prototyping of VLSI components from a formal specification.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF	Synchronous Data Flow, Formal Specification, VLSI
29	John A. Canaris	A VLSI architecture for the real time computation of discrete trigonometric transforms.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF	discrete trigonometric transforms, Goertzel's algorithm, Discrete cosine transform, VLSI architecture
29	Sy-Yen Kuo, Kuochen Wang	Fault diagnosis in reconfigurable VLSI and WSI processor arrays.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF	design for diagnosability, VLSI/WSI processor array, fault diagnosis, reconfiguration, yield enhancement
27	Ulrich Schmid 0001	Keynote: Distributed Algorithms and VLSI.	SSS	2008	DBLP DOI BibTeX RDF
27	Chih-Cheng Lu, C. C. Li, Hsin Chen	How Robust Is a Probabilistic Neural VLSI System Against Environmental Noise.	ANNPR	2008	DBLP DOI BibTeX RDF
27	Maolin Tang, Xin Yao 0001	A Memetic Algorithm for VLSI Floorplanning.	IEEE Trans. Syst. Man Cybern. Part B	2007	DBLP DOI BibTeX RDF
27	Giacomo Indiveri, Stefano Fusi	Spike-based learning in VLSI networks of integrate-and-fire neurons.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Korrai Deergha Rao, Ch. Gangadhar	VLSI Realization of Adaptive Equalizers of SIMO FIR Second Order Volterra Channels.	APCCAS	2006	DBLP DOI BibTeX RDF
27	Wu Jigang, Thambipillai Srikanthan, Heiko Schröder	Efficient reconfigurable techniques for VLSI arrays with 6-port switches.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
27	Amardeep Singh, Lalit M. Bharadwaj, Singh Harpreet	DNA and quantum based algorithms for VLSI circuits testing.	Nat. Comput.	2005	DBLP DOI BibTeX RDF	DNA algorithm, genetic algorithms, neural networks, ATPG, quantum computation, quantum algorithm
27	Chuan-Yu Cho, Shiang-Yang Huang, Jeng-Neng Hwang, Jia-Shung Wang	An embedded merging scheme for VLSI implementation of H.264/AVC motion estimation modules.	ICIP (3)	2005	DBLP DOI BibTeX RDF
27	Jin Jie, Chi-Ying Tsui, Wai Ho Mow	A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
27	Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji	General iterative heuristics for VLSI multiobjective partitioning.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
27	Hideki Yamauchi, Yoshinori Takeuchi, Masaharu Imai	VLSI Implementation of Fractal Image Compression Processor for Moving Pictures.	EUROMICRO	2001	DBLP DOI BibTeX RDF
27	Mario Alberto López, Ravi Janardan, Sartaj K. Sahni	Efficient net extraction for restricted orientation designs [VLSI layout].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
27	Ramesh Karri, Karin Högstedt, Alex Orailoglu	Computer-Aided Design of Fault-Tolerant VLSI Systems.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF	Fault-Tolerance, CAD, High Level Synthesis
27	Wai-Chi Fang, Chi-Yung Chang, Bing J. Sheu, Oscal T.-C. Chen, John C. Curlander	VLSI systolic binary tree-searched vector quantizer for image compression.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
27	Juin-Yeu Lu, Shiu-Kai Chin	Linking HOL to a VLSI CAD System.	HUG	1993	DBLP DOI BibTeX RDF
27	Marián Vajtersic	A VLSI Multigrid Poisson Solver Amenable to Biharmonic Equation.	CONPAR	1992	DBLP DOI BibTeX RDF
27	Anthony F. Hutchings, Richard J. Bonneau, William M. Fisher	Integrated VLSI CAD systems at Digital Equipment Corporation.	DAC	1985	DBLP DOI BibTeX RDF
27	Dave Johnson 0001, Dave Budde, Dave Carson, Craig Peterson	Intel iAPX 432: VLSI building blocks for a fault-tolerant computer.	AFIPS National Computer Conference	1983	DBLP DOI BibTeX RDF
27	Kemal Oflazer	A reconfigurable VLSI architecture for a database processor.	AFIPS National Computer Conference	1983	DBLP DOI BibTeX RDF
27	Qi Huang, Xiaoping Chen, Bingfeng Wang, Ronghai Cai, Kaiyu Qin	The Concept of Computing on Chip (CoC) for Electric Power System Application.	PARELEC	2006	DBLP DOI BibTeX RDF	CoC, VLSI, SOC, Power System, Transient Simulation
27	Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan	Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System.	ISVLSI	2006	DBLP DOI BibTeX RDF
27	Markus Ferringer, Gottfried Fuchs, Andreas Steininger, Gerald Kempf	VLSI Implementation of a Fault-Tolerant Distributed Clock Generation.	DFT	2006	DBLP DOI BibTeX RDF
27	Hasan Arslan, Shantanu Dutt	A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits.	ICCD	2004	DBLP DOI BibTeX RDF
27	Atul Maheshwari, Israel Koren, Wayne P. Burleson	Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits.	DFT	2003	DBLP DOI BibTeX RDF
27	Robert W. Brodersen	System-on-a-Chip VLSI - Is It Finally Really Here?	ARVLSI	1999	DBLP DOI BibTeX RDF
27	Timothy K. Horiuchi, Ernst Niebur	Conjunction Search Using a 1-D, Analog VLSI-based, Attentional Search/Tracking Chip.	ARVLSI	1999	DBLP DOI BibTeX RDF
27	Stephen P. DeWeerth, Girish N. Patel, Mario F. Simoni, David E. Schimmel, Ronald L. Calabrese	A VLSI Architecture for Modeling Intersegmental Coordination.	ARVLSI	1997	DBLP DOI BibTeX RDF
27	Jenq-Neng Hwang, Sun-Yuan Kung	Parallel algorithms/architectures for neural networks.	J. VLSI Signal Process.	1989	DBLP DOI BibTeX RDF
26	Giacomo Indiveri, Elisabetta Chicca, Rodney J. Douglas	Artificial Cognitive Systems: From VLSI Networks of Spiking Neurons to Neuromorphic Cognition.	Cogn. Comput.	2009	DBLP DOI BibTeX RDF	Neuromorphic engineering, Spike-based learning, Winner-take-all, Soft WTA, VLSI, Cognition
26	Fong-Ming Shyu, Po-Hsun Cheng, Sao-Jie Chen	Using XML for VLSI Physical Design Automation.	ICA3PP	2009	DBLP DOI BibTeX RDF	VLSI Physical Design, Web Service, XML, Parallel Architecture, Object-Oriented Architecture
26	Hannu Olkkonen, Juuso T. Olkkonen	Simplified biorthogonal discrete wavelet transform for VLSI architecture design.	Signal Image Video Process.	2008	DBLP DOI BibTeX RDF	Biorthogonal discrete wavelet transform, VLSI, Lifting scheme
26	Saeedeh Bakhshi, Hamid Sarbazi-Azad	Efficient VLSI Layout of Edge Product Networks.	DELTA	2008	DBLP DOI BibTeX RDF	Edge graph product, Collinear layout, Interconnection networks, Networks on chip, VLSI layout
26	Debasri Saha, Susmita Sur-Kolay	Fast Robust Intellectual Property Protection for VLSI Physical Design.	ICIT	2007	DBLP DOI BibTeX RDF	fingerprint- ing, VLSI physical design, watermarking, Intellectual property, electronic design automation
26	Chien-Min Ou, Huang-Chun Roan, Wen-Jyi Hwang	Fractional Full-Search Motion Estimation VLSI Architecture for H.264/AVC.	PSIVT	2006	DBLP DOI BibTeX RDF	Fractional motion estimation, H.264 standard, Video coding, VLSI architecture
26	Dian Zhou, Ruiming Li	Design and Verification of High-Speed VLSI Physical Design.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	floorplanning and placement, order reduction, parameter extraction, VLSI, delay, interconnect, power, physical design, buffer insertion, power grid, clock distribution, wire sizing
26	Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia	A semi-persistent clustering technique for VLSI circuit placement.	ISPD	2005	DBLP DOI BibTeX RDF	VLSI placement, physical design, hypergraph clustering
26	David H. Goldberg, Andreas G. Andreou, Pedro Julián, Philippe O. Pouliquen, Laurence Riddle, Rich Rosasco	A wake-up detector for an acoustic surveillance sensor network: algorithm and VLSI implementation.	IPSN	2004	DBLP DOI BibTeX RDF	acoustic surveillance, wake-up detection, sensor networks, power management, maximum likelihood estimation, periodicity, VLSI implementation
26	Wu Jigang, Thambipillai Srikanthan	Finding High Performance Solution in Reconfigurable Mesh-Connected VLSI Arrays.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF	Degradable VLSI array, fault-tolerance, reconfiguration, NP-completeness, heuristic algorithm
26	Wu Jigang, Thambipillai Srikanthan	On the Reconfiguration Algorithm for Fault-Tolerant VLSI Arrays.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF	degradable VLSI array, fault-tolerance, reconfiguration, NP-completeness, greedy algorithm
26	Chih-Wen Lu, Chung-Len Lee 0001, Chauchin Su, Jwu-E Chen	Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	VLSI, IDDQ testing, deep sub-micron
26	Parthasarathi Dasgupta, Peichen Pan, Subhas C. Nandy, Bhargab B. Bhattacharya	Monotone bipartitioning problem in a planar point set with applications to VLSI.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Complexity of algorithms, routing, very large scale integration (VLSI), partitioning, floorplanning
26	Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi 0001	Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI.	ISMVL	2002	DBLP DOI BibTeX RDF	new paradigm computing, high-speed signaling, code-division multiple access, equalization, VLSI systems
26	Chor Ping Low	An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Degradable VLSI/WSI arrays, efficient heuristic, NP-completeness, greedy algorithm