Search results for "design-for-testability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Ming Zhang 0017, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel	Sequential Element Design With Built-In Soft Error Resilience.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
10	Subhasish Mitra, Norbert Seifert, Ming Zhang 0017, Quan Shi, Kee Sup Kim	Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim.	Computer	2005	DBLP DOI BibTeX RDF
10	Mohsen Nahvi, André Ivanov	Indirect test architecture for SoC testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
10	Erik Jan Marinissen	Security vs. Test Quality: Can We Really Only Have One at a Time?	ITC	2004	DBLP DOI BibTeX RDF
10	Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita	On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure.	DELTA	2004	DBLP DOI BibTeX RDF
10	Jin-Fu Li 0001, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin	A Hierarchical Test Scheme for System-On-Chip Designs.	DATE	2002	DBLP DOI BibTeX RDF
10	Benoit Baudry, Yves Le Traon, Gerson Sunyé, Jean-Marc Jézéquel	Towards a 'Safe' Use of Design Patterns to Improve OO Software Testability.	ISSRE	2001	DBLP DOI BibTeX RDF
10	Jacob Savir	Distributed BIST Architecture to Combat Delay Faults.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	BIST, LFSR, delay test, MISR, LSSD, SRL
10	Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer	A Design For Test Perspective on I/O Management.	ICCD	1996	DBLP DOI BibTeX RDF	I/O pads, High Level Synthesis, Design For Test, Boundary Scan
10	Arun Balakrishnan, Srimat T. Chakradhar	Sequential Circuits with combinational Test Generation Complexity.	VLSI Design	1996	DBLP DOI BibTeX RDF
10	Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu	A practical current sensing technique for IDDQ testing.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
10	Hakim Bederr, Michael Nicolaidis, Alain Guyot	Analytic approach for error masking elimination in on-line multipliers.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	error masking elimination, online multipliers, high precision numbers, scan design approach, internal state observability, DFT approach, sequential circuits, digital arithmetic, fault coverage, multiplying circuits, area overhead
10	I. D. Dear, Chryssa Dislis, Anthony P. Ambler, J. H. Dick	Economic Effects in Design and Test.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
9	Shibaji Banerjee, Debdeep Mukhopadhyay, C. V. G. Rao, Dipanwita Roy Chowdhury	An integrated DFT solution for mixed-signal SOCs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
9	Josef Strnadel, Zdenek Kotásek	SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System.	ECBS	2006	DBLP DOI BibTeX RDF
9	Petr Fiser, Hana Kubátová	Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications.	DSD	2006	DBLP DOI BibTeX RDF
9	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy 0001	A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.	DATE	2005	DBLP DOI BibTeX RDF
9	Yu-Ting Lin, Tony Ambler	An Economic Selecting Model for DFT Strategies.	VTS	2005	DBLP DOI BibTeX RDF
9	Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu	Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing.	ITC	2004	DBLP DOI BibTeX RDF
9	Yuejian Wu, Paul N. MacDonald	Testing ASICs with multiple identical cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
9	Andrzej Rucinski 0002, Barrett Stetson, S. T. P. Brundavani	A DOT1 & DOT4 MOSIS - Compatible Library.	MSE	2003	DBLP DOI BibTeX RDF
9	Kaamran Raahemifar, Majid Ahmadi	A new initialization technique for asynchronous circuits.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
9	Dong Xiang, Hideo Fujiwara	Handling the pin overhead problem of DFTs for high-quality and at-speed tests.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
9	Nahmsuk Oh, Rohit Kapur, Thomas W. Williams	Fast seed computation for reseeding shift register in test pattern compression.	ICCAD	2002	DBLP DOI BibTeX RDF
9	Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey	Embedded software-based self-testing for SoC design.	DAC	2002	DBLP DOI BibTeX RDF	functional test, SoC test, VLSI test, microprocessor test
9	José Vicente Calvano, Antonio Carneiro de Mesquita Filho, Vladimir Castro Alves, Marcelo Lubaszewski	Fault Models and Test Generation for OpAmp Circuits - The FFM.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	test generation, fault model, analog test, operational amplifiers
9	Jay Bedsole, Rajesh Raina, Al Crouch, Magdy S. Abadir	Very Low Cost Testers: Opportunities and Challenges.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
9	Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara	Testable Design of Sequential Circuits with Improved Fault Efficiency.	VLSI Design	2001	DBLP DOI BibTeX RDF
9	Alessandro Bogliolo, Michele Favalli, Maurizio Damiani	Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
9	Yervant Zorian, Michael Nicolaidis, Peter Muhmenthaler, David Y. Lepejian, Chris W. H. Strolenberg, Kees Veelenturf	Tutorial Statement.	DATE	2000	DBLP DOI BibTeX RDF
9	Marina Santo Zarnik, Franc Novak, Srecko Macek	Design for Test of Crystal Oscillators: A Case Study.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	crystal oscillators, fault diagnosis, analog circuits, design-for-test
9	Thomas E. Marchok, Wojciech Maly	Modeling the Difficulty of Sequential Automatic Test Pattern Generation.	ICCD	1996	DBLP DOI BibTeX RDF
9	Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel	An observability enhancement approach for improved testability and at-speed test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
9	Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda	The Use of Model Checking in ATPG for Sequential Circuits.	CAV	1990	DBLP DOI BibTeX RDF
9	Paolo Camurati, Paolo Gianoglio, Renato Gianoglio, Paolo Prinetto	ESTA: an expert system for DFT rule verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
8	Scott Davidson 0001	A second course on testing [review of System on Chip Test Architectures (Wang, L.-T et al., Eds.; 2007)].	IEEE Des. Test Comput.	2009	DBLP DOI BibTeX RDF
8	Lyl M. Ciganda, Francesco Abate, Paolo Bernardi, M. Bruno, Matteo Sonza Reorda	An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs.	DDECS	2009	DBLP DOI BibTeX RDF
8	Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu	Controllability of Static CMOS Circuits for Timing Characterization.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Design for test, Delay fault testing, Scan design
8	Newton Lee	A word from the editor.	Comput. Entertain.	2008	DBLP DOI BibTeX RDF
8		Keith Baker's presentation: November 17, 2007.	Comput. Entertain.	2008	DBLP DOI BibTeX RDF
8	Po-Han Wu, Tsung-Tang Chen, Wei-Lin Li, Jiann-Chyi Rau	An efficient test-data compaction for low power VLSI testing.	EIT	2008	DBLP DOI BibTeX RDF
8	Masood ul-Hasan, Yichuang Sun, Xi Zhu 0001, James Moritz	Oscillation-based DFT for second-order OTA-C filters.	ISCAS	2008	DBLP DOI BibTeX RDF
8	Fei Wang, Yu Hu 0001, Xiaowei Li 0001	Adaptive Diagnostic Pattern Generation for Scan Chains.	DELTA	2008	DBLP DOI BibTeX RDF	very large scale integration (VLSI), testing, diagnosis, Boolean satisfiability, scan chain
8	Erkan Acar, Sule Ozev	Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
8	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	A System-layer Infrastructure for SoC Diagnosis.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	SoC diagnosis, Processor and UDL logic self-testing, Memory, Infrastructure-IP
8	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.	VLSI Design	2007	DBLP DOI BibTeX RDF
8	Kentaroh Katoh, Hideo Ito	Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices.	ETS	2006	DBLP DOI BibTeX RDF	Coarse Grained Dynamically Reconfigurable Devices, DRP, BIST(Built-In Self Test), PE, DFT
8	Kun Young Chung, Sandeep K. Gupta 0001	Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing.	VTS	2006	DBLP DOI BibTeX RDF
8	Hari Vijay Venkatanarayanan, Michael L. Bushnell	An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip.	VLSI Design	2006	DBLP DOI BibTeX RDF
8	Masood ul-Hasan, Yichuang Sun	Oscillation-based Test Method for Continuous-time OTA-C Filters.	APCCAS	2006	DBLP DOI BibTeX RDF
8	Xiaoming Yu, Miron Abramovici	Sequential circuit ATPG using combinational algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
8	Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov	An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform.	DSD	2005	DBLP DOI BibTeX RDF
8	Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen	Flash Memory Die Sort by a Sample Classification Method.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	die sort, test flow, wafer probe, flash memory, memory testing
8	Min-Hao Chiu, Chien-Mo James Li	Jump Scan: A DFT Technique for Low Power Testing.	VTS	2005	DBLP DOI BibTeX RDF
8	Michele Favalli, Cecilia Metra	TMR voting in the presence of crosstalk faults at the voter inputs.	IEEE Trans. Reliab.	2004	DBLP DOI BibTeX RDF
8	Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu	On Test and Diagnostics of Flash Memories.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
8	Hao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng	A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
8	Jin-Fu Li 0001, Chih-Chiang Hsu	Efficient Test Methodologies for Conditional Sum Adders.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
8	Sule Ozev, Christian Olgaard	Wafer-level RF Test and DfT for VCO Modulating Transceiver Architecures.	VTS	2004	DBLP DOI BibTeX RDF
8	Rodger Schuttert, D. C. L. (Erik) van Geest, A. Kumar	On-Chip Mixed-Signal Test Structures Re-used for Board Test.	ITC	2004	DBLP DOI BibTeX RDF
8	Shyue-Kung Lu, Chien-Hung Yeh, Han-Wen Lin	Efficient Built-in Self-Test Techniques for Memory-Based FFT Processors.	PRDC	2004	DBLP DOI BibTeX RDF
8	Muhammad Nummer, Manoj Sachdev	A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	high-performance testing, controlled-delay flip-flop, built-in self test, delay-fault testing, design for delay testability
8	Sunwoong Yang, MoonJoon Kim, JaeHeung Park, Hoon Chang	A Study on Insuring the Full Reliability of Finite State Machine.	ICCSA (2)	2003	DBLP DOI BibTeX RDF
8	Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian	A Test Interface for Built-In Test of Non-Isolated Scanned Cores.	VTS	2003	DBLP DOI BibTeX RDF
8	Kun Young Chung, Sandeep K. Gupta 0001	Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing.	ITC	2003	DBLP DOI BibTeX RDF
8	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	High-level test compaction techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
8	Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara	Design for Two-Pattern Testability of Controller-Data Path Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
8	Chee-Kian Ong, Kwang-Ting (Tim) Cheng	Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus.	VTS	2002	DBLP DOI BibTeX RDF
8	Hideyuki Ichihara, Tomoo Inoue	Generating Small Test Sets for Test Compression/Decompression Scheme Using Statistical Coding.	DELTA	2002	DBLP DOI BibTeX RDF	statistical code, test generation, ATE, test compression, test compaction
8	Irith Pomeranz, Y. Zonan	Testing of scan circuits containing nonisolated random-logic legacycores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
8	Antonio Zenteno, Víctor H. Champac, Joan Figueras	Detectability Conditions of Full Opens in the Interconnections.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	logic testing, IDDQ testing, opens, defect modeling
8	Muhammad Nummer, Manoj Sachdev	A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency.	VTS	2001	DBLP DOI BibTeX RDF	high-performance testing, controlled-delay flip-flop, built-in self test, Delay-fault testing, design for delay testability
8	Antonio Zenteno, Víctor H. Champac	Resistive Opens in a Class of CMOS Latches: Analysis and DFT.	VTS	2001	DBLP DOI BibTeX RDF
8	Franco Fummi, Donatella Sciuto	A Hierarchical Test Generation Approach for Large Controllers.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	hierarchical FSM, sequential circuits, automatic test pattern generation, Functional testing, functional fault model
8	Luis Basto	First Results of ITC'99 Benchmark Circuits.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
8	Ralph Mason, Shing Ma	Mixed Signal DFT at GHz Frequencies.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF
8	Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott	Fault Models and Tests for a 2-Bit-per-Cell MLDRAM.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
8	Andreas Lechner, J. Ferguson, Andrew Richardson 0001, B. Hermes	A Digital Partial Built-In Self-Test for a High Performance Automatic Gain Control Circuit .	DATE	1999	DBLP DOI BibTeX RDF
8	Kaamran Raahemifar, Majid Ahmadi	On-line IDDQ fault testing for CMOS/BiCMOS logic families.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
8	R. Scott Fetherston, Imtiaz P. Shaik, Siyad C. Ma	Testability Features of the AMD-K6 Microprocessor.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
8	José M. Miranda	A BIST and Boundary-Scan Economics Framework.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
8	Yoshinobu Higami, Kozo Kinoshita	Design of partially parallel scan chain.	ED&TC	1997	DBLP DOI BibTeX RDF
8	Hassan Ihs, Christian Dufaza	Test synthesis for DC test of switched-capacitors circuits.	ED&TC	1997	DBLP DOI BibTeX RDF
8	Karim Arabi, Bozena Kaminska	Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology.	VTS	1997	DBLP DOI BibTeX RDF	Oscillation-Test Method, Parametric Fault Coverage, Analog Testing, Mixed-Signal Circuits
8	Richard M. Sedmak, John S. Evans	Spanning the Product Life Cycle: RASSP DFT.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
8	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
8	Roberto Bevacqua, Luca Guerrazzi, Fabrizio Ferrandi, Franco Fummi	Implicit Test Sequences Compaction for Decreasing Test Application Cos.	ICCD	1996	DBLP DOI BibTeX RDF
8	Michel Renovell, P. Huc, Yves Bertrand	Bridging fault coverage improvement by power supply control.	VTS	1996	DBLP DOI BibTeX RDF	bridging fault coverage, power supply control, resistance interval, faulty value, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, logic circuits, parametric model, benchmark circuits
8	Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu	C-testable design techniques for iterative logic arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
8	Kewal K. Saluja	On-chip testing of random access memories.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	BIST RAM, reconfigured random access memories, test parallelism, Built-In Self-Test, pattern sensitive faults, test architectures, RAM testing
8	Steve Vinoski	RISE++: A Symbolic Environment for Scan-Based Testing.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
8	Bernhard Eschermann, Hans-Joachim Wunderlich	Optimized synthesis techniques for testable sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
8	Rajiv Gupta 0002, Rajagopalan Srinivasan, Melvin A. Breuer	Reorganizing Circuits to Aid Testability.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
8	Peter D. Hortensius, Robert D. McLeod, Werner Pries, D. Michael Miller, Howard C. Card	Cellular automata-based pseudorandom number generators for built-in self-test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
8	Sudipta Bhawmik, Parimal Pal Chaudhuri	DFTEXPERT: An Expert System for Design of Testable VLSI Circuits.	IEA/AIE (Vol. 1)	1988	DBLP DOI BibTeX RDF
8	S. Koeppe	Optimal Layout to Avoid CMOS Stuck-Open Faults.	DAC	1987	DBLP DOI BibTeX RDF
8	Helmut K. Berg, Prakash Rao, Bruce D. Shriver	Firmware quality assurance.	AFIPS National Computer Conference	1982	DBLP DOI BibTeX RDF