Search results for "memories"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Luca Larcher, Paolo Pavan, Alfonso Maurelli	Flash Memories for SoC: An Overview on System Constraints and Technology Issues, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
16	Petru Cascaval, Stuart Bennett, Corneliu Hutanu	Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	fault simulation, memory testing, march test, coupling faults, functional faults
16	S. T. Wang, H. J. Lu	On new fuzzy morphological associative memories.	IEEE Trans. Fuzzy Syst.	2004	DBLP DOI BibTeX RDF
16	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Efficient Modeling of Embedded Memories in Bounded Model Checking.	CAV	2004	DBLP DOI BibTeX RDF
16	David Elléouet, Nathalie Julien, Dominique Houzet, Jean-Gabriel Cousin, Eric Martin 0001	Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA.	DSD	2004	DBLP DOI BibTeX RDF
16	Kae-Jiun Mo, Shao-Sheng Yang, Tsin-Yuan Chang	Timing measurement unit with multi-stage TVC for embedded memories.	ASP-DAC	2004	DBLP DOI BibTeX RDF
16	Bohdana Ratitch, Doina Precup	Sparse Distributed Memories for On-Line Value-Based Reinforcement Learning.	ECML	2004	DBLP DOI BibTeX RDF
16	Yervant Zorian	Investment vs. Yield Relationship for Memories in SOC.	ITC	2004	DBLP DOI BibTeX RDF
16	Karl Thaller, Andreas Steininger	A transparent online memory test for simultaneous detection of functional faults and soft errors in memories.	IEEE Trans. Reliab.	2003	DBLP DOI BibTeX RDF
16	Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu	Testing and Diagnosis Methodologies for Embedded Content Addressable Memories.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	march test algorithm, memory diagnostics, BIST, memory testing, CAM
16	Dirk Niggemeyer, Elizabeth M. Rudnick	A data acquisition methodology for on-chip repair of embedded memories.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	column failures, on-chip repair, built-in self-test, Diagnosis, memory test, march tests, embedded memory, coupling faults
16	Manuel Graña, Josune Gallego, Francisco Javier Torrealdea, Alicia D'Anjou	On the Application of Associative Morphological Memories to Hyperspectral Image Analysis.	IWANN (2)	2003	DBLP DOI BibTeX RDF
16	Mohammad Gh. Mohammad, Kewal K. Saluja	Stress Test for Disturb Faults in Non-Volatile Memories.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
16	Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu	A Processor-Based Built-In Self-Repair Design for Embedded Memories.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
16	Antonio Martí Campoy, Sergio Sáez, Angel Perles, J. V. Busquets	Schedulability Analysis in EDF Scheduler with Cache Memories.	RTCSA	2003	DBLP DOI BibTeX RDF
16	Bai Hong Fang, Qiang Xu 0001, Nicola Nicolici	Hardware/Software Co-testing of Embedded Memories in Complex SOCs.	ICCAD	2003	DBLP DOI BibTeX RDF
16	Alvaro E. Arenas, Gareth Barrera-Sanabria	Modelling Intelligent Agents for Organisational Memories.	KES	2003	DBLP DOI BibTeX RDF	MAS-CommonKADS, Knowledge Management, Agent-Oriented Software Engineering, Organisational Memory
16	Sultan M. Al-Harbi, Sandeep K. Gupta 0001	Generating Complete and Optimal March Tests for Linked Faults in Memories.	VTS	2003	DBLP DOI BibTeX RDF
16	Olivier Caty, Ismet Bayraktaroglu, Amitava Majumdar 0002, Richard Lee, John Bell, Lisa Curhan	Instruction Based BIST for Board/System Level Test of External Memories and Internconnects.	ITC	2003	DBLP DOI BibTeX RDF
16	Vera Damazio, Pablo Dias	www.a.site.for.things-that.bring.back.memories.	DPPI	2003	DBLP DOI BibTeX RDF	social memory, emotional response, affective design, material culture
16	Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu	Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
16	Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu	Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	Hamming syndrome, memory diagnostics, data compression, built-in self-test (BIST), system-on-chip, memory testing, Huffman code, March test
16	Frank K. H. A. Dehne, Stefano Mardegan, Andrea Pietracaprina, Giuseppe Prencipe	Distribution Sweeping on Clustered Machines with Hierarchical Memories.	IPDPS	2002	DBLP DOI BibTeX RDF
16	Farzin Karimi, Fabrizio Lombardi	A Scan-Bist Environment for Testing Embedded Memories.	MTDT	2002	DBLP DOI BibTeX RDF
16	Daniele Rossi 0001, Cecilia Metra, Bruno Riccò	Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories.	MTDT	2002	DBLP DOI BibTeX RDF
16	Caroline Papaix, Jean Michel Daga	A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories.	MTDT	2002	DBLP DOI BibTeX RDF
16	Farzin Karimi, Fred J. Meyer, Fabrizio Lombardi	Random Testing of Multi-Port Static Random Access Memories.	MTDT	2002	DBLP DOI BibTeX RDF
16	Mohsen Sharifi, Behrouz Zolfaghari	An Approach to Exploiting Skewed Associative Memories in Avionics Systems.	ICPADS	2002	DBLP DOI BibTeX RDF
16	Kiyoo Itoh 0001	Low-voltage memories for power-aware systems.	ISLPED	2002	DBLP DOI BibTeX RDF	DRAM and SRAM cells, gain cells, gate-source/substrate-source back-biasing, memory-rich architectures, multi-Vr, non-volatile RAMs, on-chip voltage converters, peripheral circuits, subthreshold current, testing
16	Farzin Karimi, Fabrizio Lombardi	A Scan-Bist Environment for Testing Embedded Memories.	IOLTW	2002	DBLP DOI BibTeX RDF
16	Daniele Rossi 0001, Cecilia Metra, Bruno Riccò	Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories.	IOLTW	2002	DBLP DOI BibTeX RDF
16	Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor	Testing Static and Dynamic Faults in Random Access Memories.	VTS	2002	DBLP DOI BibTeX RDF	static faults, fault coverage, memory tests, dynamic faults, fault primitives
16	Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu	Testing and Diagnosing Embedded Content Addressable Memories.	VTS	2002	DBLP DOI BibTeX RDF
16	Tohru Ishihara, Kunihiro Asada	An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
16	Emmanuel Cecchet	Memory Mapped Networks: A New Deal for Distributed Shared Memories? The SciFS Experience.	CLUSTER	2002	DBLP DOI BibTeX RDF
16	Rochit Rajsuman	Design and Test of Large Embedded Memories: An Overview.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
16	Miroslav N. Velev, Randal E. Bryant	EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations.	CAV	2001	DBLP DOI BibTeX RDF
16	Bogdan Raducanu, Manuel Graña	On the Application of Heteroassociative Morphological Memories to Face Localization.	IWANN (2)	2001	DBLP DOI BibTeX RDF
16	Hiroyuki Aoki, Eiju Watanabe, Atsushi Nagata, Yukio Kosugi	Rotation-Invariant Image Association for Endoscopic Positional Identification Using Complex-Valued Associative Memories.	IWANN (2)	2001	DBLP DOI BibTeX RDF
16	Farzin Karimi, Fabrizio Lombardi, V. Swamy Irrinki, T. Crosby	A Parallel Approach for Testing Multi-Port Static Random Access Memories.	MTDT	2001	DBLP DOI BibTeX RDF
16	Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir	Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation.	CHARME	2001	DBLP DOI BibTeX RDF
16	Arnaud Turier, Lotfi Ben Ammar, Amara Amara	Static power consumption management in CMOS memories.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
16	Takatoshi Sakaue, Manabu Matsuzaki, Masachika Miyata	On the stability of bilayer associative memories.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
16	Michele Brucoli, Donato Cafagna, Leonarda Carnimeo	On the performance of CNNs for associative memories in robot vision systems.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
16	Farzin Karimi, Fabrizio Lombardi	Parallel Testing of Multi-port Static Random Access Memories for BIST.	DFT	2001	DBLP DOI BibTeX RDF	Memory testing, embedded memory, multi-port, parallel testing
16	Pierluigi Daglio, M. Araldi, Michele Morbarigazzi, Carlo Roma	A Fully Qualified Analog Design Flow for Non Volatile Memories Technologies.	ISQED	2001	DBLP DOI BibTeX RDF
16	Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi	Testing SRAM-Based Content Addressable Memories.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	March C algorithm, fault detection, fault modeling, memory testing, Content addressable memory
16	Kun-Jin Lin, Cheng-Wen Wu	Testing content-addressable memories using functional fault modelsand march-like algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
16	Pradip K. Jha, Nikil D. Dutt	High-level library mapping for memories.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	memory libraries, high-level synthesis, technology-mapping
16	Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham	Validating PowerPC Microprocessor Custom Memories.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
16	Hye-Yeon Kim, Jooyoung Park, Seong-Whan Lee	A New Methodology to the Design of Associative Memories Based on Cellular Neural Networks.	ICPR	2000	DBLP DOI BibTeX RDF
16	Rafael Gadea Gironés, Vicente Herrero-Bosch, Angel Sebastiá, Antonio Mocholí Salcedo	The Role of the Embedded Memories in the Implementation of Artificial Neural Networks.	FPL	2000	DBLP DOI BibTeX RDF
16	Dirk Niggemeyer, Elizabeth M. Rudnick, Michael Redeker	Diagnostic Testing of Embedded Memories Based on Output Tracing.	MTDT	2000	DBLP DOI BibTeX RDF
16	Rino Micheloni, Matteo Zammattio, Giovanni Campardo, Osama Khouri, Guido Torelli	Hierarchical Sector Biasing Organization for Flash Memories.	MTDT	2000	DBLP DOI BibTeX RDF
16	Karma Sherif, Munir Mandviwalla	Barriers to Actualizing Organizational Memories: Lessons from Industry.	HICSS	2000	DBLP DOI BibTeX RDF
16	Jooyoung Park, Hyuk Cho, Daihee Park	Design of GBSB neural associative memories using semidefinite programming.	IEEE Trans. Neural Networks	1999	DBLP DOI BibTeX RDF
16	Jarno K. Tanskanen, Jarkko Niittylahti	Parallel Memories in Video Encoding.	Data Compression Conference	1999	DBLP DOI BibTeX RDF
16	Seiichi Ozawa, K. Tsutumi, Norio Baba	Evolution of a dynamical modular neural network and its application to associative memories.	KES	1999	DBLP DOI BibTeX RDF
16	Philip P. Shirvani, Edward J. McCluskey	PADded Cache: A New Fault-Tolerance Technique for Cache Memories.	VTS	1999	DBLP DOI BibTeX RDF
16	Herman Schmit, Donald E. Thomas	Address generation for memories containing multiple arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
16	Ivo Schanstra, Dharmajaya Lukita, Ad J. van de Goor, Kees Veelenturf, Paul J. van Wijnen	Semiconductor manufacturing process monitoring using built-in self-test for embedded memories.	ITC	1998	DBLP DOI BibTeX RDF	diagnosis, BIST, fault localization, process monitoring, bitmap, RAM testing, microcode
16	Alaaeldin A. Amin, Mohamed Y. Osman, Radwan E. Abdel-Aal, Husni Al-Muhtaseb	New fault models and efficient BIST algorithms for dual-port memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
16	Pradip K. Jha, Nikil D. Dutt	Library mapping for memories.	ED&TC	1997	DBLP DOI BibTeX RDF
16	Pascal Bichebois, Pierre Mathery	Analysis of Defect to Yield Correlation on Memories: Method, Algorithms and Limits.	DFT	1997	DBLP DOI BibTeX RDF	algorithm, tool, correlation, method, errors, inspection, yield, failure, defect, limits
16	Preeti Ranjan Panda, Nikil D. Dutt	Behavioral Array Mapping into Multiport Memories Targeting Low Power.	VLSI Design	1997	DBLP DOI BibTeX RDF
16	Manish Pandey, Richard Raimi, Randal E. Bryant, Magdy S. Abadir	Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation.	DAC	1997	DBLP DOI BibTeX RDF
16	Jean Vuillemin, Patrice Bertin, Didier Roncin, Mark Shand, H. H. Touati, Philippe Boucard	Programmable active memories: reconfigurable systems come of age.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
16	Yinan N. Shen, Nohpill Park, Fabrizio Lombardi	Space Cutting Approaches for Repairing Memories.	ICCD	1996	DBLP DOI BibTeX RDF
16	Michael Nicolaidis, Vladimir Castro Alves, Hakim Bederr	Testing complex couplings in multiport memories.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
16	Herman Schmit, Donald E. Thomas	Address generation for memories containing multiple arrays.	ICCAD	1995	DBLP DOI BibTeX RDF
16	Kanad Chakraborty, Pinaki Mazumder	Technology and layout-related testing of static random-access memories.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Array layout, cell technology, Gallium Arsenide (GaAs), high electron mobility transistor (HEMT) RAMs, I DD testing, I DDQ testing
16	Cosimo Antonio Prete	Cachesim: A Graphical Software Environment to Support the Teaching of Computer Systems with Cache Memories.	CSEE	1994	DBLP DOI BibTeX RDF
16	Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima	Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
16	Francisco Javier López Aligué, M. Isabel Acevedo Sotoca, Miguel A. Jaramillo Morán	Synthesis of Adaptive Memories with Neural Networks.	IWANN	1991	DBLP DOI BibTeX RDF
16	Rob Dekker, Frans P. M. Beenker, Loek Thijssen	A realistic fault model and test algorithms for static random access memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
16	Patrick M. Miller, Ali R. Hurson	Rapid design of testable, high-performance/capacity associative memories.	SPDP	1990	DBLP DOI BibTeX RDF
16	Ram Raghavan, John P. Hayes	On randomly interleaved memories.	SC	1990	DBLP DOI BibTeX RDF
16	M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia	Allocation of multiport memories in data path synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
16	Pinaki Mazumder, Janak H. Patel, W. Kent Fuchs	Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories.	DAC	1987	DBLP DOI BibTeX RDF
16	A. K. Gillis, G. E. Hoffmann, R. H. Nelson	Holographic memories: fantasy or reality?	AFIPS National Computer Conference	1975	DBLP DOI BibTeX RDF
16	Adin D. Falkoff	Algorithms for Parallel-Search Memories.	J. ACM	1962	DBLP DOI BibTeX RDF
13	Izuchukwu Nwachukwu, Krishna M. Kavi, Fawibe Ademola, Chris Yan	Evaluation of Techniques to Improve Cache Access Uniformities.	ICPP	2011	DBLP DOI BibTeX RDF	Cache Indexing, Non-Uniformity of Cache Accesses, Cache Memories, Performance Improvement
13	Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Making Address-Correlated Prefetching Practical.	IEEE Micro	2010	DBLP DOI BibTeX RDF	address-correlated prefetching, cache memories
13	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures.	IEEE Micro	2010	DBLP DOI BibTeX RDF	nonuniform cache architectures, parallel architectures, multicore, cache memories, data placement
13	Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Peter F. Sweeney	The Effect of Omitted-Variable Bias on the Evaluation of Compiler Optimizations.	Computer	2010	DBLP DOI BibTeX RDF	Omitted-variable bias, Cache memories, Design and test, Computer performance, Measurement errors
13	George Lentaris, Dionysios I. Reisis	A Graphics Parallel Memory Organization Exploiting Request Correlations.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	storage devices, Parallel processing, graphics processors, interleaved memories
13	Yiqiang Ding, Wei Zhang 0002	Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	cache memories, Real-time and embedded systems
13	Nikola Vujic, Marc González 0001, Xavier Martorell, Eduard Ayguadé	Automatic Prefetch and Modulo Scheduling Transformations for the Cell BE Architecture.	IEEE Trans. Parallel Distributed Syst.	2010	DBLP DOI BibTeX RDF	prefetch code generation, Multicore processor, local memories, software cache
13	Karin Weigelt, Mike Hambsch, Gabor Karacs, Tino Zillger, Arved C. Hübler	Labeling the World: Tagging Mass Products with Printing Processes.	IEEE Pervasive Comput.	2010	DBLP DOI BibTeX RDF	memory control and access, design styles, printed electronics, printing processes, ubiquitous computing, logic design, hardware, hardware, computer systems organization, memory structures, special-purpose and application-based systems, ROM, semiconductor memories
13	Roberto Palmieri, Francesco Quaglia, Paolo Romano 0002	AGGRO: Boosting STM Replication via Aggressively Optimistic Transaction Processing.	NCA	2010	DBLP DOI BibTeX RDF	Distributed Transactional Memories, distributed systems, dependability, Replication protocols
13	Daniela Petrelli, Nicolas Villar, Vaiva Kalnikaité, Lina Dib, Steve Whittaker 0001	FM radio: family interplay with sonic mementos.	CHI	2010	DBLP DOI BibTeX RDF	mementos, memories, audio, narrative, tangible interaction
13	Jacques J. A. Fournier, Philippe Loubet-Moundi	Memory Address Scrambling Revealed Using Fault Attacks.	FDTC	2010	DBLP DOI BibTeX RDF	Floating Gate memories, address scrambling, EEPROM, reverse-engineering, Fault Injections, Flash
13	Harika Manem, Garrett S. Rose, Xiaoli He, Wei Wang 0003	Design considerations for variation tolerant multilevel CMOS/Nano memristor memory.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	CMOS/nano, memristor, multi level memories
13	Aleksandar Dragojevic, Rachid Guerraoui, Michal Kapalka	Stretching transactional memory.	PLDI	2009	DBLP DOI BibTeX RDF	benchmarks, software transactional memories
13	Josefa Díaz, José Ignacio Hidalgo, Francisco Fernández 0001, Oscar Garnica, Sonia López	Improving SMT performance: an application of genetic algorithms to configure resizable caches.	GECCO (Companion)	2009	DBLP DOI BibTeX RDF	reconfigurable caches, genetic algorithms, optimization, caches memories, simultaneous multithreading, gals, adaptive caches
13	Oluwayomi B. Adamo, Afrin Naz, Tommy Janjusic, Krishna M. Kavi, Chung-Ping Chung	Smaller Split L-1 Data Caches for Multi-core Processing Systems.	ISPAN	2009	DBLP DOI BibTeX RDF	Split data cache, uniform cache access patterns, Cache memories
13	Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Zhichun Zhu	Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices.	ISCA	2009	DBLP DOI BibTeX RDF	bandwidth decoupling, decoupled DIMM, DRAM memories
13	Elise van den Hoven, Berry Eggen	Informing augmented memory system design through autobiographical memory theory.	Pers. Ubiquitous Comput.	2008	DBLP DOI BibTeX RDF	Recollecting memories, Augmented memory systems, Interactive system design, Autobiographical memory
13	Roberto Antonio Vázquez Espinoza de los Monteros, Juan Humberto Sossa Azuela	A New Associative Model with Dynamical Synapses.	Neural Process. Lett.	2008	DBLP DOI BibTeX RDF	Pattern recognition, Associative memories, Dynamical synapses
13	Sung Woo Chung, Kevin Skadron	On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Low-power design, Microprocessors, Cache memories, Energy-aware systems