Search results for "x-by-wire"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Wojciech Wiçclawek, Ewa Piçtka	Numerical Complexity Reduction in Live-Wire Algorithm.	Computer Recognition Systems 2	2008	DBLP DOI BibTeX RDF
17	Massimiliano Melani, Lorenzo Bertini, Marco De Marinis, Peter Lange, Francesco D'Ascoli, Luca Fanucci	Hot Wire Anemometric MEMS Sensor for Water Flow Monitoring.	DATE	2008	DBLP DOI BibTeX RDF
17	Enrique San Millán, Luis Entrena, José Alberto Espejo	Logic Transformations by Multiple Wire Network Addition.	DSD	2008	DBLP DOI BibTeX RDF
17	Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang	An MILP-based wire spreading algorithm for PSM-aware layout modification.	ASP-DAC	2008	DBLP DOI BibTeX RDF
17	Joshua Candamo, Dmitry B. Goldgof	Wire detection in low-altitude, urban, and low-quality video frames.	ICPR	2008	DBLP DOI BibTeX RDF
17	Stephan Kubisch, Harald Widiger, Peter Danielis, Jens Schulz, Dirk Timmermann, Thomas Bahls, Daniel Duchow	Countering phishing threats with trust-by-wire in packet-switched ip networks - a conceptual framework.	IPDPS	2008	DBLP DOI BibTeX RDF
17	Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan	Guiding global placement with wire density.	ICCAD	2008	DBLP DOI BibTeX RDF
17	Michael S. McCorquodale, Scott M. Pernia, Sundus Kubba, Gordy A. Carichner, Justin D. O'Day, Eric D. Marsman, Jonathan J. Kuhn, Richard B. Brown	A 25MHz all-CMOS reference clock generator for XO-replacement in serial wire interfaces.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Qiaoyan Yu, Paul Ampadu	Configurable error correction for multi-wire errors in switch-to-switch SOC links.	SoCC	2008	DBLP DOI BibTeX RDF
17	Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl	Considering possible opens in non-tree topology wire delay calculation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	non-tree topologies, yield, static timing analysis, delay analysis
17	Harald Widiger, Stephan Kubisch, Peter Danielis, Jens Schulz, Dirk Timmermann, Thomas Bahls, Daniel Duchow	IPclip: An architecture to restore Trust-by-Wire in packet-switched networks.	LCN	2008	DBLP DOI BibTeX RDF
17	Huabin Chen, Tao Lin 0011, Shanben Chen, Jifeng Wang, Jianqiang Jia, Hui Zhang	Adaptive control on wire feeding in robot arc welding system.	RAM	2008	DBLP DOI BibTeX RDF
17	Wu Ruizhe, Han Fei, Ren Li	Optimizing the Wire Layout in Wireless Mesh Network.	ICIW	2007	DBLP DOI BibTeX RDF
17	Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter	Leveraging Wire Properties at the Microarchitecture Level.	IEEE Micro	2006	DBLP DOI BibTeX RDF	interconnections, multiprocessor systems, interprocessor communications, energy-aware systems, interconnection architectures, advanced technologies
17	Mario R. Casu, Luca Macchiarulo	Floorplanning With Wire Pipelining in Adaptive Communication Channels.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
17	Ya-Jun Pan 0001, Carlos Canudas-de-Wit, Olivier Sename	A New Predictive Approach for Bilateral Teleoperation With Applications to Drive-by-Wire Systems.	IEEE Trans. Robotics	2006	DBLP DOI BibTeX RDF
17	Stephen Saric, Alireza Bab-Hadiashar, Reza Hoseinnezhad	A Sensor Fusion Approach to Estimate Clamp Force in Brake-by-Wire Systems.	VTC Spring	2006	DBLP DOI BibTeX RDF
17	Se-Joong Lee, Kwanho Kim, Hyejung Kim, Namjun Cho, Hoi-Jun Yoo	A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes.	DATE	2006	DBLP DOI BibTeX RDF
17	Sean X. Shi, David Z. Pan	Wire sizing with scattering effect for nanoscale interconnection.	ASP-DAC	2006	DBLP DOI BibTeX RDF
17	Hui Guo, Ying Jiang	Application Layer Definition and Analyses of Controller Area Network Bus for Wire Harness Assembly Machine.	CIMCA/IAWTIC	2006	DBLP DOI BibTeX RDF
17	Kostas Siozios, Dimitrios Soudris	Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures.	FPL	2006	DBLP DOI BibTeX RDF
17	Adel M. Sharaf, Roshan Chhetri	A Novel Dynamic Capacitor Compensator/Green Plug Scheme for 3Phase-4 Wire Utilization Loads.	CCECE	2006	DBLP DOI BibTeX RDF
17	Luo Yuan, Chaichana Mitrpant, A. J. Han Vinck, Kefei Chen	Some new characters on the wire-tap channel of type II.	IEEE Trans. Inf. Theory	2005	DBLP DOI BibTeX RDF
17	Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu	Evaluation of on-chip transmission line interconnect using wire length distribution.	ASP-DAC	2005	DBLP DOI BibTeX RDF
17	Emil Axelsson, Koen Claessen, Mary Sheeran	Wired: Wire-Aware Circuit Design.	CHARME	2005	DBLP DOI BibTeX RDF
17	Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee	Wire-driven microarchitectural design space exploration.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
17	Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand	Assessment of on-chip wire-length distribution models.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
17	Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan	Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.	PATMOS	2004	DBLP DOI BibTeX RDF
17	Bradford M. Beckmann, David A. Wood 0001	Managing Wire Delay in Large Chip-Multiprocessor Caches.	MICRO	2004	DBLP DOI BibTeX RDF
17	Gérard Mas, Philippe Martin 0005	Network-on-Chip: The Intelligence is in The Wire.	ICCD	2004	DBLP DOI BibTeX RDF
17	Changkyu Kim, Doug Burger, Stephen W. Keckler	Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches.	IEEE Micro	2003	DBLP DOI BibTeX RDF
17	Peter G. Sassone, Sung Kyu Lim	A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning.	ICCAD	2003	DBLP DOI BibTeX RDF
17	Samy Ebeid, Raouf Fahmy, Sameh Habib	An Operating and Diagnostic Knowledge-Based System for Wire EDM.	KES	2003	DBLP DOI BibTeX RDF
17	Shridhar Mubaraq Mishra, A. Guruprasad, Chun Feng Hu, Pramod K. Pandey, Ming Hung	Wire-speed traffic management in Ethernet switches.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
17	Charles C. Chiang, Qing Su, Ching-Shoei Chiang	Wirelength reduction by using diagonal wire.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	45° routing, diagonal routing, routing, steiner tree
17	Steve Kapp	802.11: Leaving the Wire Behind.	IEEE Internet Comput.	2002	DBLP DOI BibTeX RDF
17	Roman Nossal, Roland Lang	Model-Based System Development: An Approach to Building X-by-Wire Applications.	IEEE Micro	2002	DBLP DOI BibTeX RDF
17	Guoan Zhong, Cheng-Kok Koh, Kaushik Roy 0001	On-chip interconnect modeling by wire duplication.	ICCAD	2002	DBLP DOI BibTeX RDF
17	Katarzyna Radecka, Zeljko Zilic	Identifying Redundant Wire Replacements for Synthesis and Verification.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
17	Changkyu Kim, Doug Burger, Stephen W. Keckler	An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches.	ASPLOS	2002	DBLP DOI BibTeX RDF
17	Yasuhiro Ishida, Y. Yamaguchi, Nobuo Kuwabara, M. Tokuda	Visualization of radiated emission sources on a wire using far field amplitude data.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
17	Rony Kay, Rob A. Rutenbar	Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
17	Michael T. Niemier, Peter M. Kogge	Exploring and exploiting wire-level pipelining in emerging technologies.	ISCA	2001	DBLP DOI BibTeX RDF
17	Christopher Metz 0001	On the Wire: IP-over-Satellite: Internet Connectivity Blasts Off.	IEEE Internet Comput.	2000	DBLP DOI BibTeX RDF
17	Bryan P. Rynne	Convergence of Galerkin method solutions of the integral equation for thin wire antennas.	Adv. Comput. Math.	2000	DBLP DOI BibTeX RDF	78O8, 78A50, 65R20, convergence rates, Galerkin methods, electromagnetic scattering
17	Noel Menezes, Chung-Ping Chen	Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect.	VLSI Design	1999	DBLP DOI BibTeX RDF
17	Ying C. (Bob) Yeh	Design Considerations in Boeing 777 Fly-By-Wire Computers.	HASE	1998	DBLP DOI BibTeX RDF
17	Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi	Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
17	David J. Hathaway, Rafik R. Habra, Erich C. Schanzenbach, Sara J. Rothman	Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
17	Sachin S. Sapatnekar	Wire sizing as a convex optimization problem: exploring the area-delay tradeoff.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
17	Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli	Synthesis of hazard-free asynchronous circuits with bounded wire delays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
17	John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin	Optimal wire sizing and buffer insertion for low power and a generalized delay model.	ICCAD	1995	DBLP DOI BibTeX RDF	Timing Optization, Dynamic Power Dissipation, Signal Slew, Dynamic Programming, Elmore Delay
17	Kyunrak Chong, Sartaj Sahni	Minimizing total wire length by flipping modules.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
17	Jan-Ming Ho, Atsushi Suzuki, Majid Sarrafzadeh	An exact algorithm for single-layer wire length minimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
17	Yvan G. Leclerc, Martin A. Fischler	An optimization-based approach to the interpretation of single line drawings as 3D wire frames.	Int. J. Comput. Vis.	1992	DBLP DOI BibTeX RDF
17	P. Groenveld	On Global Wire Ordering for Macro-Cell Routing.	DAC	1989	DBLP DOI BibTeX RDF
17	Andrew W. Appel	Simulating digital circuits with one bit per wire.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
17	John A. Brewer III, S. Mark Courter	Automated conversion of curvilinear wire-frame models to surface boundary models; a topological approach.	SIGGRAPH	1986	DBLP DOI BibTeX RDF
15	Qiaoyan Yu, Paul Ampadu	Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip.	NOCS	2010	DBLP DOI BibTeX RDF	permanent error, splitting transmission, spare wire, reliability, Network-on-chip, transient error
15	Hua Liu, Huilai Zou, Lili Zhong, Chaonan Wang, Youtian Qu	Improvement of the Optimal Hamilton Circuit for Undirected Complete Graph.	CIT	2010	DBLP DOI BibTeX RDF	undirected complete graph, Optimal Hamilton Circuit, Gradually Convergent Algorithm, Cross-wire Cutting Algorithm, Nearest Neighbor Algorithm
15	Michael R. Marner, Bruce H. Thomas	Augmented foam sculpting for capturing 3D models.	3DUI	2010	DBLP DOI BibTeX RDF	volumetric rendering techniques, augmented foam sculpting process, hand-held hot wire foam cutter tool, 3D virtual model, cut animation, wireframe visualizations, 3D procedural textures, wood grain texture, School of Industrial Design, University of South Australia, spatial augmented reality
15	Zhuang Wu, Zhi Jiao, Li Hongi Guo	Temperature and Humidity Measure-Control System Based on CAN and Digital Sensors.	IFITA (3)	2009	DBLP DOI BibTeX RDF	Measure-control System, 1-Wire, CAN
15	Beom-Il Nam, Byeungwoo Jeon	Mobile based digital contents conversion service implementation.	ICIS	2009	DBLP DOI BibTeX RDF	UCC, mobile contents sharing, mobile conversion, mobile multimedia transformation, wire and wireless service, mobile, WAP, WIPI
15	Michael Paulitsch, Brendan Hall	Starting and Resolving a Partitioned BRAIN.	ISORC	2008	DBLP DOI BibTeX RDF	braided ring, TTP/C, IMA, communication platform, x-by-wire, synchronization, integrity, availability, BRAIN, time-triggered, FlexRay, start-up
15	Mario R. Casu, Luca Macchiarulo	Adaptive Latency-Insensitive Protocols.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	latency-insensitive protocols, interconnections, ICs, wire pipelining
15	Pranav Anbalagan, Jeffrey A. Davis	A priori prediction of tightly clustered connections based on heuristic classification trees.	SLIP	2006	DBLP DOI BibTeX RDF	wire length prediction
15	Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex	Impact of interconnect resistance increase on system performance of low power and high performance designs.	SLIP	2006	DBLP DOI BibTeX RDF	interconnect sizing, interconnect technology evaluation, power-delay trade-off, wire sizing
15	Peter A. N. Bosman, Tanja Alderliesten	Evolutionary algorithms for medical simulations: a case study in minimally-invasive vascular interventions.	GECCO Workshops	2005	DBLP DOI BibTeX RDF	guide wire, minimally invasive, vascular intervention, evolutionary algorithms, training, numerical optimization, gradients, medical simulation
15	Mario R. Casu, Luca Macchiarulo	Floorplanning for throughput.	ISPD	2004	DBLP DOI BibTeX RDF	systems-on-chip, throughput, floorplanning, wire pipelining
15	Kristjan Varnik, Jason Freeman 0001, Chandrasekhar Ramakrishnan	Tools used while developing auracle: a voice-controlled networked instrument.	ACM Multimedia	2004	DBLP DOI BibTeX RDF	JSyn, SuperCollider, auracle, network and control, open sound control, transjam, voice controlled synthesis, Java, wire, interactive music systems, Max/MSP
15	Joni Dambre, Dirk Stroobandt, Jan Van Campenhout	Fast estimation of the partitioning rent characteristic using a recursive partitioning model.	SLIP	2003	DBLP DOI BibTeX RDF	a priori wire length prediction, recursive circuit partitioning, graph bipartitioning
15	Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex	Global interconnect trade-off for technology over memory modules to application level: case study.	SLIP	2003	DBLP DOI BibTeX RDF	Pareto-optimal energy/delay interconnect exploration, interconnect wire processing, intra/inter-memory interconnect
15	Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura	Power analysis techniques for SoC with improved wiring models.	ISLPED	2002	DBLP DOI BibTeX RDF	custom wire load model, SoC, power analysis, gate-level
15	Chris C. N. Chu, D. F. Wong 0001	VLSI Circuit Performance Optimization by Geometric Programming.	Ann. Oper. Res.	2001	DBLP DOI BibTeX RDF	unary geometric programming, circuit performance optimization, VLSI design, Lagrangian relaxation, gate sizing, transistor sizing, wire sizing
15	Arifur Rahman, Shamik Das, Anantha P. Chandrakasan, Rafael Reif	Wiring requirement and three-dimensional integration of field-programmable gate arrays.	SLIP	2001	DBLP DOI BibTeX RDF	3-D integrated circuits, FPGA, system-level modeling, wire-length
15	Kees Veelenturf	The Road to Better Reliability and Yield Embedded DfM Tools.	DATE	2000	DBLP DOI BibTeX RDF	wire spreading, yield prediction, yield improvement, DfM
15	Louis Scheffer, Eric Nequist	Why interconnect prediction doesn't work.	SLIP	2000	DBLP DOI BibTeX RDF	constructive estimation, wire load model, interconnect prediction
15	Peng Li 0001, Pranab K. Nag, Wojciech Maly	Cost based tradeoff analysis of standard cell designs.	SLIP	2000	DBLP DOI BibTeX RDF	a posteriori wire length estimation, die size estimation, yield and cost prediction
15	Andrew B. Kahng, Dirk Stroobandt	Wiring layer assignments with consistent stage delays.	SLIP	2000	DBLP DOI BibTeX RDF	via impact, routing, delay, wire length, layer assignment
15	Anil N. Hirani, Takashi Totsuka	Combining Frequency and Spatial Domain Information for Fast Interactive Image Noise Removal.	SIGGRAPH	1996	DBLP DOI BibTeX RDF	projections into convex sets, scratch and wire removal, POCS
15	Andrew Lim 0001, Siu-Wing Cheng, Sartaj Sahni	Optimal Joining of Compacted Cells.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	compacted cells, river routing, minimum area joining, low-order polynomial complexity, VLSI, network routing, circuit layout CAD, stretching, wire length
15	Hartmut Schmeck, Heiko Schröder 0001	Dictionary Machines for Different Models of VLSI.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	VLSI hardware models, Dictionary machines. are taken as an example to demonstrate the implications the choice of the VLSI hardware model has on the design and analysis of algorithms and special purpose architectures, A systolic search tree and a two-dimensional systolic array are used to implement the dictionary machine, If the wire lengths only affect the area, the systolic search tree suggests itself as an efficient realization of a dictionary machine having constant period, linear areS and logarithmic execution t, Algorithms for VLSI, systolic search tree, systolic array, VLSI complexity, dictionary machine
12	Stefan Appel, Kai Sachs, Alejandro P. Buchmann	Towards benchmarking of AMQP.	DEBS	2010	DBLP DOI BibTeX RDF
12	Hua Xiang 0001, Haoxing Ren, Louise Trevillyan, Lakshmi N. Reddy, Ruchir Puri, Minsik Cho	Logical and physical restructuring of fan-in trees.	ISPD	2010	DBLP DOI BibTeX RDF	symmetric-function fan-in tree, restructure, commutative
12	Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li 0001	Accurate clock mesh sizing via sequential quadraticprogramming.	ISPD	2010	DBLP DOI BibTeX RDF	optimization, sequential quadratic programming
12	Xiaoqing Yang, Tak-Kei Lam, Yu-Liang Wu	ECR: a low complexity generalized error cancellation rewiring scheme.	DAC	2010	DBLP DOI BibTeX RDF	error cancellation, ATPG, rewire
12	Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie 0001	Scan-chain design and optimization for three-dimensional integrated circuits.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	scan-chain design, genetic algorithm, integer linear programming, randomized rounding, LP relaxation, 3D ICs
12	Sungyul Choe, Junho Kim 0001, Haeyoung Lee, Seungyong Lee 0001	Random Accessible Mesh Compression Using Mesh Chartification.	IEEE Trans. Vis. Comput. Graph.	2009	DBLP DOI BibTeX RDF
12	Hu Xu 0002, Vasilis F. Pavlidis, Giovanni De Micheli	Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits.	NanoNet	2009	DBLP DOI BibTeX RDF	timing optimization, on-chip interconnect, repeater insertion, 3-D ICs
12	Yohan Noh, Masanao Segawa, Akihiro Shimomura, Hiroyuki Ishii, Jorge Solis, Atsuo Takanishi, Kazuyuki Hatake	Development of the airway management training system WKA-2 designed to reproduce different cases of difficult airway.	ICRA	2009	DBLP DOI BibTeX RDF
12	Rosemary M. Francis, Simon W. Moore	FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis.	FPGA	2009	DBLP DOI BibTeX RDF	tdm wiring, fpga, routing
12	Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li	Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing.	ASP-DAC	2009	DBLP DOI BibTeX RDF
12	Chia-I Chen, Juinn-Dar Huang	CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
12	Daisuke Yamamoto, Shotaro Ozeki, Naohisa Takahashi	Wired Fisheye Lens: A Motion-Based Improved Fisheye Interface for Mobile Web Map Services.	W2GIS	2009	DBLP DOI BibTeX RDF	Focus+Glue+Context, Fisheye views, Mobile maps, Web map service
12	Shiyan Hu, Zhuo Li 0001, Charles J. Alpert	A faster approximation scheme for timing driven minimum cost layer assignment.	ISPD	2009	DBLP DOI BibTeX RDF	dynamic programming, np-complete, oracle, fully polynomial time approximation scheme, layer assignment
12	Zhimin Chen 0002, Syed Haider, Patrick Schaumont	Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects.	ISA	2009	DBLP DOI BibTeX RDF
12	Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu	Buffer design and optimization for lut-based structured ASIC design styles.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	structured asic, interconnection, buffer insertion
12	Bao Liu 0001	Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution.	ISQED	2009	DBLP DOI BibTeX RDF
12	Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong	Incremental power optimization for multiple supply voltage design.	ISQED	2009	DBLP DOI BibTeX RDF
12	Ming Xu, Gary Gréwal, Shawki Areibi, Charlie Obimbo, Dilip K. Banerji	Near-linear wirelength estimation for FPGA placement.	CCECE	2009	DBLP DOI BibTeX RDF