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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1786 occurrences of 1001 keywords
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Results
Found 4641 publication records. Showing 4639 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Wojciech Wiçclawek, Ewa Piçtka |
Numerical Complexity Reduction in Live-Wire Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer Recognition Systems 2 ![In: Computer Recognition Systems 2, pp. 140-147, 2008, Springer, 978-3-540-75174-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Massimiliano Melani, Lorenzo Bertini, Marco De Marinis, Peter Lange, Francesco D'Ascoli, Luca Fanucci |
Hot Wire Anemometric MEMS Sensor for Water Flow Monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 342-347, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Enrique San Millán, Luis Entrena, José Alberto Espejo |
Logic Transformations by Multiple Wire Network Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 779-786, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang |
An MILP-based wire spreading algorithm for PSM-aware layout modification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 364-369, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Joshua Candamo, Dmitry B. Goldgof |
Wire detection in low-altitude, urban, and low-quality video frames. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPR ![In: 19th International Conference on Pattern Recognition (ICPR 2008), December 8-11, 2008, Tampa, Florida, USA, pp. 1-4, 2008, IEEE Computer Society, 978-1-4244-2175-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Stephan Kubisch, Harald Widiger, Peter Danielis, Jens Schulz, Dirk Timmermann, Thomas Bahls, Daniel Duchow |
Countering phishing threats with trust-by-wire in packet-switched ip networks - a conceptual framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan |
Guiding global placement with wire density. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 212-217, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Michael S. McCorquodale, Scott M. Pernia, Sundus Kubba, Gordy A. Carichner, Justin D. O'Day, Eric D. Marsman, Jonathan J. Kuhn, Richard B. Brown |
A 25MHz all-CMOS reference clock generator for XO-replacement in serial wire interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2837-2840, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Qiaoyan Yu, Paul Ampadu |
Configurable error correction for multi-wire errors in switch-to-switch SOC links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 71-74, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl |
Considering possible opens in non-tree topology wire delay calculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 17-22, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
non-tree topologies, yield, static timing analysis, delay analysis |
17 | Harald Widiger, Stephan Kubisch, Peter Danielis, Jens Schulz, Dirk Timmermann, Thomas Bahls, Daniel Duchow |
IPclip: An architecture to restore Trust-by-Wire in packet-switched networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: LCN 2008, The 33rd IEEE Conference on Local Computer Networks, The Conference on Leading Edge and Practical Computer Networking, Hyatt Regency Montreal, Montreal, Quebec, Canada, 14-17 October 2008, Proceedings, pp. 312-319, 2008, IEEE Computer Society, 978-1-4244-2412-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Huabin Chen, Tao Lin 0011, Shanben Chen, Jifeng Wang, Jianqiang Jia, Hui Zhang |
Adaptive control on wire feeding in robot arc welding system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAM ![In: 2008 IEEE Conference on Robotics, Automation and Mechatronics, RAM 2008, 21-24 September 2008, Chengdu, China, pp. 119-122, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Wu Ruizhe, Han Fei, Ren Li |
Optimizing the Wire Layout in Wireless Mesh Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIW ![In: International Conference on Internet and Web Applications and Services (ICIW 2007), May 13-19, 2007, Le Morne, Mauritius, pp. 56, 2007, IEEE Computer Society, 0-7695-2844-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter |
Leveraging Wire Properties at the Microarchitecture Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 26(6), pp. 40-52, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
interconnections, multiprocessor systems, interprocessor communications, energy-aware systems, interconnection architectures, advanced technologies |
17 | Mario R. Casu, Luca Macchiarulo |
Floorplanning With Wire Pipelining in Adaptive Communication Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2996-3004, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Ya-Jun Pan 0001, Carlos Canudas-de-Wit, Olivier Sename |
A New Predictive Approach for Bilateral Teleoperation With Applications to Drive-by-Wire Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Robotics ![In: IEEE Trans. Robotics 22(6), pp. 1146-1162, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Stephen Saric, Alireza Bab-Hadiashar, Reza Hoseinnezhad |
A Sensor Fusion Approach to Estimate Clamp Force in Brake-by-Wire Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 63rd IEEE Vehicular Technology Conference, VTC Spring 2006, 7-10 May 2006, Melbourne, Australia, pp. 3007-3011, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Se-Joong Lee, Kwanho Kim, Hyejung Kim, Namjun Cho, Hoi-Jun Yoo |
A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 79-80, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Sean X. Shi, David Z. Pan |
Wire sizing with scattering effect for nanoscale interconnection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 503-508, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Hui Guo, Ying Jiang |
Application Layer Definition and Analyses of Controller Area Network Bus for Wire Harness Assembly Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIMCA/IAWTIC ![In: 2006 International Conference on Computational Intelligence for Modelling Control and Automation (CIMCA 2006), International Conference on Intelligent Agents, Web Technologies and Internet Commerce (IAWTIC 2006), 29 November - 1 December 2006, Sydney, Australia, pp. 11, 2006, IEEE Computer Society, 0-7695-2731-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Kostas Siozios, Dimitrios Soudris |
Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Adel M. Sharaf, Roshan Chhetri |
A Novel Dynamic Capacitor Compensator/Green Plug Scheme for 3Phase-4 Wire Utilization Loads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 454-459, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Luo Yuan, Chaichana Mitrpant, A. J. Han Vinck, Kefei Chen |
Some new characters on the wire-tap channel of type II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 51(3), pp. 1222-1229, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu |
Evaluation of on-chip transmission line interconnect using wire length distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 133-138, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Emil Axelsson, Koen Claessen, Mary Sheeran |
Wired: Wire-Aware Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 5-19, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee |
Wire-driven microarchitectural design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1867-1870, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Assessment of on-chip wire-length distribution models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(10), pp. 1108-1112, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan |
Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 433-441, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Bradford M. Beckmann, David A. Wood 0001 |
Managing Wire Delay in Large Chip-Multiprocessor Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, pp. 319-330, 2004, IEEE Computer Society, 0-7695-2126-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Gérard Mas, Philippe Martin 0005 |
Network-on-Chip: The Intelligence is in The Wire. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 174-177, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Changkyu Kim, Doug Burger, Stephen W. Keckler |
Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 23(6), pp. 99-107, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Peter G. Sassone, Sung Kyu Lim |
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 74-80, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Samy Ebeid, Raouf Fahmy, Sameh Habib |
An Operating and Diagnostic Knowledge-Based System for Wire EDM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES ![In: Knowledge-Based Intelligent Information and Engineering Systems, 7th International Conference, KES 2003, Oxford, UK, September 3-5, 2003, Proceedings, Part I, pp. 691-698, 2003, Springer, 3-540-40803-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Shridhar Mubaraq Mishra, A. Guruprasad, Chun Feng Hu, Pramod K. Pandey, Ming Hung |
Wire-speed traffic management in Ethernet switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 105-108, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Charles C. Chiang, Qing Su, Ching-Shoei Chiang |
Wirelength reduction by using diagonal wire. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 104-107, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
45° routing, diagonal routing, routing, steiner tree |
17 | Steve Kapp |
802.11: Leaving the Wire Behind. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Comput. ![In: IEEE Internet Comput. 6(1), pp. 82-85, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Roman Nossal, Roland Lang |
Model-Based System Development: An Approach to Building X-by-Wire Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 22(4), pp. 56-63, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy 0001 |
On-chip interconnect modeling by wire duplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 341-346, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Katarzyna Radecka, Zeljko Zilic |
Identifying Redundant Wire Replacements for Synthesis and Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 517-523, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Changkyu Kim, Doug Burger, Stephen W. Keckler |
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), San Jose, California, USA, October 5-9, 2002., pp. 211-222, 2002, ACM Press, 1-58113-574-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | Yasuhiro Ishida, Y. Yamaguchi, Nobuo Kuwabara, M. Tokuda |
Visualization of radiated emission sources on a wire using far field amplitude data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 93-98, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Rony Kay, Rob A. Rutenbar |
Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5), pp. 672-679, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Michael T. Niemier, Peter M. Kogge |
Exploring and exploiting wire-level pipelining in emerging technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001, pp. 166-177, 2001, ACM, 0-7695-1162-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Christopher Metz 0001 |
On the Wire: IP-over-Satellite: Internet Connectivity Blasts Off. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Comput. ![In: IEEE Internet Comput. 4(4), pp. 84-89, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Bryan P. Rynne |
Convergence of Galerkin method solutions of the integral equation for thin wire antennas. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Adv. Comput. Math. ![In: Adv. Comput. Math. 12(2-3), pp. 251-259, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
78O8, 78A50, 65R20, convergence rates, Galerkin methods, electromagnetic scattering |
17 | Noel Menezes, Chung-Ping Chen |
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 476-, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Ying C. (Bob) Yeh |
Design Considerations in Boeing 777 Fly-By-Wire Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASE ![In: 3rd IEEE International Symposium on High-Assurance Systems Engineering (HASE '98), 13-14 November 1998, Washington, D.C, USA, Proceedings, pp. 64-73, 1998, IEEE Computer Society, 0-8186-9221-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi |
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(2), pp. 210-215, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | David J. Hathaway, Rafik R. Habra, Erich C. Schanzenbach, Sara J. Rothman |
Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 16(2-3), pp. 191-198, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Sachin S. Sapatnekar |
Wire sizing as a convex optimization problem: exploring the area-delay tradeoff. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8), pp. 1001-1011, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli |
Synthesis of hazard-free asynchronous circuits with bounded wire delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1), pp. 61-86, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin |
Optimal wire sizing and buffer insertion for low power and a generalized delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 138-143, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Timing Optization, Dynamic Power Dissipation, Signal Slew, Dynamic Programming, Elmore Delay |
17 | Kyunrak Chong, Sartaj Sahni |
Minimizing total wire length by flipping modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1), pp. 167-175, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Jan-Ming Ho, Atsushi Suzuki, Majid Sarrafzadeh |
An exact algorithm for single-layer wire length minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1), pp. 175-180, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Yvan G. Leclerc, Martin A. Fischler |
An optimization-based approach to the interpretation of single line drawings as 3D wire frames. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Vis. ![In: Int. J. Comput. Vis. 9(2), pp. 113-136, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | P. Groenveld |
On Global Wire Ordering for Macro-Cell Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 155-160, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
17 | Andrew W. Appel |
Simulating digital circuits with one bit per wire. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9), pp. 987-993, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | John A. Brewer III, S. Mark Courter |
Automated conversion of curvilinear wire-frame models to surface boundary models; a topological approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGGRAPH ![In: Proceedings of the 13th Annual Conference on Computer Graphics and Interactive Techniques, SIGGRAPH 1986, Dallas, Texas, USA, August 18-22, 1986, pp. 171-178, 1986, ACM, 0-89791-196-2. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
15 | Qiaoyan Yu, Paul Ampadu |
Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010, pp. 145-154, 2010, IEEE Computer Society, 978-0-7695-4053-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
permanent error, splitting transmission, spare wire, reliability, Network-on-chip, transient error |
15 | Hua Liu, Huilai Zou, Lili Zhong, Chaonan Wang, Youtian Qu |
Improvement of the Optimal Hamilton Circuit for Undirected Complete Graph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 10th IEEE International Conference on Computer and Information Technology, CIT 2010, Bradford, West Yorkshire, UK, June 29-July 1, 2010, pp. 2129-2133, 2010, IEEE Computer Society, 978-0-7695-4108-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
undirected complete graph, Optimal Hamilton Circuit, Gradually Convergent Algorithm, Cross-wire Cutting Algorithm, Nearest Neighbor Algorithm |
15 | Michael R. Marner, Bruce H. Thomas |
Augmented foam sculpting for capturing 3D models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3DUI ![In: IEEE Symposium on 3D User Interfaces, 3DUI 2010, Waltham, MA, USA, 20-21 March, 2010, pp. 63-70, 2010, IEEE Computer Society, 978-1-4244-6846-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
volumetric rendering techniques, augmented foam sculpting process, hand-held hot wire foam cutter tool, 3D virtual model, cut animation, wireframe visualizations, 3D procedural textures, wood grain texture, School of Industrial Design, University of South Australia, spatial augmented reality |
15 | Zhuang Wu, Zhi Jiao, Li Hongi Guo |
Temperature and Humidity Measure-Control System Based on CAN and Digital Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFITA (3) ![In: International Forum on Information Technology and Applications, IFITA 2009, Chengdu, China, 15-17 May 2009, pp. 548-550, 2009, IEEE Computer Society, 978-0-7695-3600-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Measure-control System, 1-Wire, CAN |
15 | Beom-Il Nam, Byeungwoo Jeon |
Mobile based digital contents conversion service implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIS ![In: Proceedings of the 2nd International Conference on Interaction Sciences: Information Technology, Culture and Human (ICIS 2009), Seoul, Korea, 24-26 November 2009, pp. 1432-1436, 2009, ACM, 978-1-60558-710-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
UCC, mobile contents sharing, mobile conversion, mobile multimedia transformation, wire and wireless service, mobile, WAP, WIPI |
15 | Michael Paulitsch, Brendan Hall |
Starting and Resolving a Partitioned BRAIN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISORC ![In: 11th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2008), 5-7 May 2008, Orlando, Florida, USA, pp. 415-421, 2008, IEEE Computer Society, 978-0-7695-3132-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
braided ring, TTP/C, IMA, communication platform, x-by-wire, synchronization, integrity, availability, BRAIN, time-triggered, FlexRay, start-up |
15 | Mario R. Casu, Luca Macchiarulo |
Adaptive Latency-Insensitive Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(5), pp. 442-452, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
latency-insensitive protocols, interconnections, ICs, wire pipelining |
15 | Pranav Anbalagan, Jeffrey A. Davis |
A priori prediction of tightly clustered connections based on heuristic classification trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 9-15, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
wire length prediction |
15 | Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex |
Impact of interconnect resistance increase on system performance of low power and high performance designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 85-90, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
interconnect sizing, interconnect technology evaluation, power-delay trade-off, wire sizing |
15 | Peter A. N. Bosman, Tanja Alderliesten |
Evolutionary algorithms for medical simulations: a case study in minimally-invasive vascular interventions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO Workshops ![In: Genetic and Evolutionary Computation Conference, GECCO 2005, Workshop Proceedings, Washington DC, USA, June 25-26, 2005, pp. 125-132, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
guide wire, minimally invasive, vascular intervention, evolutionary algorithms, training, numerical optimization, gradients, medical simulation |
15 | Mario R. Casu, Luca Macchiarulo |
Floorplanning for throughput. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 62-69, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
systems-on-chip, throughput, floorplanning, wire pipelining |
15 | Kristjan Varnik, Jason Freeman 0001, Chandrasekhar Ramakrishnan |
Tools used while developing auracle: a voice-controlled networked instrument. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Multimedia ![In: Proceedings of the 12th ACM International Conference on Multimedia, New York, NY, USA, October 10-16, 2004, pp. 528-531, 2004, ACM, 1-58113-893-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
JSyn, SuperCollider, auracle, network and control, open sound control, transjam, voice controlled synthesis, Java, wire, interactive music systems, Max/MSP |
15 | Joni Dambre, Dirk Stroobandt, Jan Van Campenhout |
Fast estimation of the partitioning rent characteristic using a recursive partitioning model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 45-52, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
a priori wire length prediction, recursive circuit partitioning, graph bipartitioning |
15 | Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex |
Global interconnect trade-off for technology over memory modules to application level: case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 125-132, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Pareto-optimal energy/delay interconnect exploration, interconnect wire processing, intra/inter-memory interconnect |
15 | Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura |
Power analysis techniques for SoC with improved wiring models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 259-262, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
custom wire load model, SoC, power analysis, gate-level |
15 | Chris C. N. Chu, D. F. Wong 0001 |
VLSI Circuit Performance Optimization by Geometric Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 105(1-4), pp. 37-60, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
unary geometric programming, circuit performance optimization, VLSI design, Lagrangian relaxation, gate sizing, transistor sizing, wire sizing |
15 | Arifur Rahman, Shamik Das, Anantha P. Chandrakasan, Rafael Reif |
Wiring requirement and three-dimensional integration of field-programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 107-113, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
3-D integrated circuits, FPGA, system-level modeling, wire-length |
15 | Kees Veelenturf |
The Road to Better Reliability and Yield Embedded DfM Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 67-68, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
wire spreading, yield prediction, yield improvement, DfM |
15 | Louis Scheffer, Eric Nequist |
Why interconnect prediction doesn't work. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 139-144, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
constructive estimation, wire load model, interconnect prediction |
15 | Peng Li 0001, Pranab K. Nag, Wojciech Maly |
Cost based tradeoff analysis of standard cell designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 129-135, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
a posteriori wire length estimation, die size estimation, yield and cost prediction |
15 | Andrew B. Kahng, Dirk Stroobandt |
Wiring layer assignments with consistent stage delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 115-122, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
via impact, routing, delay, wire length, layer assignment |
15 | Anil N. Hirani, Takashi Totsuka |
Combining Frequency and Spatial Domain Information for Fast Interactive Image Noise Removal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGGRAPH ![In: Proceedings of the 23rd Annual Conference on Computer Graphics and Interactive Techniques, SIGGRAPH 1996, New Orleans, LA, USA, August 4-9, 1996, pp. 269-276, 1996, ACM, 0-89791-746-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
projections into convex sets, scratch and wire removal, POCS |
15 | Andrew Lim 0001, Siu-Wing Cheng, Sartaj Sahni |
Optimal Joining of Compacted Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(5), pp. 597-607, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
compacted cells, river routing, minimum area joining, low-order polynomial complexity, VLSI, network routing, circuit layout CAD, stretching, wire length |
15 | Hartmut Schmeck, Heiko Schröder 0001 |
Dictionary Machines for Different Models of VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 34(5), pp. 472-475, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
VLSI hardware models, Dictionary machines. are taken as an example to demonstrate the implications the choice of the VLSI hardware model has on the design and analysis of algorithms and special purpose architectures, A systolic search tree and a two-dimensional systolic array are used to implement the dictionary machine, If the wire lengths only affect the area, the systolic search tree suggests itself as an efficient realization of a dictionary machine having constant period, linear areS and logarithmic execution t, Algorithms for VLSI, systolic search tree, systolic array, VLSI complexity, dictionary machine |
12 | Stefan Appel, Kai Sachs, Alejandro P. Buchmann |
Towards benchmarking of AMQP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DEBS ![In: Proceedings of the Fourth ACM International Conference on Distributed Event-Based Systems, DEBS 2010, Cambridge, United Kingdom, July 12-15, 2010, pp. 99-100, 2010, ACM, 978-1-60558-927-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
12 | Hua Xiang 0001, Haoxing Ren, Louise Trevillyan, Lakshmi N. Reddy, Ruchir Puri, Minsik Cho |
Logical and physical restructuring of fan-in trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 67-74, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
symmetric-function fan-in tree, restructure, commutative |
12 | Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li 0001 |
Accurate clock mesh sizing via sequential quadraticprogramming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 135-142, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
optimization, sequential quadratic programming |
12 | Xiaoqing Yang, Tak-Kei Lam, Yu-Liang Wu |
ECR: a low complexity generalized error cancellation rewiring scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 511-516, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
error cancellation, ATPG, rewire |
12 | Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie 0001 |
Scan-chain design and optimization for three-dimensional integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(2), pp. 9:1-9:26, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
scan-chain design, genetic algorithm, integer linear programming, randomized rounding, LP relaxation, 3D ICs |
12 | Sungyul Choe, Junho Kim 0001, Haeyoung Lee, Seungyong Lee 0001 |
Random Accessible Mesh Compression Using Mesh Chartification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Vis. Comput. Graph. ![In: IEEE Trans. Vis. Comput. Graph. 15(1), pp. 160-173, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Hu Xu 0002, Vasilis F. Pavlidis, Giovanni De Micheli |
Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings, pp. 141-150, 2009, Springer, 978-3-642-04849-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
timing optimization, on-chip interconnect, repeater insertion, 3-D ICs |
12 | Yohan Noh, Masanao Segawa, Akihiro Shimomura, Hiroyuki Ishii, Jorge Solis, Atsuo Takanishi, Kazuyuki Hatake |
Development of the airway management training system WKA-2 designed to reproduce different cases of difficult airway. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2009 IEEE International Conference on Robotics and Automation, ICRA 2009, Kobe, Japan, May 12-17, 2009, pp. 3833-3838, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Rosemary M. Francis, Simon W. Moore |
FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 285, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
tdm wiring, fpga, routing |
12 | Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li |
Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 570-575, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Chia-I Chen, Juinn-Dar Huang |
CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 67-72, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Daisuke Yamamoto, Shotaro Ozeki, Naohisa Takahashi |
Wired Fisheye Lens: A Motion-Based Improved Fisheye Interface for Mobile Web Map Services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
W2GIS ![In: Web and Wireless Geographical Information Systems, 9th International Symposium, W2GIS 2009, Maynooth, Ireland, December 7-8, 2009. Proceedings, pp. 153-170, 2009, Springer, 978-3-642-10600-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Focus+Glue+Context, Fisheye views, Mobile maps, Web map service |
12 | Shiyan Hu, Zhuo Li 0001, Charles J. Alpert |
A faster approximation scheme for timing driven minimum cost layer assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 167-174, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic programming, np-complete, oracle, fully polynomial time approximation scheme, layer assignment |
12 | Zhimin Chen 0002, Syed Haider, Patrick Schaumont |
Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISA ![In: Advances in Information Security and Assurance, Third International Conference and Workshops, ISA 2009, Seoul, Korea, June 25-27, 2009. Proceedings, pp. 327-336, 2009, Springer, 978-3-642-02616-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu |
Buffer design and optimization for lut-based structured ASIC design styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 377-380, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
structured asic, interconnection, buffer insertion |
12 | Bao Liu 0001 |
Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 430-435, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong |
Incremental power optimization for multiple supply voltage design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 280-286, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Ming Xu, Gary Gréwal, Shawki Areibi, Charlie Obimbo, Dilip K. Banerji |
Near-linear wirelength estimation for FPGA placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, CCECE 2009, 3-6 May 2009, Delta St. John's Hotel and Conference Centre, St. John's, Newfoundland, Canada, pp. 1198-1203, 2009, IEEE, 978-1-4244-3508-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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