Search results for "ISPD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Salim Chowdhury, John Lillis	Repeater insertion for concurrent setup and hold time violations with power-delay trade-off.	ISPD	2007	DBLP DOI BibTeX RDF	early-mode timing, hold violation, late-mode timing, setup violation, timing optimization, repeater insertion
1	Patrick H. Madden, David Z. Pan (eds.)	Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007	ISPD	2007	DBLP DOI BibTeX RDF
1	Chandu Visweswariah	Fear, uncertainty and statistics.	ISPD	2007	DBLP DOI BibTeX RDF	statistical timing, statistical optimization
1	Hao Yu 0001, Yu Hu 0002, Chunchen Liu, Lei He 0001	Minimal skew clock embedding considering time variant temperature gradient.	ISPD	2007	DBLP DOI BibTeX RDF	clock tree design, compact parameterization, parameterized perturbation, thermal management
1	Zhong Xiu, Rob A. Rutenbar	Mixed-size placement with fixed macrocells using grid-warping.	ISPD	2007	DBLP DOI BibTeX RDF	mixed-size placement, algorithms, placement
1	Hua Xiang 0001, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong	Dummy fill density analysis with coupling constraints.	ISPD	2007	DBLP DOI BibTeX RDF	CMP, coupling, dummy fills
1	Keith So	Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space.	ISPD	2007	DBLP DOI BibTeX RDF	negotiated congestion, routability-driven routing, FPGA
1	Jianhua Li, Laleh Behjat, Jie Huang	An effective clustering algorithm for mixed-size placement.	ISPD	2007	DBLP DOI BibTeX RDF	placement, hypergraph clustering
1	Louis Scheffer, Lars Liebmann, Riko Rakojcic, David White	Rules vs tools: what's the right way to address IC manufacturing complexity?	ISPD	2007	DBLP DOI BibTeX RDF
1	Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang	Efficient obstacle-avoiding rectilinear steiner tree construction.	ISPD	2007	DBLP DOI BibTeX RDF	routing, spanning tree, physical design, Steiner tree
1	Ray T. Chen	Optical interconnects: a viable solution for interconnection beyond 10 gbit/sec.	ISPD	2007	DBLP DOI BibTeX RDF	PCB interconnects, optical bus architecture, optical interconnects
1	Shiyan Hu, Jiang Hu	Pattern sensitive placement for manufacturability.	ISPD	2007	DBLP DOI BibTeX RDF	placement, physical design, manufacturability
1	Hua Xiang 0001, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong	Is your layout density verification exact?: a fast exact algorithm for density calculation.	ISPD	2007	DBLP DOI BibTeX RDF	fix-dissection, DFM, density
1	Yiyu Shi 0001, Lei He 0001	Empire: an efficient and compact multiple-parameterized model order reduction method.	ISPD	2007	DBLP DOI BibTeX RDF	reduction, sensitivity, parameter
1	Shankar Krishnamoorthy	Variation and litho driven physical implementation system.	ISPD	2007	DBLP DOI BibTeX RDF	multi-variation optimization, VLSI, lithography
1	Song Chen 0001, Takeshi Yoshimura	A stable fixed-outline floorplanning method.	ISPD	2007	DBLP DOI BibTeX RDF	floorplanning, sequence pair, fixed-outline
1	Philip Chong, Christian Szegedy	A morphing approach to address placement stability.	ISPD	2007	DBLP DOI BibTeX RDF	incremental placement, stability, morphing
1	Anand Ramalingam, Giri Devarayanadurg, David Z. Pan	Accurate power grid analysis with behavioral transistor network modeling.	ISPD	2007	DBLP DOI BibTeX RDF	RC model of transistor, behavioral modeling of switch, power grid
1	Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri	A methodology for interconnect dimension determination.	ISPD	2007	DBLP DOI BibTeX RDF
1	Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden	ISPD placement contest updates and ISPD 2007 global routing contest.	ISPD	2007	DBLP DOI BibTeX RDF
1	David Cross, Eric Nequist, Louis Scheffer	A DFM aware, space based router.	ISPD	2007	DBLP DOI BibTeX RDF
1	Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang	X-architecture placement based on effective wire models.	ISPD	2007	DBLP DOI BibTeX RDF	X architecture, partitioning, placement, physical design, Steiner tree, min cut, net weighting
1	Vishal Khandelwal, Ankur Srivastava 0001	Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation.	ISPD	2007	DBLP DOI BibTeX RDF	post-silicon tunability, variability, stochastic optimization, timing optimization, gate sizing
1	Jim Kahle	Cell architecture: key physical design features and methodology.	ISPD	2007	DBLP DOI BibTeX RDF
1	Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten	Algorithms for automatic length compensation of busses in analog integrated circuits.	ISPD	2007	DBLP DOI BibTeX RDF	analog routing, length compensation, net bundles, paired nets, virtual terminals, routing, EDA, RF, bus routing, IC-layout
1	Noel Menezes	The good, the bad, and the statistical.	ISPD	2007	DBLP DOI BibTeX RDF
1	Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera	Worst-case delay analysis considering the variability of transistors and interconnects.	ISPD	2007	DBLP DOI BibTeX RDF	worst-case delay, interconnect, process variation
1	B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine	Timing analysis in presence of supply voltage and temperature variations.	ISPD	2006	DBLP DOI BibTeX RDF
1	Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky Ramachandran	Solving hard instances of floorplacement.	ISPD	2006	DBLP DOI BibTeX RDF	floorplacement, benchmarks, placement, floorplanning, RTL, circuit layout
1	Mongkol Ekpanyapong, Sung Kyu Lim	Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization.	ISPD	2006	DBLP DOI BibTeX RDF	supply and threshold voltage scaling, low power design, retiming
1	Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang	NTUplace2: a hybrid placer using partitioning and analytical techniques.	ISPD	2006	DBLP DOI BibTeX RDF	placement, physical design, legalization
1	Jianhua Li, Laleh Behjat	Net cluster: a net-reduction based clustering preprocessing algorithm.	ISPD	2006	DBLP DOI BibTeX RDF	VLSI partitioning, physical design, hypergraph clustering
1	Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen	Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs.	ISPD	2006	DBLP DOI BibTeX RDF	fault-tolerant, reliability, low power, coupling capacitance
1	Bor-Yiing Su, Yao-Wen Chang, Jiang Hu	An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles.	ISPD	2006	DBLP DOI BibTeX RDF	jumper insertion, antenna effect
1	Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian 0001	Prediction and reduction of routing congestion.	ISPD	2006	DBLP DOI BibTeX RDF	placement, physical design, congestion, routability
1	Uday Padmanabhan, Janet Meiling Wang, Jiang Hu	Statistical clock tree routing for robustness to process variations.	ISPD	2006	DBLP DOI BibTeX RDF	routing, robustness, process variations, clock tree
1	P. V. Srinivas	Chip assembly: a new paradigm in hierarchical physical design.	ISPD	2006	DBLP DOI BibTeX RDF
1	Yiyu Shi 0001, Hao Yu 0001, Lei He 0001	SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance.	ISPD	2006	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Qinke Wang	A faster implementation of APlace.	ISPD	2006	DBLP DOI BibTeX RDF	lens aberration, supply voltage degradation, scalability, analytical placement
1	Arjun Rajagopal	Clock tree design challenges for robust and low power design.	ISPD	2006	DBLP DOI BibTeX RDF	NBTI, IR drop
1	Jens Lienig	introduction to electromigration-aware physical design.	ISPD	2006	DBLP DOI BibTeX RDF	interconnect, layout, physical design, electromigration, current density, interconnect reliability
1	Chen-Wei Liu, Yao-Wen Chang	Floorplan and power/ground network co-synthesis for fast design convergence.	ISPD	2006	DBLP DOI BibTeX RDF	power/ground analysis, simulated annealing, floorplanning, IR drop, power integrity
1	Ted Vucurevich	Commercial CAD: challenges and opportunities.	ISPD	2006	DBLP DOI BibTeX RDF
1	Ad M. G. Peeters	Clockless IC design using handshake technology.	ISPD	2006	DBLP DOI BibTeX RDF
1	Azadeh Davoodi, Ankur Srivastava 0001	Probabilistic evaluation of solutions in variability-driven optimization.	ISPD	2006	DBLP DOI BibTeX RDF	probabilistic optimization
1	Jarrod A. Roy, James F. Lu, Igor L. Markov	Seeing the forest and the trees: Steiner wirelength optimization in placemen.	ISPD	2006	DBLP DOI BibTeX RDF	routing, placement, physical design, Steiner tree
1	Hsin-Yu Chen, Zhi-Da Lin	NEMO: a new implicit connection graph-based gridless router with multi-layer planes and pseudo-tile propagation.	ISPD	2006	DBLP DOI BibTeX RDF	full-chip routing, gridless router, implicit connection graph-based router, point-to-point routing, tile-based router, detailed routing
1	Anne E. Gattiker	IC failure mechanisms yesterday, today, tomorrow: implications from test to DFM.	ISPD	2006	DBLP DOI BibTeX RDF
1	Sherief Reda, Amit Chowdhary	Effective linear programming based placement methods.	ISPD	2006	DBLP DOI BibTeX RDF	relative placement, whitespace management, linear programming, timing-driven placement
1	Zhe Feng 0002, Yu Hu 0002, Tong Jing, Xianlong Hong, Xiaodong Hu 0001, Guiying Yan	An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane.	ISPD	2006	DBLP DOI BibTeX RDF	?-geometry, O(nlogn), Steiner tree construction, obstacle-avoiding
1	Shinichi Kouda, Chikaaki Kodama, Kunihiro Fujiyoshi	Improved method of cell placement with symmetry constraints for analog IC layout design.	ISPD	2006	DBLP DOI BibTeX RDF	symmetry constraints, linear programming, placement, analog circuits, sequence-pair
1	Gi-Joon Nam	ISPD 2006 Placement Contest: Benchmark Suite and Results.	ISPD	2006	DBLP DOI BibTeX RDF
1	Lizheng Zhang, Jun Shao, Charlie Chung-Ping Chen	Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis.	ISPD	2006	DBLP DOI BibTeX RDF
1	Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi, Maogang Wang, Majid Sarrafzadeh	Dragon2006: blockage-aware congestion-controlling mixed-size placer.	ISPD	2006	DBLP DOI BibTeX RDF	placement, physical design
1	Jarrod A. Roy, David A. Papa, Aaron N. Ng, Igor L. Markov	Satisfying whitespace requirements in top-down placement.	ISPD	2006	DBLP DOI BibTeX RDF	placement, physical design, floorplanning
1	Beth L. Chen, Dmitri B. Chklovskii	Placement and routing optimization in the brain.	ISPD	2006	DBLP DOI BibTeX RDF	wiring length minimization, linear programming, neurons, synapses, C. elegans
1	Christoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen	Efficient generation of short and fast repeater tree topologies.	ISPD	2006	DBLP DOI BibTeX RDF	inverter tree, repeater tree, buffering, tree topology, rectilinear Steiner tree
1	François Rémond	Physical design challenges for multi-million gate SoC's: an STMicroelectronics perspective.	ISPD	2006	DBLP DOI BibTeX RDF
1	Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kenton Sze, Min Xie 0004	mPL6: enhanced multilevel mixed-size placement.	ISPD	2006	DBLP DOI BibTeX RDF	mixed-size placement, legalization, Helmholtz equation, force-directed placement, multilevel optimization
1	Jinjun Xiong, Vladimir Zolotov, Lei He 0001	Robust extraction of spatial correlation.	ISPD	2006	DBLP DOI BibTeX RDF	robust extraction, process variation, extraction, spatial correlation
1	Louis Scheffer (eds.)	Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006	ISPD	2006	DBLP DOI BibTeX RDF
1	Jinjun Xiong, Lei He 0001	Fast buffer insertion considering process variations.	ISPD	2006	DBLP DOI BibTeX RDF	pruning rule, dynamic programming, process variation, transitive closure, buffer insertion
1	Anand Rajaram, David Z. Pan	Variation tolerant buffered clock network synthesis with cross links.	ISPD	2006	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
1	Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng	Integrating dynamic thermal via planning with 3D floorplanning algorithm.	ISPD	2006	DBLP DOI BibTeX RDF	3D floorplanning, thermal optimization, thermal via
1	Jun Chen 0008, Lei He 0001	Noise driven in-package decoupling capacitor optimization for power integrity.	ISPD	2006	DBLP DOI BibTeX RDF	IC package, modeling, integrity, noise, power, resonance, decoupling capacitor, power distribution system
1	Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong	High accurate pattern based precondition method for extremely large power/ground grid analysis.	ISPD	2006	DBLP DOI BibTeX RDF	pattern, iterative method, precondition, PCG
1	Andrew B. Kahng, Bao Liu 0001, Sheldon X.-D. Tan	Efficient decoupling capacitor planning via convex programming methods.	ISPD	2006	DBLP DOI BibTeX RDF
1	Stephen P. Boyd, Seung-Jean Kim	Geometric programming for circuit optimization.	ISPD	2005	DBLP DOI BibTeX RDF	convex optimization, geometric programming, generalized geometric programming, circuit sizing
1	Patrick Groeneveld, Louis Scheffer (eds.)	Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005	ISPD	2005	DBLP DOI BibTeX RDF
1	Yukiko Kubo, Atsushi Takahashi 0001	A global routing method for 2-layer ball grid array packages.	ISPD	2005	DBLP DOI BibTeX RDF	2-layer routing, ball grid array, cost graph, heuristic, global routing, monotonic, greedy
1	Di Wu 0017, Jiang Hu, Rabi N. Mahapatra	Coupling aware timing optimization and antenna avoidance in layer assignment.	ISPD	2005	DBLP DOI BibTeX RDF	VLSI, interconnect, probabilistic modeling, physical design, crosstalk, design for manufacturability (DFM), antenna effect
1	Ameya R. Agnihotri, Satoshi Ono, Patrick H. Madden	Recursive bisection placement: feng shui 5.0 implementation details.	ISPD	2005	DBLP DOI BibTeX RDF	mixed block design, placement, floorplanning
1	Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar	An efficient technology mapping algorithm targeting routing congestion under delay constraints.	ISPD	2005	DBLP DOI BibTeX RDF	logic synthesis, technology mapping, routing congestion
1	Bo Hu 0006, Yue Zeng, Malgorzata Marek-Sadowska	mFAR: fixed-points-addition-based VLSI placement algorithm.	ISPD	2005	DBLP DOI BibTeX RDF	placement, fixed points, force-directed
1	Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov	Early research experience with OpenAccess gear: an open source development environment for physical design.	ISPD	2005	DBLP DOI BibTeX RDF	database, timing, open source, placement, physical design, EDA
1	James D. Z. Ma, Rob A. Rutenbar	Fast interval-valued statistical interconnect modeling and reduction.	ISPD	2005	DBLP DOI BibTeX RDF	interval-valued statistical interconnect analysis, manufacturing variation, affine arithmetic
1	Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz	The ISPD2005 placement contest and benchmark suite.	ISPD	2005	DBLP DOI BibTeX RDF	VLSI placement, benchmarks, physical design
1	Rajeev Madhavan	The death of logic synthesis.	ISPD	2005	DBLP DOI BibTeX RDF
1	Brent Goplen, Sachin S. Sapatnekar	Thermal via placement in 3D ICs.	ISPD	2005	DBLP DOI BibTeX RDF	3-D VLSI, thermal gradient, thermal optimization, thermal via, routing, placement, temperature, finite element analysis, 3-D IC
1	Robert F. Lembach, Rafael A. Arce-Nazario, Donald Eisenmenger, Cory Wood	A diagnostic method for detecting and assessing the impact of physical design optimizations on routing.	ISPD	2005	DBLP DOI BibTeX RDF	routing, efficiency, timing, placement, physical synthesis, netlist
1	I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson S. Hall, David V. Anderson	Mapping algorithm for large-scale field programmable analog array.	ISPD	2005	DBLP DOI BibTeX RDF	floating gates, mapping, field programmable analog array
1	Andrew B. Kahng, Sherief Reda	Evaluation of placer suboptimality via zero-change netlist transformations.	ISPD	2005	DBLP DOI BibTeX RDF	placer suboptimality, benchmarking, wirelength
1	Jin-Yih Li, Yih-Lang Li	An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow.	ISPD	2005	DBLP DOI BibTeX RDF	ECO routing, connection-based router, gridless router, tile-based router, global routing
1	Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera	Effects of on-chip inductance on power distribution grid.	ISPD	2005	DBLP DOI BibTeX RDF	on-chip inductance, power supply noise, power distribution network, decoupling capacitance
1	Hayward H. Chan, Saurabh N. Adya, Igor L. Markov	Are floorplan representations important in digital design?	ISPD	2005	DBLP DOI BibTeX RDF	B*-tree, floorplanning, sequence pair, circuit layout
1	Tony F. Chan, Jason Cong, Kenton Sze	Multilevel generalized force-directed method for circuit placement.	ISPD	2005	DBLP DOI BibTeX RDF	force-directed method, multilevel, standard cell placement
1	Mario R. Casu, Luca Macchiarulo	Floorplan assisted data rate enhancement through wire pipelining: a real assessment.	ISPD	2005	DBLP DOI BibTeX RDF	through-put, systems-on-chip, floorplanning, wire pipelining
1	Chris C. N. Chu, Yiu-Chung Wong	Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design.	ISPD	2005	DBLP DOI BibTeX RDF	rectilinear steiner minimal tree algorithm, wirelength estimation, routing
1	Paul Villarrubia	Physical design tools for hierarchy.	ISPD	2005	DBLP DOI BibTeX RDF
1	Gary Smith 0001	A new era for CAD.	ISPD	2005	DBLP DOI BibTeX RDF
1	Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang	NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs.	ISPD	2005	DBLP DOI BibTeX RDF	mincut, ratio cut, placement
1	Qinghua Liu, Malgorzata Marek-Sadowska	Wire length prediction-based technology mapping and fanout optimization.	ISPD	2005	DBLP DOI BibTeX RDF	prediction, congestion, wire length
1	Natarajan Viswanathan, Min Pan, Chris C. N. Chu	FastPlace: an analytical placer for mixed-mode designs.	ISPD	2005	DBLP DOI BibTeX RDF	mixed-mode placement, floorplanning, analytical placement
1	Bernd Obermeier, Hans Ranke, Frank M. Johannes	Kraftwerk: a versatile placement approach.	ISPD	2005	DBLP DOI BibTeX RDF	Kraftwerk, force-directed placement, domino
1	Baris Taskin, Ivan S. Kourtev	Delay insertion method in clock skew scheduling.	ISPD	2005	DBLP DOI BibTeX RDF	delay insertion, re-convergent paths, optimization, linear programming, clock skew
1	Tung-Chieh Chen, Yao-Wen Chang	Modern floorplanning based on fast simulated annealing.	ISPD	2005	DBLP DOI BibTeX RDF	simulated annealing, floorplanning
1	Tony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie 0004	mPL6: a robust multilevel mixed-size placement engine.	ISPD	2005	DBLP DOI BibTeX RDF	mixed-size placement, legalization, helmholtz equation, force-directed placement, multilevel optimization
1	Xin Yuan, Kevin W. McCullen, Fook-Luen Heng, Robert F. Walker, Jason Hibbeler, Robert J. Allen, Rani R. Narayan	Technology migration technique for designs with strong RET-driven layout restrictions.	ISPD	2005	DBLP DOI BibTeX RDF	RDR, RET-driven layout, restrictive design rules, technology migration
1	Andrew B. Kahng, Sherief Reda, Qinke Wang	APlace: a general analytic placement framework.	ISPD	2005	DBLP DOI BibTeX RDF	mixed size, congestion, multi-level, analytical placement
1	Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif	An efficient surface-based low-power buffer insertion algorithm.	ISPD	2005	DBLP DOI BibTeX RDF	low-power design, buffer insertion, physical synthesis

Publications at "ISPD"( http://dblp.L3S.de/Venues/ISPD )