Search results for "analog"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Vishal Hiremath, Robert W. Proctor, Richard O. Fanjoy, Robert G. Feyen, John P. Young	Comparison of Pilot Recovery and Response Times in Two Types of Cockpits.	HCI (9)	2009	DBLP DOI BibTeX RDF	glass cockpits, digital displays, analog displays, displays, aviation
20	Ming Liu, Hua Yu, Wei Wang 0003	FPAA Based on Integration of CMOS and Nanojunction Devices for Neuromorphic Applications.	NanoNet	2008	DBLP DOI BibTeX RDF	Field programmable analog arrays (FPAA), Nanojunction devices, Operational amplifier (Op-amp)
20	Guoyong Shi, Weiwei Chen, C.-J. Richard Shi	A Graph Reduction Approach to Symbolic Circuit Analysis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	symbolic analog circuit simulator, symbolic circuit analysis, recursive sign determination algorithm, binary decision diagram, graph reduction
20	Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu	Time-domain analysis methodology for large-scale RLC circuits and its applications.	Sci. China Ser. F Inf. Sci.	2006	DBLP DOI BibTeX RDF	RLC circuits, analog circuit analysis, P/G networks, algorithm complexity, time-domain analysis
20	Fabio Lacerda, Stefano Pietri, Alfredo Olmos	A differential switched-capacitor amplifier with programmable gain and output offset voltage.	SBCCI	2006	DBLP DOI BibTeX RDF	differential to single ended, switched capacitor stage, analog integrated circuits
20	Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eduardo Conrad Jr., Sergio Bampi	T-shaped association of transistors: modeling of multiple channel lengths and regular associations.	SBCCI	2005	DBLP DOI BibTeX RDF	associations of transistors, modeling, analog design, MOSFET
20	Jérôme Durand-Lose	Abstract Geometrical Computation: Turing-Computing Ability and Undecidability.	CiE	2005	DBLP DOI BibTeX RDF	Analog model of computation, Turing universality, Cellular automata, Geometry, Abstract geometrical computation
20	Samiran Halder, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Swapna Banerjee	A 160MSPS 8-Bit Pipeline Based ADC.	VLSI Design	2005	DBLP DOI BibTeX RDF	Double sampling Sample-and-Hold, Multiplying digital-to-analog converter, Pipeline architecture, Comparator
20	Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri	Fast and accurate parasitic capacitance models for layout-aware.	DAC	2004	DBLP DOI BibTeX RDF	layout aware, parasitic estimation, analog synthesis
20	Michael A. Caloyannides	Digital "Evidence" and Reasonable Doubt.	IEEE Secur. Priv.	2003	DBLP DOI BibTeX RDF	analog data, privacy, digital forensics, digital evidence, data entry
20	Jianhua Gan, Shouli Yan, Jacob A. Abraham	Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	non-binary capacitor array, successive approximation, calibration, analog-to-digital converter
20	Brian W. Amick, Claude R. Gauthier, Dean Liu	Macro-modeling concepts for the chip electrical interface.	DAC	2002	DBLP DOI BibTeX RDF	VLSI power distribution, analog and I/O power delivery, high speed microprocessor design, inductance
20	José Vicente Calvano, Antonio Carneiro de Mesquita Filho, Vladimir Castro Alves, Marcelo Lubaszewski	Fault Models and Test Generation for OpAmp Circuits - The FFM.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	test generation, fault model, analog test, operational amplifiers
20	Rafael C. Carrasco, Mikel L. Forcada	Simple Strategies to Encode Tree Automata in Sigmoid Recursive Neural Networks.	IEEE Trans. Knowl. Data Eng.	2001	DBLP DOI BibTeX RDF	analog neural networks, Tree automata, neural computation, recursive neural networks
20	Hans A. R. Manhaeve, Johan Verfaillie, B. Straka, J. P. Cornil	Application of Supply Current Testing to Analogue Circuits, Towards a Structural Analogue Test Methodology.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	supply current test, I DD, I DDX monitor, analog test, structural test, mixed-signal test, current monitor
20	Melissa Moy, David B. Stewart	An Engineering Approach to Determining Sampling Rates for Switches and Sensors in Real-Time Systems.	IEEE Real Time Technology and Applications Symposium	2000	DBLP DOI BibTeX RDF	component-based device drivers, switch matrix, real-time scheduling, parallel I/O, analog-to-digital converter, software modeling, real-time operating system, experimental software engineering, digital control systems
20	Jeongjin Roh, Jacob A. Abraham	A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test.	VTS	2000	DBLP DOI BibTeX RDF	oscillation test, BIST, signature, analog, time-division multiplexing, comparator, mixed-signal
20	Benoit Provost, Edgar Sánchez-Sinencio, Anna Maria Brosa	A Unified Approach for a Time-Domain Built-In Self-Test Technique and Fault Detection.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	NGCC amplifier, BIST, Fault-coverage, Analog testing, Time-domain
20	Ananta K. Majhi, Vishwani D. Agrawal	Mixed-Signal Test.	VLSI Design	1998	DBLP DOI BibTeX RDF	a survey of mixed-signal testing, tools and methods for mixed-signal test, Analog test
20	Bapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi	Pseudoduplication - An ACOB Technique for Single-Ended Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF	pseudoduplication, ACOB, analog circuit observer block, single-ended switched capacitor filter, data duplication code, simulation, fault detection, layout, design for test, switched capacitor filters
20	Robert M. Gray, Richard A. Olshen, D. Ikeda, Pamela C. Cosman, Sharon M. Perlmutter, Cheryl L. Nash, Keren Perlmutter	Evaluating quality and utility in digital mammography.	ICIP	1995	DBLP DOI BibTeX RDF	digital mammography utility, digital mammography quality evaluation, scientists, insurance companies, lawyers, computer-aided diagnostic methodology, clinical experiments, data compression, image enhancement, medical image processing, engineers, regulators, reviews, quality control, protocols design, administrators, medical diagnostic imaging, lossy compression, diagnostic radiography, patients, analogue-digital conversion, analog-to-digital conversion
20	Isaac Rosenhouse, Anthony J. Weiss	Combined Analog and Digital Error-Correcting Codes For Analog Information Sources.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
20	Isaac Rosenhouse, Anthony J. Weiss	Combined Analog and Digital Error-Correcting Codes for Analog Information Sources.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
19	Kenneth S. Kundert, Henry Chang	Model-based functional verification.	DAC	2010	DBLP DOI BibTeX RDF
19	Zhuizhuan Yu, Sebastian Hoyos, Brian M. Sadler	Mixed-signal parallel compressed sensing and reception for cognitive radio.	ICASSP	2008	DBLP DOI BibTeX RDF
19	Ye Li, Bertan Bakkaloglu, Chaitali Chakrabarti	A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
19	David M. Baylon	On the Detection of Temporal Field Order in Interlaced Video Data.	ICIP (6)	2007	DBLP DOI BibTeX RDF
19	Pedro Tejera, Wolfgang Utschick	Feedback of Channel State Information in Wireless Systems.	ICC	2007	DBLP DOI BibTeX RDF
19	Paolo Maffezzoni, Lorenzo Codecasa, Dario D'Amore	Event-Driven Time-Domain Simulation of Closed-Loop Switched Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
19	Ewout Martens, Georges G. E. Gielen	Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
19	Ashkan Olyaei, Roman Genov	Algorithmic Delta-Sigma-modulated FIR filter.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Gordon Allan, John Knight, Norman M. Filiol, Tom A. D. Riley	Digitally Place and Routed Up-converting Bandpass DAC.	CCECE	2006	DBLP DOI BibTeX RDF
19	Sheldon X.-D. Tan	A general hierarchical circuit modeling and simulation algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
19	Ying Song, Yu Gong, Sen M. Kuo	A robust hybrid feedback active noise cancellation headset.	IEEE Trans. Speech Audio Process.	2005	DBLP DOI BibTeX RDF
19	Bo Hu, Zhao Li, Lili Zhou, C.-J. Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe	Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
19	Kazuhiro Shimonomura, Tetsuya Yagi	A 100×100 pixels orientation-selective multi-chip vision system.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
19	Rafal Karakiewicz, Roman Genov	Minimal activity mixed-signal VLSI architecture for real-time linear transforms in video.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
19	Shaolei Quan, Meng-Yao Liu, Chin-Long Wey	Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress.	DFT	2005	DBLP DOI BibTeX RDF
19	Adão Antônio de Souza Jr., Luigi Carro	Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs.	DATE	2004	DBLP DOI BibTeX RDF
19	Eugenio Culurciello, Andreas G. Andreou	An 8-bit, 1mW successive approximation ADC in SOI CMOS.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
19	Ari Paasio, Mika Laiho, Asko Kananen, Kari Halonen, Jonne Poikonen	A 32×32 cellular test chip targeting new functionalities.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
19	Jung Hyun Choi, Sergio Bampi	OTA Amplifiers Design on Digital Sea-of-Transistors Array.	DATE	1999	DBLP DOI BibTeX RDF
19	Paul E. Hasler, Bradley A. Minch, Chris Diorio	Floating-gate devices: they are not just for digital memories any more.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
19	Keith Hanna	Reasoning about Imperfect Digital Systems.	Prospects for Hardware Foundations	1998	DBLP DOI BibTeX RDF
19	Gert Cauwenberghs	Bit-serial bidirectional A/D/A conversio.	ARVLSI	1995	DBLP DOI BibTeX RDF	digital-analogue conversion, bidirectional bit-serial convertor, algorithmic DAC conversion, successive approximation ADC, D/A conversion, fault-tolerant VLSI architecture, matched monotonic characteristics, 200 muW, 20 mus, VLSI, CMOS integrated circuits, analogue-digital conversion, integrated circuit reliability, A/D conversion, 2 micron, CMOS process
19	Gilbert P. Hyatt, Gene Ohlberg	Electrically alterable digital differential analyzer.	AFIPS Spring Joint Computing Conference	1968	DBLP DOI BibTeX RDF
18	Stephen K. Sunter, Aubin Roy	A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution.	ETS	2011	DBLP DOI BibTeX RDF	mixed-signal DFT, analog bus, mixed-signal BIST
18	Naoki Sugiyama, Hiroshi Noto, Yoshito Nishigami, Ryosuke Oda, Takao Waho	A Low-Power Successive Approximation Analog-to-Digital Converter Based on 2-Bit/Step Comparison.	ISMVL	2010	DBLP DOI BibTeX RDF	successive approximation, low-power, analog-to-digital converter, multiple-valued
18	Amlan Ghosh, Rob Franklin, Richard B. Brown	Analog Circuit Design Methodologies to Improve Negative-Bias Temperature Instability Degradation.	VLSI Design	2010	DBLP DOI BibTeX RDF	analog circuit design methodologies, input switching, NBTI, body biasing
18	Ahmad Tahmasebi, Arash Kamali, Hossein Balazadeh Bahar, Ziaeddin Daie Koozeh Kanani	A Fully Digital Background Calibration Technique for Pipeline Analog-to-Digital Converters.	ICSAP	2009	DBLP DOI BibTeX RDF	digital calibration, pipeline converters, Analog to digital converter (ADC)
18	Vladimir A. Zivkovic, Frank van der Heyden, Guido Gronthoud, Frans G. M. de Jong	Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based Design.	ETS	2008	DBLP DOI BibTeX RDF	Modular Test, Analog Test, Test Architecture
18	Gordon W. Roberts, Mohammed Ali-Bakhshian	Time-domain analog signal processing techniques.	SBCCI	2008	DBLP DOI BibTeX RDF	time-domain analog signal processing, process variation
18	Lelia Festila, Lorant Andras Szolga, Mihaela Cirlugea, Robert Groza	Analog Multiplying/Weighting VLSI Cells for SVM Classifiers.	KES (3)	2008	DBLP DOI BibTeX RDF	weighting circuits, th domain, square-root domain, current controlled amplifiers, analog multipliers
18	Koudai Hiratsuka, Kazuhiro Kondo, Kiyoshi Nakagawa	On the Accuracy of Estimated Synchronization Positions for Audio Digital Watermarks Using the Modified Patchwork Algorithm on Analog Channels.	IIH-MSP	2008	DBLP DOI BibTeX RDF	Patchwork method, Analog channels, Synchronization, Digital Watermarks, Audio signal
18	Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten	Algorithms for automatic length compensation of busses in analog integrated circuits.	ISPD	2007	DBLP DOI BibTeX RDF	analog routing, length compensation, net bundles, paired nets, virtual terminals, routing, EDA, RF, bus routing, IC-layout
18	José Pineda de Gyvez, Guido Gronthoud, Rashid Amine	Multi-VDD Testing for Analog Circuits.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	VDD, ramp, test, analog, IDDQ
18	Haralampos-G. D. Stratigopoulos, Yiorgos Makris	Generating decision regions in analog measurement spaces.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	implicit functional test, neural networks, analog circuits
18	Saurabh K. Tiwary, Rob A. Rutenbar	Scalable trajectory methods for on-demand analog macromodel extraction.	DAC	2005	DBLP DOI BibTeX RDF	trajectory method, analog, SPICE, circuit, macromodel
18	Daniel Mueller 0001, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann	Deterministic approaches to analog performance space exploration (PSE).	DAC	2005	DBLP DOI BibTeX RDF	performance space exploration, pareto optimization, analog integrated circuits, fourier motzkin elimination
18	Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri	A high level language for pre-layout extraction in parasite-aware analog circuit synthesis.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	MSL, pre-layout extraction, parasitics, analog VLSI
18	Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei	A low-power design methodology for high-resolution pipelined analog-to-digital converters.	ISLPED	2003	DBLP DOI BibTeX RDF	low-power design, operational amplifiers, pipelined analog-to-digital converters
18	Jincheol Yoo, Daegyu Lee, Kyusun Choi, Jongsoo Kim	A power and resolution adaptive flash analog-to-digital converter.	ISLPED	2002	DBLP DOI BibTeX RDF	TIQ comparator, flash ADC, inverter quantization, adaptive, threshold, analog-to-digital converter
18	Mandeep Singh, Israel Koren	Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs).	ISQED	2002	DBLP DOI BibTeX RDF	Fault sensitivity, Alpha particle, Fault tolerance, Reliability, Transient faults, Analog-to-Digital Converters
18	Mustapha Slamani, Karim Arabi	Reducing Test Time in the High-Volume Production of Analog Circuits using Efficient Test-Vector Generation and Interpolation Techniques.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	analog circuits testing, interpolation technique, sensitivity analysis, frequency domain analysis, test vectors generation
18	Sree Ganesan, Ranga Vemuri	Technology Mapping and Retargeting for Field-Programmable Analog Arrays.	DATE	2000	DBLP DOI BibTeX RDF	Rapid prototyping Field-programmable analog arrays, Technology Mapping, Retargeting, FPAA
18	Madhu K. Iyer, Michael L. Bushnell	Effect of Noise on Analog Circuit Testing.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	analog test generation, noise analysis
18	Martin H. Levin	Use of a soundcard in teaching audio frequency and analog modem communications.	ITiCSE	1999	DBLP DOI BibTeX RDF	analog telephone systems, dual tone multiple frequencies, soundcards, telephone modems, visual pictorization, handshakes
18	Francis G. Wolff, Michael J. Knieser, Daniel J. Weyer, Christos A. Papachristou	Using codesign techniques to support analog functionality.	CODES	1999	DBLP DOI BibTeX RDF	design methodologies, analog, hardware/software codesign
18	Markus Wolf 0001, Ulrich Kleine	Automatic Topology Optimization for Analog Module Generators.	DATE	1998	DBLP DOI BibTeX RDF	optimization, layout, analog, module generators
18	Todd Hinck, Allyn E. Hubbard	Image Edge Enhancement, Dynamic Compression and Noise Suppression using Analog Circuit Processing.	ARVLSI	1997	DBLP DOI BibTeX RDF	Silicon Retina, Image Edge Enhancement, Neural Network, Spatial Filtering, Analog VLSI
18	Cheng-Ping Wang, Chin-Long Wey	Test Generation Of Analog Switched-Current Circuits.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	switched current circuits, analog switched-current circuits, current switches, voltage switches, noncatastrophic faults, transistor switches, full testability, current copiers, stray inductance, CMOS switch, BIST design, fault model, circuit simulation, macromodel, switched-capacitor circuits, test sequence generation, catastrophic faults
18	Diego Vázquez, Adoración Rueda, José L. Huertas	A solution for the on-line test of analog ladder filters.	VTS	1995	DBLP DOI BibTeX RDF	ladder filters, analog ladder filters, stability problems, design for test methodology, solution feasibility, analogue ICs, integrated circuit testing, design for testability, on-line testing, analogue integrated circuits, active filters, active filters, circuit stability
18	György Turán, Farrokh Vatan	On the Computation of Boolean Functions by Analog Circuits of Bounded Fan-in (Extended Abstract)	FOCS	1994	DBLP DOI BibTeX RDF	explicit nonlinear lower bounds, computation of Boolean functions, bounded fan-in, real-valued functions, sign-representation, n-variable function, piecewise linear circuits, complexity, upper bounds, nondeterminism, analog circuits
18	David Blair Kirk, Alan H. Barr	Implementing rotation matrix constraints in Analog VLSI.	SIGGRAPH	1993	DBLP DOI BibTeX RDF	constraint solution, adaptive, interaction, VLSI, robotics, animation, CMOS, analog, rotation
18	Nenad Marovac	Sieve Method for Real-Time Computer-Aided Extraction of Multivalued Analog Signals in the Presence of Noise.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	Analog signals, computer-aided signal processing, real time, noise
18	Art Lew	On Analog Computer Generation of Continuous Functions.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	analytic function generation, differential approximation, Bessel functions, Analog computation
18	Granino A. Korn, Robert Vichnevetsky	Analog/Hybrid Computation and Digital Simulation.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	Continuous-system simulation, analog/hybrid computation, simulation, interactive computers
17	Zheng Liu, Lihong Zhang	Performance-constrained template-driven retargeting for analog and RF layouts.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	optimization, performance, layout, retargeting, parasitics
17	Nobuyuki Itoh, Mototsugu Hamada	RF-analog circuit design in scaled SoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
17	Linfu Xiao, Evangeline F. Y. Young	Analog placement with common centroid and 1-D symmetry constraints.	ASP-DAC	2009	DBLP DOI BibTeX RDF
17	Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya	Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit.	ASP-DAC	2009	DBLP DOI BibTeX RDF
17	Jonathan W. Mills	Awakening the Analogue Computer: Rubel's Extended Analog Computer Workshop.	UC	2009	DBLP DOI BibTeX RDF
17	Rui He, Lihong Zhang	Artificial neural network application in analog layout placement design.	CCECE	2009	DBLP DOI BibTeX RDF
17	Zheng Liu, Lihong Zhang	Performance-constrained parasitic-aware retargeting and optimization of analog layouts.	CCECE	2009	DBLP DOI BibTeX RDF
17	Shubhankar Basu, Balaji Kommineni, Ranga Vemuri	Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space.	VLSI Design	2009	DBLP DOI BibTeX RDF
17	Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu	Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
17	Rafael Castro-López, Oscar Guerra, Elisenda Roca, Francisco V. Fernández 0001	An Integrated Layout-Synthesis Approach for Analog ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
17	Reza Hashemian	Use of local biasing in designing analog integrated circuits.	EIT	2008	DBLP DOI BibTeX RDF
17	Chadi Abou-Rjeily, Georges El-Howayeck	A simple analog space-time coded Transmitted-Reference MIMO UWB transceiver.	PIMRC	2008	DBLP DOI BibTeX RDF
17	Motoji Yamamoto, Takeshi Ikeda, Yoshinobu Sasaki	Real-time analog input device using breath pressure for the operation of powered wheelchair.	ICRA	2008	DBLP DOI BibTeX RDF
17	Petru Bogdan Bacinschi, Tudor Murgan, Klaus Koch, Manfred Glesner	An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs.	DATE	2008	DBLP DOI BibTeX RDF
17	Almitra Pradhan, Ranga Vemuri	Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches.	DATE	2008	DBLP DOI BibTeX RDF
17	Guo Yu, Peng Li 0001	Yield-aware hierarchical optimization of large analog integrated circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
17	Trent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert	Automated extraction of expert knowledge in analog topology selection and sizing.	ICCAD	2008	DBLP DOI BibTeX RDF
17	Peng Gao, Trent McConaghy, Georges G. E. Gielen	Importance sampled circuit learning ensembles for robust analog IC design.	ICCAD	2008	DBLP DOI BibTeX RDF
17	Boris Murmann, Christian Vogel 0001, Heinz Koeppl	Digitally enhanced analog circuits: System aspects.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Guillaume Ferré, Maher Jridi, Lilian Bossuet, Bertrand Le Gal, Dominique Dallet	A new orthogonal online digital calibration for time-interleaved analog-to-digital converters.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Csaba Petre, Craig Schlottmann, Paul E. Hasler	Automated conversion of Simulink designs to analog hardware on an FPAA.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Stephen Pfetsch, Tamer Ragheb, Jason N. Laska, Hamid Nejati, Anna C. Gilbert, Martin Strauss 0001, Richard G. Baraniuk, Yehia Massoud	On the feasibility of hardware implementation of sub-Nyquist random-sampling based analog-to-information conversion.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Yukiya Miura, Jiro Kato	Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling.	DFT	2008	DBLP DOI BibTeX RDF