Search results for "circuit"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal	A STAFAN-like functional testability measure for register-level circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
18	Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita	Transistor leakage fault location with ZDDQ measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	field effect transistor circuits, transistor leakage fault location, I/sub DDQ/ measurement, equivalence fault collapsing, diagnosed faults, gate-array circuit, fault diagnosis, logic testing, random tests, fault location, CMOS logic circuits, leakage currents, logic arrays, CMOS circuit, deterministic tests, electric current measurement, diagnostic resolution
18	Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita	Power analysis and low-power scheduling techniques for embedded DSP software.	ISSS	1995	DBLP DOI BibTeX RDF	circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor
18	Robert Spence, Lisa Tweedie, Huw Dawkes, Hua Su	Visualization for functional design.	INFOVIS	1995	DBLP DOI BibTeX RDF	visualisation tools, Influence Explorer, Prosection Matrix, engineering artifact design, electronic circuit design, user interfaces, CAD, optimisation, interactive systems, data visualisation, circuit CAD, interactive display, manufacturing process, engineering graphics, functional design
18	Claudio Truzzi, Eric Beyne, Edwin Ringoot, J. Peeters	Signal propagation in high-speed MCM circuits.	ICCD	1995	DBLP DOI BibTeX RDF	thin film circuits, signal propagation, high-speed MCM circuits, thin-film multichip module substrate, timing analyses, lossy interconnection lines, timing, circuit analysis computing, circuit simulations, CMOS integrated circuits, CMOS integrated circuits, multichip modules, receivers, drivers, microsystems, substrates
18	Manish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain	Extraction of finite state machines from transistor netlists by symbolic simulation.	ICCD	1995	DBLP DOI BibTeX RDF	finite state machine extraction, transistor netlists, clock level finite state machines, gate level representation, circuit clocking, output timing, simulation patterns, next state, output function, equivalent FSM, static storage structures, time multiplexed inputs, time multiplexed outputs, finite state machines, logic design, logic CAD, circuit analysis computing, FSMs, symbolic simulation, symbolic simulator, Ordered Binary Decision Diagrams
18	Steven Parkes, Prithviraj Banerjee, Janak H. Patel	A parallel algorithm for fault simulation based on PROOFS .	ICCD	1995	DBLP DOI BibTeX RDF	fault partitioning, dynamic partitioning schemes, compute intensive task, integrated circuit design process, rapid design turn around, ProperPROOFS, parallel extension, PROOFS fault simulation package, distributed method, fault redistribution, ISCAS-89 benchmark set, high performance serial fault simulation applications, parallel algorithms, parallel algorithm, parallel architectures, parallel architectures, fault diagnosis, logic testing, sequential circuits, sequential circuits, circuit analysis computing, logic partitioning
18	Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller	Emulation verification of the Motorola 68060.	ICCD	1995	DBLP DOI BibTeX RDF	emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level
18	Michael S. Hsiao, Janak H. Patel	A new architectural-level fault simulation using propagation prediction of grouped fault-effects.	ICCD	1995	DBLP DOI BibTeX RDF	architectural-level fault simulation, propagation prediction, grouped fault-effects, fault effects, intelligent propagation prediction, automated behavioral simulation, ALFSIM, Architectural Level Fault Simulation, gate level fault simulation, VLSI, fault diagnosis, circuit analysis computing, stuck at faults, integrated circuit design, deterministic algorithm, data types, symbolic data, architectural level
18	Huy Nguyen 0001, Abhijit Chatterjee	OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositions.	ARVLSI	1995	DBLP DOI BibTeX RDF	linear network synthesis, OPTIMUS program, linear circuits, shift-and-add decomposition, behavioral synthesis tool, architectural transformations, numerical matrix transformation algorithms, number-splitting transformation, optimization, high level synthesis, multiplications, circuit CAD, circuit optimisation, matrix decomposition
18	David E. Long, Mahesh A. Iyer, Miron Abramovici	Identifying sequentially untestable faults using illegal states.	VTS	1995	DBLP DOI BibTeX RDF	sequentially untestable faults, illegal states, FILL algorithm, FUNI algorithm, functional partitioning procedure, incremental building, fault diagnosis, logic testing, test generator, integrated circuit testing, sequential circuits, automatic testing, binary decision diagrams, synchronous sequential circuit, logic partitioning, partial solution
18	Mohamed Soufi, Yvon Savaria, Bozena Kaminska	On the design of at-speed testable VLSI circuits.	VTS	1995	DBLP DOI BibTeX RDF	at-speed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuck-at test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, design-for-testability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique
18	Víctor H. Champac, Joan Figueras	Testability of floating gate defects in sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing
18	Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams	On the decline of testing efficiency as fault coverage approaches 100%.	VTS	1995	DBLP DOI BibTeX RDF	single stuck-at fault model, ISCAS benchmark circuits, nontarget defects, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault coverage, test pattern generation, manufacturing process, test quality, production testing, testing efficiency, circuit sizes
18	Xinghao Chen 0003, Michael L. Bushnell	Generation of search state equivalence for automatic test pattern generation.	VLSI Design	1995	DBLP DOI BibTeX RDF	search state equivalence, current search status, prior search decisions, previously-searched decision spaces, enabling theorem, logic testing, integrated circuit testing, sequential circuits, automatic test pattern generation, automatic testing, search problems, sequential circuit test generation
18	Jason P. Hurst, Adit D. Singh	A differential built-in current sensor design for high speed IDDQ testing.	VLSI Design	1995	DBLP DOI BibTeX RDF	built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices
18	Abu Khari bin A'Ain, A. H. Bratt, A. P. Dorey	Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique.	VLSI Design	1995	DBLP DOI BibTeX RDF	analogue CMOS circuits, power supply voltage control testing technique, floating gate defect exposure, power supply voltage sweep, fault diagnosis, integrated circuit testing, fault detection, fault coverage, integrated circuit modelling, CMOS analogue integrated circuits
18	Daniel D. Harrison, M. P. Weir	High-Speed Triangulation-Based 3-D Imaging with Orthonormal Data Projections and Error Detection.	IEEE Trans. Pattern Anal. Mach. Intell.	1990	DBLP DOI BibTeX RDF	surface topography measurement, triangulation-based 3-D imaging, orthonormal data projections, charge-injection-device image sensor, laser-based investigation system, printed-circuit board inspection, laser beam applications, surface topography measurement, computer vision, error detection, inspection, CCD image sensors, CCD image sensors, printed circuit testing
17	Wei Zhang, Bao-Lin Nie, Jinping Wang, Enbo Liu, Jiabao Wang, Pingan Du	A highly accurate and robust source reconstruction method of printed circuit boards based on complex-valued neural network.	Int. J. Circuit Theory Appl.	2024	DBLP DOI BibTeX RDF
17	Fan Yang, Zhanguo Li, Yuehang Xu	An improved harmonics suppression power amplifier circuit using integrated self-resonant capacitor for radar application.	Int. J. Circuit Theory Appl.	2024	DBLP DOI BibTeX RDF
17	Song Wang, Wei Wang, Fei Xie, Shengxuan Qiu, Fengye Yang	Cut-set matrix methods for frequency response analysis curves of lumped parameter equivalent circuit model of three-winding power transformer.	Int. J. Circuit Theory Appl.	2024	DBLP DOI BibTeX RDF
17	Jiawei Zeng, Shunli Wang 0002, Wen Cao, Mengyun Zhang, Carlos Fernandez, Josep M. Guerrero	Improved fractional-order hysteresis-equivalent circuit modeling for the online adaptive high-precision state of charge prediction of urban-electric-bus lithium-ion batteries.	Int. J. Circuit Theory Appl.	2024	DBLP DOI BibTeX RDF
17	Ge Qi, Zhenfan Bu, Shuai Xu, Xiaochang Jiang	Equivalent circuit modeling and optimization design for a novel double-stator linear-rotary switched reluctance motor.	Int. J. Circuit Theory Appl.	2024	DBLP DOI BibTeX RDF
17	Mostafa Noohi, Amin Faraji, Sayed Alireza Sadrossadat, Ali Mirvakili, Ali Moftakharzadeh	Modeling and implementation of a novel active voltage balancing circuit using deep recurrent neural network with dropout regularization.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Prema Kumar Govindaswamy, Raviteja Kammari, Vijaya Sankara Rao Pasupureddi	An adaptive link training based hybrid circuit topology for full-duplex on-chip interconnects.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Yu Tang 0004, Baolin Zhao, Zhe Shi, Lin Jiang, Yun Zhang	LLC resonant converter based on PFM and secondary-side short-circuit control for on-board charger.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Antonino M. Sommariva, Marco Dalai	Refined asymptotic analysis of the two-capacitor circuit.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Tian Zhao, JiaHao Wei, BiJia Lan, Qing Peng, Jing Wan	A unified black-box macro model for analog circuit based on artificial neural network.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Selma Dilek, Suleyman Tosun, Alperen Cakin	Simulated annealing-based high-level synthesis methodology for reliable and energy-aware application specific integrated circuit designs with multiple supply voltages.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Baltazar Cerda, Isaac Campos-Cantón, Finees Delgado-Aranda, Carlos Soubervielle-Montalvo, Edgar Tristán-Hernández	Sixteen logic functions in a single electronic circuit.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Lin Wang, Yong Chen 0005, Chaowei Yang, Xionghui Zhou, Mei Han, Paolo Stefano Crovetti, Pui-In Mak, Rui Paulo Martins	A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Xiaobing Zhang, Guohua Zhou, Shuyi Liu	Equalization circuit based on switched-capacitor units and graph networks for series-connected cell strings.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Naorem Yaipharenba Meitei, Krishna Lal Baishnab, Gaurav Trivedi	Fast power density aware three-dimensional integrated circuit floorplanning for hard macroblocks using best operator combination genetic algorithm.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Hsien-Yuan Hsu, Tzu-Yang Lo, Min-Fu Hsieh	A simple signal extraction-based online real-time diagnosis approach for interturn short-circuit fault of permanent magnet motor.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Jie Zhang 0097, Jing Yang, Longhao Xu, Xiaopeng Zhu	The circuit realization of a fifth-order multi-wing chaotic system and its application in image encryption.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Quang-Manh Duong, Quang-Kien Trinh, Van-Tinh Nguyen, Dinh-Ha Dao, Luong Duy Manh, Van-Phuc Hoang, Longyang Lin, Chacko John Deepu	A low-power charge-based integrate-and-fire circuit for binarized-spiking neural network.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Yahu Gao, Yu Tang 0004, Jiarong Kan, Zhe Shi, Hongjing Liu, Jincai Niu, Donghao Tian	Phase-shifted full-bridge converter based on an adjustable current auxiliary circuit with full load range ZVS and small duty cycle loss.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Michelle Sern Mi Lim, Kim Heng Yeo, Sawal Hamid Md. Ali	An optimal power management circuit with a dynamic subthreshold start-up for thermal energy harvesting.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Doaa K. Abdelrahman, Mohammed E. Fouda, Ihsen Alouani, Lobna A. Said, Ahmed G. Radwan	Ternary SRAM circuit designs with CNTFETs.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Emre Özer 0002	A new electronically tunable mutually coupled circuit using current conveyor transconductance amplifiers (CCTAs).	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Abidur Rahaman, Apurba Adhikary, Mohammad Amzad Hossain, Md Mobaidul Islam, Jin Jang	Enhanced current mirror circuit by dual-gate coplanar amorphous InGaZnO TFTs.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Hamed Aminzadeh	Subthreshold reference circuit with curvature compensation based on the channel length modulation of MOS devices.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Muzaffer Ates	Circuit theory approach to stability and passivity analysis of nonlinear dynamical systems.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Reza Daie Koozehkanani, Somaye Makouei, Siroos Toofan	Improved loop stability approach in fully differential operational transconductance amplifier with common-mode feedback circuit.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Ekrem Cengelci, Muhammet Garip, Ahmed S. Elwakil	Fractional-order controllers for switching DC/DC converters using the K-factor method: Analysis and circuit realization.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Zhixia Ding, Ting Su, Sai Li 0002, Le Yang	Memristor-based circuit design of continuously adjustable direct-current voltage source.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Zhenyu Wu, Chaoqun Peng, Jiao Liao, Quanxiu Chen	Study on circuit modeling of stretchable serpentine interconnects.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Chunling Hao, Faqiang Wang	Design method and implementation of the fractional-order inductor and its application in series-resonance circuit.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Siona Menezes Picardo, Jani Babu Shaik, Sonal Singhal, Nilesh Goel	Enabling efficient rate and temporal coding using reliability-aware design of a neuromorphic circuit.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Farid Mohammadi, Hasan Rastegar, Mohammad Pichan	Circuit design and implementation of fault-tolerant step-up converter with variable voltage gain.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Blaise Ravelo, Wenceslas Rahajandraibe, Mathieu Guerin, Benoît Agnus, Preeti Thakur, Atul Thakur	130-nm BiCMOS design of low-pass negative group delay integrated RL-circuit.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Sofia Fenni, Fayrouz Haddad, Antonio Jaomiary, Samar S. Yazdani, Frank Elliot Sahoa, Lucius Ramifidisoa, Mathieu Guerin, Wenceslas Rahajandraibe, Blaise Ravelo	Investigation on four-port mono-capacitor circuit with high-pass negative group delay behavior.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Rahmatullah Ibrahim Nuruddeen, José Francisco Gómez-Aguilar, Abdulaziz Garba Ahmad, Khalid K. Ali	Investigating the dynamics of Hilfer fractional operator associated with certain electric circuit models.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Zainab Aizaz, Kavita Khare	Energy efficient approximate booth multipliers using compact error compensation circuit for mitigation of truncation error.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Armineh Dastgiri, Majid Hosseinpour, Farzad Sedaghati, Seyed Reza Mousavi-Aghdam	A high step-up DC-DC converter with active switched LC-network and voltage-lift circuit: Topology, operating principle, and implementation.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Wei-Cheng Lin, Ming-Chiu Chang, Chien-Hung Liao, Chun-Ting Hsieh	Design of 0.1-mV zero-g and 200-μg/√Hz capacitance accelerometer with high sensitivity readout circuit with time-to-digital convertor applied to finger tremor of neurodegenerative disease.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
17	Mohammad Hossein Rezaei, Mahdi Akhbari	An active parallel power decoupling circuit with a dual loop control scheme for micro-inverters.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Zhimeng Liu, Lifang Wang, Chengxuan Tao, Shufan Li, Yanjie Guo, Fang Li	Analysis and design of wireless power transfer system based on inductor-capacitor-capacitor/none magnetic integration compensation circuit.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Ahmadali Ashrafian, Mahmoud Mohammad-Taheri, Mohammad Naser-Moghaddasi, Mehdi Khatir, Behbod Ghalamkari	Planar circuit analysis of ultra-wideband millimeter-wave inductor using transmission line sections.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Pratikanta Mishra, Atanu Banerjee, Mousam Ghosh, Sushanta Gogoi, Rukmi Dutta	Development of a cost-effective circuit hardware architecture for brushless direct current motor driver.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Qingjian Li, Yan Liang 0005, Zhenzhou Lu, Guangyi Wang	Threshold-type memristor-based memory circuit.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Léandre Kamdjeu Kengne, Yannick Pascal Kamdeu Nkandeu, Justin Roger Mboupda Pone, Alain Tiedeu, Hilaire Bertrand Fotsin	Image encryption using a novel quintic jerk circuit with adjustable symmetry.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Saleh Abdel-Hafeez, Ann Gordon-Ross	Reconfigurable FIFO memory circuit for synchronous and asynchronous communication.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Marek Nalecz	A unified approach to autonomous and nonautonomous models of circuit elements.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Mohammad Moradinezhad Maryan, Majid Amini Valashani, Seyed Javad Azhari	An input controlled leakage restrainer transistor-based technique for leakage and short-circuit power reduction of 1-bit hybrid full adders.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Bernardo Tellini, Mauro Bologna, Kristopher J. Chandia, Massimo Macucci	Revisiting the memristor concept within basic circuit theory.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Michael Günther 0005, Andreas Bartel, Birgit Jacob, Timo Reis	Dynamic iteration schemes and port-Hamiltonian formulation in coupled differential-algebraic equation circuit simulation.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Rohollah Abdollahi, Ehsan Badfar	Harmonics mitigation approach by using pulse-doubling circuit in the AC-DC rectifier.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Ömer Yildirim, Ibrahim Bozyel, Kubra Saka, Temel Kayikçioglu, Dinçer Gökcen	Polydimethylsiloxane-based capacitive motion sensor and its read-out circuit.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Francisco G. Montoya, Raúl Baños, Alfredo Alcayde, Francisco Manuel Arrabal-Campos	Geometric Algebra for teaching AC Circuit Theory.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Qiang Fu, Qing Guo, Wei Zhang 0095, Weimin Cui, Ling Zhao	An analytical model for squirrel cage induction machine with broken rotor bars derived based on the multiple coupled circuit theory and the winding function approach.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Kaushal Kishore, Nidhi Chaturvedi, SA Akbar	Auto-clamping interface circuit for high electron mobility transistor-based heavy metal detection sensor.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Karlheinz Ochs, Sebastian Jenderny	An equivalent electrical circuit for the Hindmarsh-Rose model.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Renyun Jin, Haifeng Qiu, Liguo Weng, Bin Yu, Jie Chen, Yanghui Zhang	Circuit system based on cloud edge fusion and outdoor intelligent light networking.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
17	Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi	Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
17	Masood Teymouri	A multipurpose circuit to read out and digitize pixel signal for low-power CMOS imagers.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
17	Arjun Kumar Joginipelly, Dimitrios Charalampidis	An efficient circuit for error reduction in logarithmic multiplication for filtering applications.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
17	Abhilash Tirupathi, Kirubakaran Annamalai, Veeramraju Tirumala Somasekhar	A three-phase inverter circuit using half-bridge cells and T-NPC for medium-voltage applications.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
17	Antonino M. Sommariva	Fractionability of circuit components.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
17	Jingfang Wang, Xuliang Yao, Qi Guan, Shiyan Yang	A novel 12-pulse full-wave rectifier with simple circuit configuration.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
17	Ridvan Umaz	Efficient power management circuit for biomass-based energy harvesting system.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
17	Megavarna Ezhilarasu Pitchaimuthu, Kathamuthu Thamilmaran	Dynamics of the forced negative conductance series LCR circuit.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
17	Weiming Chen, Weiguo Lu, Xi Wang	Circuit modeling and efficiency analysis for wireless power transfer system with shielding.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
17	Noemen Ammar, Henri Baudrand	The wave concept iterative process (WCIP) method for electrical circuit network with triangular and hexagonal topology.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
17	Tommaso Addabbo, Ada Fort, Marco Mugnaini, Nicola Petra, Hadis Takaloo, Valerio Vignoli	Self-tunable chaotic true random bit generator in current-mode CMOS circuit with nonlinear distortion analysis.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
17	Amir Reza Siminfar, Omid Shoaei	A comprehensive circuit model for evaluating the response of silicon photomultipliers in continuous wave light regime.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
17	Xiaoyun Zhong, Minfang Peng, Mohammad Shahidehpour	Creation and circuit implementation of two-to-eight-wing chaotic attractors using a 3D memristor-based system.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
17	Brent J. Maundy, Ahmed S. Elwakil, Stephan J. G. Gift	Enhancing the improved Howland circuit.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
17	Aida Todri-Sanial, Xueqing Li, Juan Núñez 0002	Emerging technologies and computing paradigms for the Internet of Everything applications. International Journal of Circuit, Theory, and Applications.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
17	Francesco Ferranti, Daniele Romano, Giulio Antonini	On the passivity of the quasi-static partial element equivalent circuit method.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
17	Óscar Pereira-Rial, Paula López 0001, Juan M. Carrillo, Víctor M. Brea 0001, Diego Cabello	Ultralow power voltage reference circuit for implantable devices in standard CMOS technology.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
17	Caio M. de Miranda, Sérgio Francisco Pichorim, Paulo José Abatti	On the impact of relay circuit losses in four-coil wireless power transfer systems.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
17	Jing Wang, Wenxin Yu, Junnian Wang, Yanming Zhao, Jing Zhang, Dan Jiang	A new six-dimensional hyperchaotic system and its secure communication circuit implementation.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
17	Bulent Nafi Örnek, Timur Duzenli	Schwarz lemma for driving point impedance functions and its circuit applications.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
17	Dominik Baumann, Alon Ascoli, Ronald Tetzlaff, Leon O. Chua, Manfred Hild	Memristor-enhanced humanoid robot control system - Part II: Circuit theoretic model and performance analysis.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF
17	Buncha Munmuangsaen, Banlue Srisuchinwong	A minimum five-component five-term single-nonlinearity chaotic jerk circuit based on a twin-jerk single-op-amp technique.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF
17	Bülent Bilgehan, Ali Özyapici, Zehra Boratas Sensoy	Experimentally approved generalized model for circuit applications.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF
17	Quan Xu 0001, Q. L. Zhang, H. Qian, H. G. Wu, Bocheng Bao	Crisis-induced coexisting multiple attractors in a second-order nonautonomous memristive diode bridge-based circuit.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF
17	Balázs Rakos	Circuit model of photoswitchable proteins.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF
17	Brent Maundy, Ahmed S. Elwakil, Costas Psychalinos	Simple MOS-based circuit designed to show pinched hysteresis behavior.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF