Search results for "scan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
25	Hans-Joachim Hof, Ingmar Baumgart, Martina Zitterbart	Key Exchange for Service Discovery in Secure Content Addressable Sensor Networks.	KiVS	2007	DBLP DOI BibTeX RDF
25	Irith Pomeranz, Sudhakar M. Reddy	Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
25	Xiao Liu 0010, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran	Efficient techniques for transition testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	test chain, test data volume reduction, transition faults, Test application time reduction, yield loss
25	Praveen Parvathala	High Level Test Generation / SW based Embedded Test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
25	Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng	ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values.	ICCD	2005	DBLP DOI BibTeX RDF
25	Prasad Jayanti	An optimal multi-writer snapshot algorithm.	STOC	2005	DBLP DOI BibTeX RDF	fault-tolerant, asynchronous, wait-free, snapshot, lock-free, concurrent algorithm
25	Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase	Test data compression technique using selective don't-care identification.	ASP-DAC	2004	DBLP DOI BibTeX RDF
25	Tilo Gockel, Pedram Azad, Rüdiger Dillmann	Calibration Issues for Projector-based 3D-Scanning.	SMI	2004	DBLP DOI BibTeX RDF	Pattern Projector, 3D Shape Acquisition, Single Shot, Calibration, 3D Scanning, Structured Light
25	Giuseppe Patanè 0001, Michela Spagnuolo	Multi-resolution and slice-oriented feature extraction and segmentation of digitized data.	Symposium on Solid Modeling and Applications	2002	DBLP DOI BibTeX RDF	segmentation, reverse engineering, feature detection
25	Marwan Krunz, George Apostolopoulos	Efficient Support for Interactive Scanning Operations in MPEG-Based Video-on-Demand Systems.	Multim. Syst.	2000	DBLP DOI BibTeX RDF	Video scheduling, Interactive video-on-demand, MPEG, Scanning operations
25	Hsung-Pin Chang, Ruei-Chuan Chang, Ray-I Chang, Wei-Kuan Shih	Enlarged-Maximum-Scannable-Groups for Real-Time Disk Scheduling in a Multimedia System.	COMPSAC	2000	DBLP DOI BibTeX RDF
25	Dilip K. Bhavsar	Testing Interconnections to Static RAMs.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
25	Mathew D. Hunter, Quoc Hao Mach, Ratvinder Singh Grewal 0001	The relationship between scan path direction and cognitive processing.	C3S2E	2010	DBLP DOI BibTeX RDF	QEEG, human-computer interaction, eye tracking, cognitive processing
25	Sobeeh Almukhaizim, Ozgur Sinanoglu	Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
25	Michael Bosse, Robert Zlot	Continuous 3D scan-matching with a spinning 2D laser.	ICRA	2009	DBLP DOI BibTeX RDF
25	Zhanglei Wang, Krishnendu Chakrabarty	Test Data Compression Using Selective Encoding of Scan Slices.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
25	Irith Pomeranz, Sudhakar M. Reddy	Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
25	Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, James Chien-Mo Li	Diagnosis of Multiple Scan Chain Timing Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
25	Lifeng He, Yuyan Chao, Kenji Suzuki 0001	A Run-Based Two-Scan Labeling Algorithm.	IEEE Trans. Image Process.	2008	DBLP DOI BibTeX RDF
25	Jeng-Ji Huang, Sen-Ching Chang	A hybrid channel scan mechanism for improved VoIP handoff performance in 802.11 WLANs.	PIMRC	2008	DBLP DOI BibTeX RDF
25	Fu-Sheng Huang, Kai-Tai Song	Vision SLAM using omni-directional visual scan matching.	IROS	2008	DBLP DOI BibTeX RDF
25	Jia Li 0022, Qiang Xu 0001, Yu Hu 0001, Xiaowei Li 0001	On reducing both shift and capture power for scan-based testing.	ASP-DAC	2008	DBLP DOI BibTeX RDF
25	Jia Li 0022, Xiao Liu 0011, Yubin Zhang, Yu Hu 0001, Xiaowei Li 0001, Qiang Xu 0001	On capture power-aware test data compression for scan-based testing.	ICCAD	2008	DBLP DOI BibTeX RDF
25	Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz	Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells.	DFT	2008	DBLP DOI BibTeX RDF
25	Gaurav Sengar, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury	Secured Flipped Scan-Chain Model for Crypto-Architecture.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
25	Enrique Coiras, Yvan R. Petillot, David M. Lane	Multiresolution 3-D Reconstruction From Side-Scan Sonar Images.	IEEE Trans. Image Process.	2007	DBLP DOI BibTeX RDF
25	Teng Lin, Jianhua Feng, Yangyuan Wang	A New Test Data Compression Scheme for Multi-scan Designs.	ISVLSI	2007	DBLP DOI BibTeX RDF
25	Haruhiko Takeuchi, Yoshiko Habuchi	A Quantitative Method for Analyzing Scan Path Data Obtained by Eye Tracker.	CIDM	2007	DBLP DOI BibTeX RDF
25	Barry Irwin, Jean-Pierre van Riel	Using InetVis to Evaluate Snort and Bro Scan Detection on a Network Telescope.	VizSEC	2007	DBLP DOI BibTeX RDF
25	Hao Fang 0008, Chenguang Tong, Xu Cheng	RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power.	ASP-DAC	2007	DBLP DOI BibTeX RDF
25	Grigorios Chrysos 0001, Apostolos Dollas, Nikolaos G. Bourbakis, J. Sukarno Mertoguno	An Integrated Video Compression, Encryption and Information Hiding Architecture based on the SCAN Algorithm and the Stretch Technology.	FCCM	2007	DBLP DOI BibTeX RDF
25	Vishnu C. Vimjam, M. Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang	Using Scan-Dump Values to Improve Functional-Diagnosis Methodology.	VTS	2007	DBLP DOI BibTeX RDF
25	Kedarnath J. Balakrishnan	Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding.	VLSI Design	2007	DBLP DOI BibTeX RDF
25	Kim T. Le, Dong Hyun Baik, Kewal K. Saluja	Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan.	VLSI Design	2007	DBLP DOI BibTeX RDF
25	Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov	Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture.	VLSI Design	2007	DBLP DOI BibTeX RDF
25	Kaushal Solanki, Upamanyu Madhow, B. S. Manjunath, Shivkumar Chandrasekaran, Ibrahim El-Khalil	'Print and Scan' Resilient Data Hiding in Images.	IEEE Trans. Inf. Forensics Secur.	2006	DBLP DOI BibTeX RDF
25	Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi	Enhancing Delay Fault Coverage through Low Power Segmented Scan.	ETS	2006	DBLP DOI BibTeX RDF
25	Xuan-Lun Huang, Jiun-Lang Huang	A routability constrained scan chain ordering technique for test power reduction.	ASP-DAC	2006	DBLP DOI BibTeX RDF
25	Qianli Zhang, Xing Li	A Hypothesis Testing Based Scalable TCP Scan Detection.	ICOIN	2006	DBLP DOI BibTeX RDF
25	Irith Pomeranz, Sudhakar M. Reddy	Scan-Based Delay Fault Tests for Diagnosis of Transition Faults.	DFT	2006	DBLP DOI BibTeX RDF
25	Adit D. Singh, Gefu Xu	Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing.	VTS	2006	DBLP DOI BibTeX RDF	Hazard-Free, Test, Delay, Transition
25	Kun Young Chung, Sandeep K. Gupta 0001	Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing.	VTS	2006	DBLP DOI BibTeX RDF
25	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards	Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
25	James Chien-Mo Li	Diagnosis of single stuck-at faults and multiple timing faults in scan chains.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
25	Evgeny Artyomov, Yair Rivenson, Guy Levi, Orly Yadid-Pecht	Morton (Z) scan based real-time variable resolution CMOS image sensor.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
25	Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura	Low Power Test Compression Technique for Designs with Multiple Scan Chain.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
25	Shih Ping Lin 0001, Chung-Len Lee 0001, Jwu E. Chen	Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
25	Jheng-Syun Yang, Shi-Yu Huang	Quick Scan Chain Diagnosis Using Signal Profiling.	ICCD	2005	DBLP DOI BibTeX RDF
25	Ganapati P. Patil, Stephen L. Rathbun, Raj Acharya, Pushkar Patankar, Reza Modarres	Upper level set scan statistic system for detecting arbitrarily shaped hotspots for digital governance.	DG.O	2005	DBLP BibTeX RDF	confidence set of hotspots, geosurveillance statistics, hotspot rating, typology of space-time hotspots, prioritization, early warning, hotspot detection, surveillance geoinformatics partnership, decision support for hotspot detection
25	Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz	On Generating Pseudo-Functional Delay Fault Tests for Scan Designs.	DFT	2005	DBLP DOI BibTeX RDF
25	Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda	Should Illinois-Scan Based Architectures be Centralized or Distributed?	DFT	2005	DBLP DOI BibTeX RDF
25	Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos	Scan Cell Ordering for Low Power BIST.	ISVLSI	2004	DBLP DOI BibTeX RDF
25	Baris Arslan, Alex Orailoglu	CircularScan: A Scan Architecture for Test Cost Reduction.	DATE	2004	DBLP DOI BibTeX RDF
25	Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards	Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits.	DATE	2004	DBLP DOI BibTeX RDF
25	Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara	Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
25	Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel	Logic BIST Using Constrained Scan Cells.	VTS	2004	DBLP DOI BibTeX RDF
25	Baris Arslan, Alex Orailoglu	Test Cost Reduction Through A Reconfigurable Scan Architecture.	ITC	2004	DBLP DOI BibTeX RDF
25	Peilin Song, Franco Stellari, Alan J. Weger, Tian Xia	A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current.	ITC	2004	DBLP DOI BibTeX RDF
25	Jeff Rearick, Sylvia Patterson, Krista Dorner	Integrating Boundary Scan into Multi-GHz I/O Circuitry.	ITC	2004	DBLP DOI BibTeX RDF
25	Kedarnath J. Balakrishnan, Nur A. Touba	Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion.	ITC	2004	DBLP DOI BibTeX RDF
25	Yu Huang 0005, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung	Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
25	Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies	Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor.	ICCD	2003	DBLP DOI BibTeX RDF
25	Meng Lu, Yvon Savaria, Bing Qiu 0003, Jacques Taillefer	IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration.	DFT	2003	DBLP DOI BibTeX RDF
25	Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi	Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.	DFT	2003	DBLP DOI BibTeX RDF
25	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains.	ISQED	2003	DBLP DOI BibTeX RDF
25	Manish Sharma, Janak H. Patel, Jeff Rearick	Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture.	VTS	2003	DBLP DOI BibTeX RDF
25	Priyank Kalla, Maciej J. Ciesielski	A comprehensive approach to the partial scan problem using implicitstate enumeration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
25	Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich	Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	store and generate schemes, BIST, test data compression, deterministic BIST
25	Kuen-Jong Lee, Jih-Jeen Chen	Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
25	Holger Bischof, Sergei Gorlatch	Double-Scan: Introducing and Implementing a New Data-Parallel Skeleton.	Euro-Par	2002	DBLP DOI BibTeX RDF
25	Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu	Test Power Reduction through Minimization of Scan Chain Transitions.	VTS	2002	DBLP DOI BibTeX RDF
25	Seongmoon Wang	Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST.	ITC	2002	DBLP DOI BibTeX RDF
25	Tsung-Chu Huang, Kuen-Jong Lee	Reduction of power consumption in scan-based circuits during testapplication by an input control technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
25	Kevin Stanley	High-Accuracy Flush-and-Scan Software Diagnostic.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
25	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan-Based BIST.	IOLTW	2001	DBLP DOI BibTeX RDF
25	Josef Schmid, Timo Schüring, Christoph Smalla	Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow.	ISQED	2001	DBLP DOI BibTeX RDF
25	Irith Pomeranz, Sudhakar M. Reddy	Functional Test Generation for Full Scan Circuits.	DATE	2000	DBLP DOI BibTeX RDF
25	Irith Pomeranz, Sudhakar M. Reddy	On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs.	ICCD	2000	DBLP DOI BibTeX RDF
25	Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone	Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits.	DFT	2000	DBLP DOI BibTeX RDF
25	Makoto Ikeda, Hideyuki Aoki, Kunihiro Asada	DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path.	ISQED	2000	DBLP DOI BibTeX RDF
25	Massimiliano Poletto, Vivek Sarkar	Linear scan register allocation.	ACM Trans. Program. Lang. Syst.	1999	DBLP DOI BibTeX RDF	compilers, register allocation, code optimization
25	Hsing-Chung Liang, Chung-Len Lee	An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
25	Sameer Sharma, Michael S. Hsiao	Partial Scan Using Multi-Hop State Reachability Analysis.	VTS	1999	DBLP DOI BibTeX RDF
25	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin	Partial scan delay fault testing of asynchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	robust path delay fault testing, asynchronous circuits, delay faults, sequential testing
25	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPGs for Faults in Board Level Interconnect via Boundary Scan.	VTS	1997	DBLP DOI BibTeX RDF
25	Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska	STARBIST: Scan Autocorrelated Random Pattern Generation.	DAC	1997	DBLP DOI BibTeX RDF
25	Seongmoon Wang, Sandeep K. Gupta 0001	ATPG for Heat Dissipation Minimization During Scan Testing.	DAC	1997	DBLP DOI BibTeX RDF
25	Dhiraj K. Pradhan, Jayashree Saxena	A novel scheme to reduce test application time in circuits with full scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
25	Chengfu Yao, Jon G. Rokne	Hybrid Scan-Conversion of Circles.	IEEE Trans. Vis. Comput. Graph.	1995	DBLP DOI BibTeX RDF
25	Debesh K. Das, Bhargab B. Bhattacharya	Testable design of non-scan sequential circuits using extra logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design
25	Sandip Kundu	Diagnosing scan chain faults.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
25	Jacob Savir, Srinivas Patil	Scan-based transition test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
25	W. David Ballew, Lauren M. Streb	Board-level boundary scan: regaining observability with an additional IC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
25	R. P. van Riessen, Hans G. Kerkhoff, A. Kloppenburg	Designing and Implementing an Architecture with Boundary Scan.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
25	Jon G. Rokne, Brian Wyvill, Xiaolin Wu 0001	Fast line scan-conversion.	ACM Trans. Graph.	1990	DBLP DOI BibTeX RDF
25	Siddhartha Chatterjee, Guy E. Blelloch, Marco Zagha	Scan primitives for vector computers.	SC	1990	DBLP DOI BibTeX RDF
25	Arie E. Kaufman	Efficient algorithms for 3D scan-conversion of parametric curves, surfaces, and volumes.	SIGGRAPH	1987	DBLP DOI BibTeX RDF
25	Subhash C. Agrawal, Jeffrey P. Buzen, Ashok K. Thareja	A Unified Approach to Scan Time Analysis of Token Rings and Polling Networks.	SIGMETRICS	1984	DBLP DOI BibTeX RDF
24	Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability.	ASP-DAC	2006	DBLP DOI BibTeX RDF
24	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences.	VLSI Design	2003	DBLP DOI BibTeX RDF