Search results for "FPGAs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Christian Schuck, Matthias Kühnle, Michael Hübner 0001, Jürgen Becker 0001	A framework for dynamic 2D placement on FPGAs.	IPDPS	2008	DBLP DOI BibTeX RDF
16	Yamuna Rajasekhar, Yashodhan Phatak, Andrew G. Schmidt, William V. Kritikos, Ron Sass	FPGA Session Control (FSC): Providing Remote Access to a Cluster of FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
16	Hanyu Liu, Xiaolei Chen, Yajun Ha	An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects.	FCCM	2008	DBLP DOI BibTeX RDF
16	Karthik Nagarajan, Brian Holland, K. Clint Slatton, Alan D. George	Scalable and Portable Architecture for Probability Density Function Estimation on FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
16	Saar Drimer, Tim Güneysu, Christof Paar	DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
16	Maciej Wielgosz, Ernest Jamro, Kazimierz Wiatr	Highly efficient structure of 64-bit exponential function implemented in FPGAs.	ARC	2008	DBLP DOI BibTeX RDF	HPRC (High Performance Reconfigurable Computing), exponent function, FPGA, elementary function
16	Amit Agarwal, Jason Cong, Brian Tagiku	Fault tolerant placement and defect reconfiguration for nano-FPGAs.	ICCAD	2008	DBLP DOI BibTeX RDF
16	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	Interconnection lengths and delays estimation for communication links in FPGAs.	SLIP	2008	DBLP DOI BibTeX RDF	communciation link, interconnection length prediction, FPGA
16	Mingxuan Yuan, Xiuqiang He 0001, Zonghua Gu 0001	Hardware/Software Partitioning and Static Task Scheduling on Runtime Reconfigurable FPGAs using a SMT Solver.	IEEE Real-Time and Embedded Technology and Applications Symposium	2008	DBLP DOI BibTeX RDF
16	Mark Hammerquist, Roman L. Lysecky	Design space exploration for application specific FPGAS in system-on-a-chip designs.	SoCC	2008	DBLP DOI BibTeX RDF
16	Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, Yasuaki Ito	A Tiny Processing System for Education and Small Embedded Systems on the FPGAs.	EUC (2)	2008	DBLP DOI BibTeX RDF
16	Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong	Place-and-Route Impact on the Security of DPL Designs in FPGAs.	HOST	2008	DBLP DOI BibTeX RDF
16	Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis	Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.	ISQED	2008	DBLP DOI BibTeX RDF	Transistor networks, logic synthesis, BDDs, Logical effort
16	Philippe Bulens, François-Xavier Standaert, Jean-Jacques Quisquater, Pascal Pellegrin, Gaël Rouvroy	Implementation of the AES-128 on Virtex-5 FPGAs.	AFRICACRYPT	2008	DBLP DOI BibTeX RDF
16	Nadia Nedjah, Rodrigo Martins da Silva, Luiza de Macedo Mourelle, Marcus Vinícius Carvalho da Silva	Reconfigurable MAC-Based Architecture for Parallel Hardware Implementation on FPGAs of Artificial Neural Networks.	ICANN (2)	2008	DBLP DOI BibTeX RDF
16	Tim Güneysu, Christof Paar	Ultra High Performance ECC over NIST Primes on Commercial FPGAs.	CHES	2008	DBLP DOI BibTeX RDF	FPGA, High-Performance, Elliptic Curve Cryptosystems
16	Stephen Bijansky, Adnan Aziz	TuneFPGA: post-silicon tuning of dual-Vdd FPGAs.	DAC	2008	DBLP DOI BibTeX RDF	FPGA, delay, process variation, yield, tuning
16	Iván González 0004, Estanislao Aguayo, Sergio López-Buedo	Self-Reconfigurable Embedded Systems on Low-Cost FPGAs.	IEEE Micro	2007	DBLP DOI BibTeX RDF	reconfigurable hardware, real-time and embedded systems, special-purpose and application-based systems, algorithms implemented in hardware
16	Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna	High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	G.1.0.g Parallel algorithms, C.3.e Reconfigurable hardware
16	Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton	Improvements to Technology Mapping for LUT-Based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
16	Akhilesh Kumar, Mohab Anis	Dual-Threshold CAD Framework for Subthreshold Leakage Power Aware FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
16	Li Shang, Robert P. Dick, Niraj K. Jha	SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
16	Mehdi Baradaran Tahoori, Subhasish Mitra	Application-Dependent Delay Testing of FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
16	Antony W. Savich, Medhat Moussa, Shawki Areibi	The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study.	IEEE Trans. Neural Networks	2007	DBLP DOI BibTeX RDF
16	Pritha Banerjee 0001, Susmita Sur-Kolay	Faster Placer for Island-Style FPGAs.	ICCTA	2007	DBLP DOI BibTeX RDF
16	Yan Lin 0001, Lei He 0001	Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, uncertainty, process variation, stochastic, physical synthesis
16	N. Pete Sedcole, Peter Y. K. Cheung	Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis.	FPGA	2007	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modelling, FPGA, delay, reconfiguration, process variation, yield
16	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton	GlitchLess: an active glitch minimization technique for FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	field-programmable gate arrays, power minimization
16	Nathan Woods	Integrating FPGAs in high-performance computing: the architecture and implementation perspective.	FPGA	2007	DBLP DOI BibTeX RDF	compute acceleration, high-performance computinghigh-performance computing, reconfigurable computing, co-processor
16	Satish Sivaswamy, Kia Bazargan	Variation-aware routing for FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	statistical timing analysis, FPGA routing
16	Jin Cui, Qingxu Deng, Xiuqiang He 0001, Zonghua Gu 0001	An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs.	DATE	2007	DBLP DOI BibTeX RDF
16	Andrzej Krasniewski	Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs.	DSD	2007	DBLP DOI BibTeX RDF
16	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
16	Shilpa Bhoj, Dinesh Bhatia	Pre-route Interconnect Capacitance and Power Estimation in FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
16	Satish Sivaswamy, Kia Bazargan	Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
16	Mark Dickinson	System-Level Design for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
16	Jens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario Porrmann	A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
16	Gerald Hempel, Christian Hochberger	A resource optimized SoC Kit for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
16	Timothy F. Oliver, Leow Yuan Yeow, Bertil Schmidt	High Performance Database Searching with HMMer on FPGAs.	IPDPS	2007	DBLP DOI BibTeX RDF
16	Zain-ul-Abdin, Bertil Svensson	A Study of Design Efficiency with a High-Level Language for FPGAs.	IPDPS	2007	DBLP DOI BibTeX RDF
16	João Bispo, Ioannis Sourdis, João M. P. Cardoso, Stamatis Vassiliadis	Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues.	ARC	2007	DBLP DOI BibTeX RDF
16	Rayan Chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton	Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval.	ARC	2007	DBLP DOI BibTeX RDF
16	Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Sudarshan Banerjee	Energy-aware co-processor selection for embedded processors on FPGAs.	ICCD	2007	DBLP DOI BibTeX RDF
16	Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan	CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
16	Henrique C. Freitas, Dalton M. Colombo, Fernanda Lima Kastensmidt, Philippe Olivier Alexandre Navaux	Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
16	Manuel G. Gericota, Luís F. Lemos, Gustavo R. Alves, José M. Ferreira 0001	On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs.	IOLTS	2007	DBLP DOI BibTeX RDF
16	Ben Cope, Peter Y. K. Cheung, Wayne Luk	Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective.	ASAP	2007	DBLP DOI BibTeX RDF
16	Javid Jaffari, Mohab Anis	Thermal-Aware Placement for FPGAs Using Electrostatic Charge Model.	ISQED	2007	DBLP DOI BibTeX RDF
16	Pritha Banerjee 0001, Susmita Sur-Kolay, Arijit Bishnu	Floorplanning in Modern FPGAs.	VLSI Design	2007	DBLP DOI BibTeX RDF
16	Krishnan Ramakrishnan, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin	Impact of NBTI on FPGAs.	VLSI Design	2007	DBLP DOI BibTeX RDF
16	Uday Bondhugula, J. Ramanujam, P. Sadayappan	Automatic mapping of nested loops to FPGAS.	PPoPP	2007	DBLP DOI BibTeX RDF	FPGA compilation, control signals, regular processor arrays, scheduling, FPGA, resource constraints, nested loops, linear transformation
16	Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert Felber, Matthias Braendli	Multi-gigabit GCM-AES Architecture Optimized for FPGAs.	CHES	2007	DBLP DOI BibTeX RDF	Galois/Counter Mode (GCM), hybrid multiplier, Field Programmable Gate Array (FPGA), Very Large Scale Integration (VLSI), Advanced Encryption Standard (AES), high throughput, digit-serial multiplier, bit-parallel multiplier
16	PariVallal Kannan, Dinesh Bhatia	Interconnect estimation for FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
16	Jason Helge Anderson, Farid N. Najm	Active leakage power optimization for FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
16	Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi	Compile-time area estimation for LUT-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Reconfigurable computing, compiler optimization, resource estimation
16	Robert P. McEvoy, Francis M. Crowe, Colin C. Murphy, William P. Marnane	Optimisation of the SHA-2 Family of Hash Functions on FPGAs.	ISVLSI	2006	DBLP DOI BibTeX RDF
16	Yohei Matsumoto, Hanpei Koike, Akira Masaki	FPGAs with multidimensional mesh topology.	FPGA	2006	DBLP DOI BibTeX RDF
16	Kenneth Eguro, Scott Hauck	Armada: timing-driven pipeline-aware routing for FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	pipeline FPGA, pipeline routing, reconfigurable computing
16	Chidamber Kulkarni, Gordon J. Brebner	Memory centric thread synchronization on platform FPGAs.	DATE	2006	DBLP DOI BibTeX RDF
16	Vishal Suthar, Shantanu Dutt	Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults.	DATE	2006	DBLP DOI BibTeX RDF
16	Divyang K. Masrani, W. James MacLean	A Real-Time Large Disparity Range Stereo-System using FPGAs.	ICVS	2006	DBLP DOI BibTeX RDF
16	Ling Zhuo, Viktor K. Prasanna	High-Performance and Parameterized Matrix Factorization on FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
16	Patrick Lysaght, Brandon Blodget, Jeff Mason, Jay Young, Brendan Bridgford	Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
16	Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz	High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
16	Somsubhra Mondal, Seda Ogrenci Memik	Power Optimization Techniques for SRAM-Based FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
16	Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert	Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
16	María Brox, Santiago Sánchez-Solano	Development of IP Modules of Fuzzy Controllers for the Design of Embedded Systems on FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
16	Peter Alfke	Tutorial: 65 NM FPGAs, A Look Under the Hood Technology, Features, and Applications.	FPL	2006	DBLP DOI BibTeX RDF
16	Go-An Rau, Meng-Xin Guo	Multiplierless Realization of Modified Comb Filter by Using Xilinx Spartan FPGAs.	ICICIC (2)	2006	DBLP DOI BibTeX RDF
16	Christopher T. Johnston, Donald G. Bailey, Paul J. Lyons	Towards a visual notation for pipelining in a visual programming language for programming FPGAs.	CHINZ	2006	DBLP DOI BibTeX RDF	FPGA, pipelining, visual programming language
16	Michael Hübner 0001, Jürgen Becker 0001	Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration.	SBCCI	2006	DBLP DOI BibTeX RDF	designflow, dynamic and partial reconfiguration, reconfigurable hardware
16	Premysl Sucha, Zdenek Hanzálek	Scheduling of Tasks with Precedence Delays and Relative Deadlines - Framework for Time-optimal Dynamic Reconfiguration of FPGAs.	IPDPS	2006	DBLP DOI BibTeX RDF
16	Premysl Sucha, Zdenek Hanzálek	Scheduling of tasks with precedence delays and relative deadlines framework for time-optimal dynamic reconfiguration of FPGAs.	IPDPS	2006	DBLP DOI BibTeX RDF
16	Kwatra Kwatra, Viktor K. Prasanna, Mitali Singh	Accelerating DTI tractography using FPGAs.	IPDPS	2006	DBLP DOI BibTeX RDF
16	Miguel L. Silva, João Canas Ferreira	Exploiting dynamic reconfiguration of platform FPGAs: implementation issues.	IPDPS	2006	DBLP DOI BibTeX RDF
16	Michael J. Jipping, Sara Henry, Kathleen Ludewig, Leslie Tableman	How to integrate FPGAs into a computer organization course.	SIGCSE	2006	DBLP DOI BibTeX RDF	digital logic circuit, simulation, FPGA, computer organization
16	Michael J. Wirthlin, Welson Sun	DSynth: A Pipeline Synthesis Environment for FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
16	Simin Dai, Elaheh Bozorgzadeh	CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures.	FCCM	2006	DBLP DOI BibTeX RDF
16	Manuel G. Gericota, Gustavo R. Alves, Luís F. Lemos, José M. Ferreira 0001	A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
16	Mariusz Bajger, Amos Omondi	Implementations of Square-Root and Exponential Functions for Large FPGAs.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
16	Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama	Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.	ISMVL	2006	DBLP DOI BibTeX RDF
16	Nei-Chiung Perng, Jian-Jia Chen, Chuan-Yue Yang, Tei-Wei Kuo	Energy-efficient scheduling on multi-context FPGAs.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Somsubhra Mondal, Rajarshi Mukherjee, Seda Ogrenci Memik	Fine-grain thermal profiling and sensor insertion for FPGAs.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Justin Lee, Joaquin Sitte	Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs.	AHS	2006	DBLP DOI BibTeX RDF
16	Andres Upegui, Eduardo Sanchez	Evolving Hardware with Self-reconfigurable connectivity in Xilinx FPGAs.	AHS	2006	DBLP DOI BibTeX RDF
16	Chang Woo Kang, Massoud Pedram	Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	antifuse, clustering, FPGA, power
16	Salvatore Pontarelli, Marco Ottavi, Vamsi Vankamamidi, Adelio Salsano, Fabrizio Lombardi	Reliability Evaluation of Repairable/Reconfigurable FPGAs.	DFT	2006	DBLP DOI BibTeX RDF
16	Divyang K. Masrani, W. James MacLean	A Real-Time Large Disparity Range Stereo-System Using FPGAs.	ACCV (2)	2006	DBLP DOI BibTeX RDF
16	Donald G. Bailey, K. T. Gribbon, Christopher T. Johnston, Montree Siripruchyanun	GATOS: A Windowing Operating System for FPGAs.	DELTA	2006	DBLP DOI BibTeX RDF
16	Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001	An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.	VLSI Design	2006	DBLP DOI BibTeX RDF
16	Guy Dupenloup, Thierry Lemeunier, Roland Mayr	Transistor abstraction for the functional verification of FPGAs.	DAC	2006	DBLP DOI BibTeX RDF	cone model, logic equivalence checking, transistor abstraction, FPGA, register transfer level, multiplexer, functional verification
16	Yan Meng, Timothy Sherwood, Ryan Kastner	Leakage power reduction of embedded memories on FPGAs through location assignment.	DAC	2006	DBLP DOI BibTeX RDF	location assignment, leakage power, embedded memory
16	Ali Karabiyik, Aydogan Savran	Hardware Implementation of a Wavelet Neural Network Using FPGAs.	ICONIP (3)	2006	DBLP DOI BibTeX RDF
16	Ju-wook Jang, Seonil B. Choi, Viktor K. Prasanna	Energy- and time-efficient matrix multiplication on FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
16	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan	Timing-driven partitioning-based placement for island style FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
16	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	look-up table (LUT), FPGA, test, delay fault
16	Robert Fischer 0002, Klaus Buchenrieder, Ulrich Nageldinger	Reducing the Power Consumption of FPGAs through Retiming.	ECBS	2005	DBLP DOI BibTeX RDF
16	Siobhán Launders, Colin Doyle, Wesley Cooper	Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs.	PATMOS	2005	DBLP DOI BibTeX RDF
16	Ghazanfar Asadi, Mehdi Baradaran Tahoori	Soft error rate estimation and mitigation for SRAM-based FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	soft error rate estimation, error recovery, SRAM-based FPGA
16	Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi	Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF