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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 841 occurrences of 340 keywords
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Results
Found 983 publication records. Showing 983 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Anand Rajaram, David Z. Pan, Jiang Hu |
Improved algorithms for link-based non-tree clock networks for skew variability reduction. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
non-tree clocks, physical design, VLSI CAD, clock network |
1 | Jaskirat Singh, Sachin S. Sapatnekar |
A fast algorithm for power grid design. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
power grid design, wire pitch, optimization, locality, macromodel, bipartitioning |
1 | Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris |
Unified quadratic programming approach for mixed mode placement. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
mixed mode placement, discrete cosine transformation, quadratic programming |
1 | Andrzej J. Strojwas |
Tutorial on DFM for physical design. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia |
A semi-persistent clustering technique for VLSI circuit placement. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
VLSI placement, physical design, hypergraph clustering |
1 | Jill H. Y. Law, Evangeline F. Y. Young |
Multi-bend bus driven floorplanning. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
bus planning, floorplanning, VLSI CAD |
1 | Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong |
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
yield, buffering, design for manufacturing, wire sizing, chemical mechanical polishing (CMP) |
1 | Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi |
Dragon2005: large-scale mixed-size placement tool. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
placement, physical design |
1 | Jue-Hsien Chern |
Challenges of analog/mixed-signal SoC design and verification. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Shankar Krishnamoorthy |
Insights and perspectives on physical synthesis. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten |
Routing of analog busses with parasitic symmetry. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
analog routing, net bundles, paired nets, virtual terminals, routing, EDA, RF, bus routing, IC-layout |
1 | Jarrod A. Roy, David A. Papa, Saurabh N. Adya, Hayward H. Chan, Aaron N. Ng, James F. Lu, Igor L. Markov |
Capo: robust and scalable open-source min-cut floorplacer. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
placement, physical design, floorplanning |
1 | Kun-Cheng Wu, Yu-Wen Tsai |
Structured ASIC, evolution or revolution? |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
ASIC, structured ASIC |
1 | Charles J. Alpert, Patrick Groeneveld (eds.) |
Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004 |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Shamik Das, Andy Fan, Kuan-Neng Chen, Chuan Seng Tan, Nisha Checka, Rafael Reif |
Technology, performance, and computer-aided design of three-dimensional integrated circuits. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
3-D VLSI, routing, placement, layout, 3-D IC, 3-D integration |
1 | Debjit Sinha, Hai Zhou 0001, Chris C. N. Chu |
Optimal gate sizing for coupling-noise reduction. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
coupling-noise, gate-sizing, lattice theory, fixpoint |
1 | Jaskirat Singh, Sachin S. Sapatnekar |
Topology optimization of structured power/ground networks. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
optimization, routing, power, ground |
1 | Natarajan Viswanathan, Chris C. N. Chu |
FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
net models, analytical placement, standard cell placement |
1 | Kai Wang 0011, Malgorzata Marek-Sadowska |
Clock network sizing via sequential linear programming with time-domain analysis. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
sequential linear programming, sizing, clock skew, time-domain analysis |
1 | Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang |
A predictive distributed congestion metric and its application to technology mapping. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
congestion prediction, technology mapping |
1 | Hua Xiang 0001, Kai-Yuan Chao, D. F. Wong 0001 |
An ECO algorithm for eliminating crosstalk violations. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
routing, crosstalk, ECO |
1 | Charles J. Alpert, Milos Hrkic, Stephen T. Quay |
A fast algorithm for identifying good buffer insertion candidate locations. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
planning, global routing, buffer insertion, physical synthesis |
1 | Jason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl |
An area-optimality study of floorplanning. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
area partitioning, block packing, optimality, benchmarking, placement, floorplanning, aspect ratios |
1 | Changbo Long, Jinjun Xiong, Lei He 0001 |
On optimal physical synthesis of sleep transistors. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
physical design, power-gating, sleep transistors |
1 | Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester |
The great interconnect buffering debate: are you a chicken or an ostrich? |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen |
Multilevel routing with antenna avoidance. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
nanometer, process antenna effect, routing, physical design, design for manufacturability (DFM), multilevel optimization |
1 | Mario R. Casu, Luca Macchiarulo |
Floorplanning for throughput. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
systems-on-chip, throughput, floorplanning, wire pipelining |
1 | Taraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh |
Innovate or perish: FPGA physical design. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
FPGA, partitioning, placement, physical design, floorplanning, delay estimation, routing architecture |
1 | Jurjen Westra, Chris Bartels, Patrick Groeneveld |
Probabilistic congestion prediction. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
congestion prediction, routing, congestion |
1 | Rafael Escovar, Salvador Ortiz 0002, Roberto Suaya |
Mutual inductance extraction and the dipole approximation. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
mutual coupling, inductance, approximation methods, parasitic extraction, electromagnetic fields |
1 | Lakshmi Kalpana Vakati, Janet Meiling Wang |
A new multi-ramp driver model with RLC interconnect load. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
inductance criteria, multi-ramp driver model, transmission line effects, interconnect modeling, effective capacitance |
1 | Andrew B. Kahng, Qinke Wang |
Implementation and extensibility of an analytic placer. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
I/O-Core co-placement, hierarchical placement, congestion, geometric constraints, analytical placement |
1 | Peter J. Osler |
Placement driven synthesis case studies on two sets of two chips: hierarchical and flat. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
synthesis, placement, application specific integrated circuit (ASIC), register transfer level (RTL), static timing analysis (STA), netlist |
1 | Robert K. Montoye |
The four degrees of 3D. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Takumi Okamoto, Tsutomu Kimoto, Naotaka Maeda |
Design methodology and tools for NEC electronics' structured ASIC ISSP. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
ISSP, placement, structured ASIC, regular fabric |
1 | Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar |
Early-stage power grid analysis for uncertain working modes. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
early estimation, supply network, random walk, power grid |
1 | Qinghua Liu, Malgorzata Marek-Sadowska |
A study of netlist structure and placement efficiency. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
netlist structure, efficiency, placement |
1 | Deepak D. Sherlekar |
Design considerations for regular fabrics. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
structured ASIC, regular fabric |
1 | Ulrich Brenner, Anna Pauli, Jens Vygen |
Almost optimum placement legalization by minimum cost flow and dynamic programming. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
placement, legalization, minimum-cost flow, detailed placement |
1 | Dennis K. Y. Tong, Evangeline F. Y. Young |
Performance-driven register insertion in placement. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
post-retiming, register insertion, placement |
1 | Monica Donno, Enrico Macii, Luca Mazzoni |
Power-aware clock tree planning. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
clock tree synthesis and routing, physical design and optimization, low-power design, digital design |
1 | Robert K. Montoye |
The four degrees of 3D. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Ateen Khatkhate, Chen Li 0004, Ameya R. Agnihotri, Mehmet Can Yildiz, Satoshi Ono, Cheng-Kok Koh, Patrick H. Madden |
Recursive bisection based mixed block placement. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
mixed block design, placement, floorplanning |
1 | Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen |
Sensitivity guided net weighting for placement driven synthesis. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
interconnect, sensitivity analysis, physical synthesis, timing driven placement, net weight |
1 | Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Xu Xu 0001, Alexander Zelikovsky |
Multi-project reticle floorplanning and wafer dicing. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
multi-project wafers, reticle design, wafer dicing |
1 | Haoxing Ren, David Zhigang Pan, David S. Kung 0001 |
Sensitivity guided net weighting for placement driven synthesis. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
interconnect, sensitivity analysis, physical synthesis, timing driven placement, net weight |
1 | Hardy Kwok-Shing Leung |
Advanced routing in changing technology landscape. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
routing, physical design, manufacturability, design rules |
1 | Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan |
Closed form expressions for extending step delay and slew metrics to ramp inputs. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
Elmore, slew, delay, timing, interconnects, PDF, moments, median, skewness |
1 | Leon Stok, John M. Cohn |
There is life left in ASICs. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
design cost, ASIC, design tools |
1 | Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda |
Signal integrity management in an SoC physical design flow. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
noise avoidance, noise repair, signal integrity, crosstalk noise |
1 | Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill Halpin |
Timing driven force directed placement with physical net constraints. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
net constraints, timing driven placement, force directed placement |
1 | Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden |
Benchmarking for large-scale placement and beyond. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
placer, signal delay, performance, evaluation, routing, benchmark, timing, placement, layout, congestion, comparison, wirelength |
1 | Jason Cong, Michail Romesis, Min Xie 0004 |
Optimality, scalability and stability study of partitioning and placement algorithms. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
optimality, scalability, stability, partitioning, placement |
1 | Andrew B. Kahng, Xu Xu 0001 |
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Raymond X. Nijssen, Ed P. Huijbregts |
A complete design for power methodology and flow for large ASICs. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera |
Capturing crosstalk-induced waveform for accurate static timing analysis. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
capacitive coupling noise, delay calculation, slope propagation, static timing analysis, crosstalk noise |
1 | Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay |
Porosity aware buffered steiner tree construction. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
VLSI, interconnect, physical design, buffer insertion |
1 | Bing Lu, Jiang Hu, Gary Ellis, Haihua Su |
Process variation aware clock tree routing. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
VLSI, interconnect, physical design, clock tree synthesis |
1 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen 0001, Yici Cai, Chung-Kuan Cheng, Jun Gu |
An integrated floorplanning with an efficient buffer planning algorithm. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
floorplanning, buffer insertion, routability |
1 | Raul Camposano |
Keynote Speaker. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick |
The scaling challenge: can correct-by-construction design help? |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
clocked repeaters, correct-by-construction design, design fabrics, post-RTL design, routing, interconnect, placement, logic synthesis, scaling, technology mapping, repeaters |
1 | Andrew B. Kahng |
Research directions for coevolution of rules and routers. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Bo Hu 0006, Hailin Jiang, Qinghua Liu, Malgorzata Marek-Sadowska |
Synthesis and placement flow for gain-based programmable regular fabrics. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
programmable, regular fabric, gain |
1 | Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee |
Explicit gate delay model for timing evaluation. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
pre-characterize, delay model, explicit |
1 | Paul Villarrubia |
Important placement considerations for modern VLSI chips. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Chetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi |
An architectural exploration of via patterned gate arrays. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
VPGA, lookup table, interconnect architectures, gate array |
1 | Matthew Moe, Herman Schmit |
Floorplanning of pipelined array modules using sequence pairs. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
pipelined array, floorplan, sequence pair |
1 | Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang |
Constrained "Modern" Floorplanning. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
floorplanning, network flow, rectilinear polygons |
1 | Ting-Yuan Wang, Yu-Min Lee, Charlie Chung-Ping Chen |
3D thermal-ADI: an efficient chip-level transient thermal simulator. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
ADI, design, automation, temperature, finite difference methods, thermal simulation |
1 | Massoud Pedram, Charles J. Alpert (eds.) |
Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003 |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen |
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
?-optimal, incremental refinement, pseudo-polynomial, clock tree, wire-sizing, zero-skew |
1 | Ravi Varadarajan |
Convergence of placement technology in physical synthesis: is placement really a point tool? |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang |
Architecture and synthesis for multi-cycle communication. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
RDR, multi-cycle communication, scheduling, interconnect, placement, binding, deep sub-micron, timing closure |
1 | Bo Hu 0006, Malgorzata Marek-Sadowska |
Fine granularity clustering for large scale placement problems. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
clustering, placement |
1 | Hai Zhou 0001 |
Efficient Steiner tree construction based on spanning graphs. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
routing, Steiner tree, minimal spanning tree |
1 | Guoqiang Chen, Sachin S. Sapatnekar |
Partition-driven standard cell thermal placement. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
VLSI, partition, placement, temperature, standard cell, thermal model |
1 | Lars Liebmann |
Layout impact of resolution enhancement techniques: impediment or opportunity? |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
radically restricted designs, resolution enhancement techniques, design for manufacturability, lithography |
1 | Fan Mo, Robert K. Brayton |
Fishbone: a block-level placement and routing scheme. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
routing, placement |
1 | Luca Daniel, Chin Siong Ong, Sok Chay Low, Kwok Hong Lee, Jacob White 0001 |
Geometrically parameterized interconnect performance models for interconnect synthesis. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
parametrized model order reduction, interconnect synthesis |
1 | Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani |
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
floorplanning, routability, interconnect estimation |
1 | Lauren Hui Chen, Malgorzata Marek-Sadowska |
Incremental delay change due to crosstalk noise. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas |
Understanding and addressing the impact of wiring congestion during technology mapping. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham |
Buffer insertion with adaptive blockage avoidance. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera |
Crosstalk noise optimization by post-layout transistor sizing. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
capacitive coupling noise, post-layout optimization, gate sizing, transistor sizing, crosstalk noise |
1 | Pinhong Chen, Yuji Kukimoto, Chin-Chi Teng, Kurt Keutzer |
On convergence of switching windows computation in presence of crosstalk noise. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Andrew B. Kahng, Stefanus Mantik, Igor L. Markov |
Min-max placement for large-scale timing optimization. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Chunhong Chen |
Physical design with multiple on-chip voltages. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh |
Routability driven white space allocation for fixed-die standard-cell placement. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
placement, physical design, routability |
1 | Jason Cong, Chang Wu |
Global clustering-based performance-driven circuit partitioning. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
clustering, partitioning, performance optimization, retiming, VLSI CAD |
1 | Milos Hrkic, John Lillis |
Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Shuo Zhang, Wayne Wei-Ming Dai |
TEG: a new post-layout optimization method. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Saurabh N. Adya, Igor L. Markov |
Consistent placement of macro-blocks using floorplanning and standard-cell placement. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Chiu-Wing Sham, Evangeline F. Y. Young |
Routability driven floorplanner with buffer block planning. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Yu Chen 0005, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky |
Closing the smoothness and uniformity gap in area fill synthesis. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
VLSI manufacturability, density analysis, dummy fill problem, monte-carlo, chemical-mechanical polishing |
1 | Chin-Chih Chang, Jason Cong, David Zhigang Pan |
Physical hierarchy generation with routing congestion control. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
routing, interconnect, placement, hierarchy, congestion, physical, deep sub-micron |
1 | Sung-Mo Kang |
On-chip thermal engineering for peta-scale integration. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Hui Xu 0001, Rob A. Rutenbar, Karem A. Sakallah |
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Seokjin Lee, D. F. Wong 0001 |
Timing-driven routing for FPGAs based on Lagrangian relaxation. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
timing-driven routing, FPGA, Lagrangian relaxation |
1 | Ulrich Brenner, André Rohe |
An effective congestion driven placement framework. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Vivek De |
Leakage-tolerant design techniques for high performance processors. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
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