Search results for "pipeline"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Jeremy R. Levitt, Kunle Olukotun	Verifying correct pipeline implementation for microprocessors.	ICCAD	1997	DBLP DOI BibTeX RDF
14	Frank Yeong-Chyang Shih, Chung Ta King, Christopher C. Pu	Pipeline architectures for recursive morphological operations.	IEEE Trans. Image Process.	1995	DBLP DOI BibTeX RDF
14	Jang Dae Kim, Shiu-Kai Chin	Formal Verification of Serial Pipeline Multipliers.	TPHOLs	1995	DBLP DOI BibTeX RDF
14	A. G. Bolton, M. Dankiw, Lakhmi C. Jain	Optimum parameters for a pipeline processor.	Electronic Technology Directions	1995	DBLP DOI BibTeX RDF
14	Lih-Gwo Jeng, Liang-Gee Chen	Rate-optimal DSP synthesis by pipeline and minimum unfolding.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
14	Sofiène Tahar, Ramayya Kumar	Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL.	TPHOLs	1994	DBLP DOI BibTeX RDF
14	Matthew Regan, Ronald Pose	Priority rendering with a virtual reality address recalculation pipeline.	SIGGRAPH	1994	DBLP DOI BibTeX RDF
14	Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin	PLS: a scheduler for pipeline synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
14	Beverly Gocal	PRISM architecture: parallel and pipeline features.	MICRO	1990	DBLP BibTeX RDF
14	David J. Mallon, Peter B. Denyer	A new approach to pipeline optimisation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
14	François Bodin, François Charot, Charles Wagner	Overview of a high-performance programmable pipeline structure.	ICS	1989	DBLP DOI BibTeX RDF
14	William Alexander, Tom W. Keller, Ellen E. Boughter	A Workload Characterization Pipeline for Models of Parallel Systems.	SIGMETRICS	1987	DBLP DOI BibTeX RDF
14	Gérard G. Baille, Jean-Pierre Schoellkopf	A pipeline polish string computer.	AFIPS National Computer Conference	1976	DBLP DOI BibTeX RDF
12	Huy T. Vo, João Luiz Dihl Comba, Berk Geveci, Cláudio T. Silva	Streaming-Enabled Parallel Data Flow Framework in the Visualization ToolKit.	Comput. Sci. Eng.	2011	DBLP DOI BibTeX RDF	Parallel dataflow, visualization pipeline, streaming, multithreaded, VTK
12	Michael Agun, Shawn Bowers	Approaches for Implementing Persistent Queues within Data-Intensive Scientific Workflows.	SERVICES	2011	DBLP DOI BibTeX RDF	Actor-Oriented Modeling, Scientific Workflows, Dataflow, Pipeline Parallelism
12	Oguzhan Erdem, Hoang Le, Viktor K. Prasanna	Clustered Hierarchical Search Structure for Large-Scale Packet Classification on FPGA.	FPL	2011	DBLP DOI BibTeX RDF	Large-Scale Packet Classification, Hierarchical Search Structure, FPGA, Decision tree, Pipeline
12	Yang-Ming Zhu, Steven M. Cochoff	Medical Image Viewing on Multicore Platforms Using Parallel Computing Patterns.	IT Prof.	2010	DBLP DOI BibTeX RDF	parallel programming software patterns, pipeline, multicore, data parallelism, task parallelism, task decomposition, data decomposition
12	Yeim-Kuan Chang, Yung-Chieh Lin, Cheng-Chien Su	Dynamic Multiway Segment Tree for IP Lookups and the Fast Pipelined Search Engine.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	elementary interval, FPGA, pipeline, B-tree, Segment tree
12	Xiaoyu Yang 0001, Richard Paul Bruin, Martin T. Dove	Developing an End-to-End Scientific Workflow.	Comput. Sci. Eng.	2010	DBLP DOI BibTeX RDF	Service-oriented workflow, Pipeline Pilot, SOA, grid computing, scientific computing, workflow management, e-science
12	Jose Alexander Guevara, Eduardo César, Joan Sorribes, Andreu Moreno, Tomàs Margalef, Emilio Luque	A Performance Tuning Strategy for Complex Parallel Application.	PDP	2010	DBLP DOI BibTeX RDF	dynamic tuning, Master/Worker, Pipeline, composite models
12	Scott Michael, Patricia Knezek, Elizabeth B. Stobie, Robert Henschel, Stephen C. Simms	A Revolutionary New Paradigm for the Reduction and Analysis of Astronomical Images.	eScience	2010	DBLP DOI BibTeX RDF	Image processing, Image analysis, Pipeline processing, Astronomy
12	Nils Gruschka, Meiko Jensen, Luigi Lo Iacono	A Design Pattern for Event-Based Processing of Security-Enriched SOAP Messages.	ARES	2010	DBLP DOI BibTeX RDF	event-based processing, Event Pipeline Pattern, Design Pattern, streaming, Web Service Security
12	Iman Faraji, Moslem Didehban, Hamid R. Zarandi	Analysis of Transient Faults on a MIPS-Based Dual-Core Processor.	ARES	2010	DBLP DOI BibTeX RDF	Dual-core microprocessor, Microprocessor without Interlocked Pipeline Stages (MIPS), simulation-based fault injection, vulnerability analysis, fault propagation
12	Iris Adä, Michael R. Berthold	The new iris data: modular data generators.	KDD	2010	DBLP DOI BibTeX RDF	artificial data, pipeline tool, data generation
12	Kristy Elizabeth Boyer, E. Nathan Thomas, Audrey Smith Rorrer, Deonte Cooper, Mladen A. Vouk	Increasing technical excellence, leadership and commitment of computing students through identity-based mentoring.	SIGCSE	2010	DBLP DOI BibTeX RDF	computing pipeline, project-based initiatives, diversity, mentoring, broadening participation
12	Mark D. LeBlanc, Tom Armstrong, Michael B. Gousie	Connecting across campus.	SIGCSE	2010	DBLP DOI BibTeX RDF	bioinformatics, pipeline, intelligent systems, arts, retention, humanities, web programming, recruitment, interdisciplinary, curricula, social sciences, multidisciplinary, women in computing, applied computer science
12	Xin Jin 0003, Mikel Luján, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Steve B. Furber	Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	mlp, spinnaker, parallel, mapping, pipeline, backpropagation
12	Zhong-Ho Chen, Ta-Chun Chen, Jung-Yin Chien, Alvin Wen-Yu Su, Ce-Kuen Shieh	Exploiting Parallelism of MPEG-4 Decoder with Dataflow Programming on Multicore Processor.	ISPA	2010	DBLP DOI BibTeX RDF	Modeling, Parallel Processing, component, Decoding, Pipeline Processing
12	Kuei-Ping Shih, Yen-Da Chen, Shu-Sheng Liu	A Collision Avoidance Multi-channel MAC Protocol with Physical Carrier Sensing for Mobile Ad Hoc Networks.	AINA Workshops	2010	DBLP DOI BibTeX RDF	hidden terminal problem, single transceiver, pipeline, IEEE 802.11, Multi-Channel
12	Jingbang Qiu, Tianci Huang, Takeshi Ikenaga	A FPGA-Based Dual-Pixel Processing Pipelined Hardware Accelerator for Feature Point Detection Part in SIFT.	NCM	2009	DBLP DOI BibTeX RDF	Dual-Pixel Processing, FPGA, Pipeline, SIFT, Feature Point Detection
12	Jiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing	Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture.	ReConFig	2009	DBLP DOI BibTeX RDF	temporal parallelism, macro-pipeline, FPGA accelerator, matrix multiplication
12	Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose	FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy.	FCCM	2009	DBLP DOI BibTeX RDF	photodynamic therapy, PDT, Stratix, DE3, FPGA, applications, pipeline, Power, Monte Carlo, SystemC, acceleration, cancer
12	Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang 0032, Yuan Xie 0001, Frank Mueller 0001	CheckerCore: enhancing an FPGA soft core to capture worst-case execution times.	CASES	2009	DBLP DOI BibTeX RDF	LEON3, checkercore, shadow pipeline, FPGA, embedded system, real-time, WCET, worst-case-execution-time, SPARC
12	Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy 0001, Ranjani Narayan	Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.	CASES	2009	DBLP DOI BibTeX RDF	application synthesis, custom instruction extension, dataflow software pipeline, honeycomb, polymorphic asic, runtime reconfiguration, router, NOC
12	Garo Bournoutian, Alex Orailoglu	Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions.	CASES	2009	DBLP DOI BibTeX RDF	compiler assisted hardware, pipeline stalls, embedded processors, data cache
12	Yeim-Kuan Chang, Yen-Cheng Liu, Fang-Chen Kuo	A Pipelined IP Forwarding Engine with Fast Update.	AINA	2009	DBLP DOI BibTeX RDF	route update, FPGA, pipeline, IP lookup
12	Kui Yi, YueHua Ding	32-bit RISC CPU Based on MIPS Instruction Fetch Module Design.	JCAI	2009	DBLP DOI BibTeX RDF	Pipeline, Data Flow, MIPS, Data Path
12	Paolo Cignoni, Roberto Scopigno	Sampled 3D models for CH applications: A viable and enabling new medium or just a technological exercise?.	ACM Journal on Computing and Cultural Heritage	2008	DBLP DOI BibTeX RDF	color data acquisition and mapping, computer-aided restoration, efficient visualization, scanning pipeline, 3D scanning
12	Stavros Souravlas, Manos Roumeliotis	A message passing strategy for array redistributions in a torus network.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Superclasses, Pipeline, High performance Fortran, Communication scheduling, Array redistribution
12	Nikolaos Kavvadias, Spiridon Nikolaidis 0001	Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Optimization, Microprocessors, Hardware description languages, Real-time and embedded systems, Pipeline processors, Control design
12	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Modeling techniques, Pipeline processors, Modeling of computer architecture
12	Deniz Balkan, Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose	Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	General, Microprocessors, Pipeline processors, Performance attributes
12	Paul Biggar, Nicholas Nash, Kevin Williams 0001, David Gregg	An experimental study of sorting and branch prediction.	ACM J. Exp. Algorithmics	2008	DBLP DOI BibTeX RDF	caching, Sorting, branch prediction, pipeline architectures
12	Marcin Wojnarski	Debellor: A Data Mining Platform with Stream Architecture.	Trans. Rough Sets	2008	DBLP DOI BibTeX RDF	Pipeline, Online Algorithms, Library, Software Environment
12	Chua-Chin Wang, Gang-Neng Sung, Pai-Li Liu	Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	data transition detection, CLA, pipeline, power-aware, ANT
12	Duc Vianney, Gadi Haber, Andre Heilper, Marcel Zalmanovici	Performance analysis and visualization tools for cell/B.E. multicore environment.	IFMT	2008	DBLP DOI BibTeX RDF	Euler based particle simulation, code analyzer, control flow analyzer, counter analyzer, pipeline analyzer, profile analyzer, trace analyzer, virtual performance analyzer, cell broadband engine
12	Abdulrahman Hanoun, Friedrich Mayer-Lindenberg, Bassel Soudan	Reconfigurable Cell Architecture for Systolic and Pipelined Computing Datapaths.	ReConFig	2008	DBLP DOI BibTeX RDF	2D pipeline, Baugh-Wooley, Reconfigurable, Multiplier, distributed arithmetic, Systolic
12	Swapnil Bahl, Vishal Srivastava	Self-Programmable Shared BIST for Testing Multiple Memories.	ETS	2008	DBLP DOI BibTeX RDF	Memory testing and Semiconductor memory, Built-in Self-test (BIST), Pipeline architecture
12	Janice L. Pearce, Mario Nakazawa	The funnel that grew our cis major in the cs desert.	SIGCSE	2008	DBLP DOI BibTeX RDF	pipeline, retention, cs0, computer literacy, enrollment
12	Peng Wang, Yong-en Chen	Low-Complexity Real-Time LDPC Encoder Design for CMMB.	IIH-MSP	2008	DBLP DOI BibTeX RDF	CMMB standard, LDPC encoding, Pipeline design, Pingpong buffer, LU decomposition
12	Zulhakimi Razak, Tughrul Arslan	Analog to Digital Converter Specification for UMTS/FDD Receiver Applications.	DELTA	2008	DBLP DOI BibTeX RDF	UMTS/FDD, specification, pipeline, ADC
12	Tingting Sha, Milo M. K. Martin, Amir Roth	NoSQ: Store-Load Communication without a Store Queue.	IEEE Micro	2007	DBLP DOI BibTeX RDF	microarchitecture, RISC, pipeline processors, VLIW architectures, CISC
12	Weiwu Hu, Ji-Ye Zhao, Shi-Qiang Zhong, Xu Yang, Elio Guidetti, Chris Wu	Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	superscalar pipeline, non-blocking cache, synthesis flow, bit-sliced placement, crafted cell, performance evaluation, physical design, out-of-order execution, general-purpose processor
12	Tao Li 0006, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio 0001	OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	branch prediction, processor architectures, Pipeline processors, performance of systems, hardware/software interfaces, computer system implementation
12	Jeffrey D. Weekley, Curtis L. Blais, Donald P. Brutzman	Composing behaviors and swapping bodies with motion capture data in X3D.	Web3D	2007	DBLP DOI BibTeX RDF	Humanoid Animation (H-Anim), XML data archive for motion capture-derived behaviors, blended behaviors and composable bodies prototypes, general pipeline description for motion capture to H-Anim data conversion, motion capture data transformation
12	Jason Cong, Guoling Han, Wei Jiang	Synthesis of an application-specific soft multiprocessor system.	FPGA	2007	DBLP DOI BibTeX RDF	clustering, multiprocessor, pipeline, labeling, design space
12	Kristy Elizabeth Boyer, Rachael S. Dwight, Carolyn S. Miller, C. Dianne Raubenheimer, Matthias F. Stallmann, Mladen A. Vouk	A case for smaller class size with integrated lab for introductory computer science.	SIGCSE	2007	DBLP DOI BibTeX RDF	class size, underrepresented groups, active learning, pipeline, assessment, introductory computer science
12	Shmuel Fink, Gerald Kruse, Keith Olson	Status report on the SIGCSE committee on models for evaluating faculty scholarship.	SIGCSE	2007	DBLP DOI BibTeX RDF	faculty evaluation, tenure, pipeline, professional development, scholarship
12	James Aspnes, Yinghua Wu	O(logn)-Time Overlay Network Construction from Graphs with Out-Degree 1.	OPODIS	2007	DBLP DOI BibTeX RDF	balanced search tree, fault tolerance, pipeline, Overlay network, self-stabilizing, randomization
12	Voicu Popescu, Paul Rosen 0001	Forward rasterization.	ACM Trans. Graph.	2006	DBLP DOI BibTeX RDF	point-based modeling and rendering, rendering pipeline, antialiasing, rasterization, 3D warping
12	Jeni Tennison	Processing XML documents with pipelines.	ACM Symposium on Document Engineering	2006	DBLP DOI BibTeX RDF	XML, pipeline, transformation, processing
12	Weiwu Hu, Fuxin Zhang, Zusong Li	Microarchitecture of the Godson-2 Processor.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	superscalar pipeline, dynamic scheduling non-blocking cache, load speculation, branch prediction, out-of-order execution, register renaming
12	Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero	Software Trace Cache.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	compiler optimizations, branch prediction, Pipeline processors, trace cache, instruction fetch
12	Aneesh Aggarwal, Manoj Franklin	Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	Clustered processor architecture, pipeline processors, interconnection architectures, load balancing and task assignment
12	Peter Petrov, Alex Orailoglu	A reprogrammable customization framework for efficient branch resolution in embedded processors.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	Branch resolution, pipeline organization
12	Niwat Thepvilojanapong, Yoshito Tobe, Kaoru Sezaki	Impact of intentional mobility in sparse sensor networks.	SenSys	2005	DBLP DOI BibTeX RDF	disruption tolerance, intentional mobility, pipeline formation, sensing robots, mobile sensor networks
12	Christine Rochange, Pascal Sainrat	A time-predictable execution mode for superscalar pipelines with instruction prescheduling.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	real-time, pipeline, WCET, processor architecture
12	Stamatis Vassiliadis, Leonel Sousa, Georgi Gaydadjiev	The Midlifekicker Microarchitecture Evaluation Metric.	ASAP	2005	DBLP DOI BibTeX RDF	pipeline, microarchitecture, ILP
12	Abdallah Merhebi, Otmane Aït Mohamed	FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	OC192, PL4, POS, WF scheduler, FPGAs, ATM, pipeline
12	Hui Qin, Tsutomu Sasao, Yukihiro Iguchi	An FPGA design of AES encryption circuit with 128-bit keys.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	AES encryption, FPGA, pipeline
12	Deng Pan, Yuanyuan Yang	Pipelined two step iterative matching algorithms for CIOQ crossbar switches.	ANCS	2005	DBLP DOI BibTeX RDF	scheduling, pipeline, convergence, iterative algorithms
12	David J. Duke	Linking Representation with Meaning.	IEEE Visualization	2004	DBLP DOI BibTeX RDF	Ontology, Visualization, Database, Pipeline
12	Yuu Tanaka, Toshinori Sato, Takenori Koushiro	The potential in energy efficiency of a speculative chip-multiprocessor.	SPAA	2004	DBLP DOI BibTeX RDF	dual pipeline, energy efficiency, speculative multithreading
12	Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He 0001	Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects.	DAC	2004	DBLP DOI BibTeX RDF	piecewise-linear, performance, pipeline, interconnect, floorplanning
12	Andrea Lodi 0002, Mario Toma, Fabio Campi	A pipelined configurable gate array for embedded processors.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, pipeline, energy, reconfigurable processor
12	Mark G. Arnold	A VLIW Architecture for Logarithmic Arithmetic.	DSD	2003	DBLP DOI BibTeX RDF	Very Long Instruction Word, sum of products, pipeline, Logarithmic Number System
12	Alberto Ortiz 0001, Miquel Simó, Gabriel Oliver	A vision system for an underwater cable tracker.	Mach. Vis. Appl.	2002	DBLP DOI BibTeX RDF	Features detection and tracking, Pipeline inspection, Image sequences, Autonomous underwater vehicles
12	Raya Leviathan, Amir Pnueli	Validating software pipelining optimizations.	CASES	2002	DBLP DOI BibTeX RDF	optimization, verification, compilers, pipeline processors, translation validation
12	Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon	Exploiting data forwarding to reduce the power budget of VLIW embedded processors.	DATE	2001	DBLP DOI BibTeX RDF	VLIW embedded architectures, low-power, pipeline processors, forwarding
12	Dietmar Fey, Marko Degenkolb	Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	optoelectronic VLSI, signed-digit arithmetic, pipeline processing, optical interconnects, superscalar architectures
12	Chia-Lin Yang, Barton Sano, Alvin R. Lebeck	Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	geometry pipeline, paired-single instructions, 3D graphics, superscalar processors, SIMD instructions
12	Fernando Pardo, Isaac Llorens, Franciscó Mico, Jose Antonio Boluda	Space Variant Vision and Pipelined Architecture for Time to Impact Computation.	CAMP	2000	DBLP DOI BibTeX RDF	time to impact computation, avoid collision, space-variant camera, differential image processing, image processing, pipeline processing, autonomous vehicle, pipelined architecture, real-time image processing
12	Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph	High-Throughput Coherence Controllers.	HPCA	2000	DBLP DOI BibTeX RDF	Coherence Controllers, Pipeline, Microarchitecture, DSM, NUMA, Protocol Engines
12	Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube	Formal Verification for Microprocessors with Extendable Instruction Set.	ASAP	2000	DBLP DOI BibTeX RDF	reconfigurable processor architecture, abstraction techniques, formal verification, pipeline processor
12	Johann Großschädl	The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip.	ACSAC	2000	DBLP DOI BibTeX RDF	RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency
12	Bagio Budiardjo, Bobby A. A. Nazief, Djoko Hartanto	Integrated Services to Differentiated Services Packet Forwarding: Guaranteed Service to Expedited Forwarding PHB.	LCN	2000	DBLP DOI BibTeX RDF	guaranteed class-of-service flows, expedited forwarding PHB, packet forwarding algorithm, pipelined processor configuration, jitter value, packet forwarding priority, packet throughput, simulation, quality of service, QoS, packet switching, pipeline processing, differentiated services, integrated services, guaranteed service, packet loss ratio
12	Stephen L. Hary, Füsun Özgüner	Precedence-Constrained Task Allocation onto Point-to-Point Networks for Pipelined Execution.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	real-time systems, Task scheduling, direct networks, message scheduling, pipeline scheduling
12	Paul Chapman, Derek Wills, Graham R. Brookes, Peter Stevens	Visualizing Underwater Environments Using Multifrequency Sonar.	IEEE Computer Graphics and Applications	1999	DBLP DOI BibTeX RDF	seabed visualization, sonar technology, harbor wall visualization, shipwreck visualization, pipeline visualization
12	Adger E. Harvin III, José G. Delgado-Frias	A Dictionary Machine Emulation on a VLSI Computing Tree System.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	tree architectures, VLSI, data structure, pipeline computing, bit-serial, Dictionary machines
12	Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte	Path Prediction for High Issue-Rate Processors.	IEEE PACT	1997	DBLP DOI BibTeX RDF	high issue-rate processors, path prediction, issue bandwidth, multiple branches, path prediction automaton, arbitrary subgraphs, scalability single access prediction, low hardware cost, instruction-level parallelism, pipeline processing, speculative execution, cycle, performance improvement
12	Mel Slater, Yiorgos Chrysanthou	View volume culling using a probabilistic caching scheme.	VRST	1997	DBLP DOI BibTeX RDF	virtual reality walkthrough, pipeline, graphics, clipping, BSP trees, culling
12	Shobana Balakrishnan, Füsun Özgüner	Providing message delivery guarantees in pipelined flit-buffered multiprocessor networks.	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	message delivery guarantees, pipelined flit-buffered multiprocessor networks, periodic messages, multiple virtual channels, unbounded priority inversion, global priority order, flow control mechanism, preemptive pipelined circuit switching, preemption history stack, flit level simulations, feasible messages, real-time systems, parallel processing, message passing, wormhole routing, distributed memory systems, pipeline processing, real-time applications, distributed memory multiprocessors
12	S. Ramanathan, V. Visvanathan	A systolic architecture for LMS adaptive filtering with minimal adaptation delay.	VLSI Design	1996	DBLP DOI BibTeX RDF	LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm
12	Alain Guyot, Marc Renaudin, Bachar El-Hassan, Volker Levering	Self timed division and square-root extraction.	VLSI Design	1996	DBLP DOI BibTeX RDF	self-timed integrated circuit, square-root extraction, mathematical algorithm, logic level, binary notation, iterative methods, design methodology, integrated circuit design, division, dividing circuits, quotient, pipeline arithmetic, pipelined arithmetic, functional blocks
12	Shriram Kulkarni, Pinaki Mazumder, George I. Haddad	A high-speed 32-bit parallel correlator for spread spectrum communication.	VLSI Design	1996	DBLP DOI BibTeX RDF	pseudonoise codes, radio equipment, high speed pipelined digital parallel correlator, lattice field programmable gate array, 87 MHz, 11.5 ns, field programmable gate arrays, parallel processing, data stream, correlators, CDMA, pipeline processing, CMOS integrated circuit, CMOS digital integrated circuits, transceiver, spread spectrum communication, spread spectrum communication, digital radio, 32 bit, PN sequence
12	G. Enrique Fernandez, R. Sridhar	Dual rail static CMOS architecture for wave pipelining.	VLSI Design	1996	DBLP DOI BibTeX RDF	dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations
12	Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar	A multiplier generator for Xilinx FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
12	Li Cheng, Dingxing Wang, Meiming Shen, Weimin Zheng, Peng Shanling	The Compiler for Supporting Multithreading in Cyclic Register Windows.	ISPAN	1996	DBLP DOI BibTeX RDF	pipeline, Multithreading, compilation optimization, register allocation, multicomputers
12	Yooichi Shintani, Kiyoshi Inoue, Eiki Kamada, Toru Shonai	A Performance and Cost Analysis of Applying Superscalar Method to Mainframe Computers.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	CPI, operand cache, object compatibility, performance, pipeline, RISC, superscalar, CPU, OLTP, hardware cost, CISC, mainframe computer, Arithmetic unit
12	KyungHi Chang, XuDuan Lin	Ultra-high-speed digital filtering algorithm for video signal processing.	ICIP	1995	DBLP DOI BibTeX RDF	ultra-high-speed digital filtering algorithm, improved minimum-order augmented pipelining, IMAP algorithm, clustered look-ahead technique, augmented pipelining order, undesirable quantization effects, 1-D IMAP digital filter, 2-D structure, bandwidth reduction algorithm, motion estimation, motion estimation, pipeline processing, minimization, minimisation, video signal processing, video signal processing, interference suppression, two-dimensional digital filters, spatio-temporal filtering