Search results for "D-latch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura	A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA.	DSD	2002	DBLP DOI BibTeX RDF
11	Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster	Tradeoffs in power-efficient issue queue design.	ISLPED	2002	DBLP DOI BibTeX RDF	non-compacting, adaptation, low-power, microarchitecture, compacting, banking, issue queue
11	Hong-Yi Huang, Jing-Fu Lin	CMOS bulk input technique.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
11	Ming-Dou Ker, Kuo-Chun Hsu	On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
11	G. A. Al-Rawi	A new offset measurement and cancellation technique for dynamic latches.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
11	Bill Pontikakis, Mohamed Nekili	A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
11	Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	Logic synthesis for PLA with 2-input logic elements.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
11	Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	logic synthesis, PLA
11	Hai Zhou 0001	Clock schedule verification with crosstalk.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	verification, delay, coupling, clock schedule
11	Martin Foltin, Brian Foutz, Sean Tyler	Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency.	DAC	2002	DBLP DOI BibTeX RDF	timing analysis, VLSI design, timing model, circuit optimization
11	Cho W. Moon, Harish Kriplani, Krishna P. Belkhale	Timing model extraction of hierarchical blocks by graph reduction.	DAC	2002	DBLP DOI BibTeX RDF
11	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	Bisimulation relation, complete-1-distinguishability, finite state machine equivalence, sequential logic synthesis, equivalence checking
11	Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata	Test circuits for substrate noise evaluation in CMOS digital ICs.	ASP-DAC	2001	DBLP DOI BibTeX RDF
11	Frank Wolz, Reiner Kolla	Bubble Partitioning for LUT-Based Sequential Circuits.	FPL	2001	DBLP DOI BibTeX RDF
11	Qing K. Zhu, Michael Zhang	Low-voltage swing clock distribution schemes.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
11	Samgsuk Kim, Minkyu Song	An 8-bit 200 MSPS CMOS A/D converter for analog interface module of TFT-LCD driver.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
11	Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang	New current-mode sense amplifiers for high density DRAM and PIM architectures.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
11	Christian Jesús B. Fayomi, Gordon W. Roberts, Mohamad Sawan	A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 um CMOS technology.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
11	Sepp Hochreiter, Michael Mozer	A Discrete Probabilistic Memory Model for Discovering Dependencies in Time.	ICANN	2001	DBLP DOI BibTeX RDF
11	Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata	Measurements and analyses of substrate noise waveform inmixed-signal IC environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
11	Hussain Al-Asaad, John P. Hayes	Logic Design Validation via Simulation and Automatic Test Pattern Generation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	test generation, logic design, fault simulation, error modeling, design validation
11	Jacob Savir	Distributed BIST Architecture to Combat Delay Faults.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	BIST, LFSR, delay test, MISR, LSSD, SRL
11	Montek Singh, Steven M. Nowick	High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths.	ASYNC	2000	DBLP DOI BibTeX RDF	fine-grain pipelining, VLSI, pipelines, asynchronous, dynamic logic, FIFO, high-throughput, digital design
11	David M. Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose	Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor.	PACS	2000	DBLP DOI BibTeX RDF
11	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith	Timing constraints for high-speed counterflow-clocked pipelining.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
11	Naresh Maheshwari, Sachin S. Sapatnekar	Optimizing large multiphase level-clocked circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
11	Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz	Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists.	CAV	1999	DBLP DOI BibTeX RDF
11	Kenneth Y. Yun, Ayoob E. Dooply	Optimal Evaluation Clocking of Self-Resetting Domino Pipelines.	ASP-DAC	1999	DBLP DOI BibTeX RDF
11	Toshio Murayama, Kimihiro Ogawa, Haruhiko Yamaguchi	Estimation of Peak Current through CMOS VLSI Circuit Supply Lines.	ASP-DAC	1999	DBLP DOI BibTeX RDF
11	J. V. Tran, Farnaz Mounes-Toussi, S. N. Storino, D. L. Stasiak	SOI Implementation of a 64-Bit Adder.	ICCD	1999	DBLP DOI BibTeX RDF
11	Jacob Savir	Design for Testability to Combat Delay Faults.	ICCD	1999	DBLP DOI BibTeX RDF	BIST, LFSR, Delay Test, MISR, LSSD, SRL
11	Costantino Pala, Gerd Schuppener, Mehran Mokhtari	A 6 GHz, 1.8 V, divide-by-2 circuit implemented in silicon bipolar technology.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
11	Ayoob E. Dooply, Kenneth Y. Yun	Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines.	ARVLSI	1999	DBLP DOI BibTeX RDF	Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault
11	Tetsuya Uemura, Pinaki Mazumder	Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
11	Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev	Hazard-free implementation of speed-independent circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
11	Kåre Tais Christensen, Peter Jensen, Peter Korger, Jens Sparsø	The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core.	ASYNC	1998	DBLP DOI BibTeX RDF	Asynchronous circuits and systems, low-power, microprocessor design
11	Weiyu Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	Test generation in VLSI circuits for crosstalk noise.	ITC	1998	DBLP DOI BibTeX RDF
11	S. K. Misra, R. K. Kolagotla, Hosahalli R. Srinivas, J. C. Mo, Marc S. Diamondstein	VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay.	VLSI Design	1998	DBLP DOI BibTeX RDF	Fast counter, VLSI, Testability
11	Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar	A hierarchical decomposition methodology for multistage clock circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	performance driven router, routing, process variations, manufacturability, clock
11	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin	Partial scan delay fault testing of asynchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	robust path delay fault testing, asynchronous circuits, delay faults, sequential testing
11	Naresh Maheshwari, Sachin S. Sapatnekar	Minimum area retiming with equivalent initial states.	ICCAD	1997	DBLP DOI BibTeX RDF	VLSI, Sequential Circuits, Retiming, Design Automation, Timing Optimization, Area Optimization
11	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ICCAD	1996	DBLP DOI BibTeX RDF	sequential logic synthesis and verification, finite state machine equivalence, bisimulation relation, 1-distinguishability, 1-equivalence, formal verification
11	Andrea Boni, Carlo Morandi	Low-Power, Low-Voltage BiCMOS Comparators for Approximately 200MHz, 8bit Operation.	VLSI Design	1996	DBLP DOI BibTeX RDF
11	Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge	Critical paths in circuits with level-sensitive latches.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
11	K. Wayne Current	Memory Circuits for Multiple-Valued Logic Voltage Signals.	ISMVL	1995	DBLP DOI BibTeX RDF	memory circuits, multiple valued logic voltage signals, voltage-mode CMOS multiple valued logic memory circuits, polysilicon-gate CMOS technology, SETUP clock mode, HOLD clock mode, multivalued logic circuits, integrated memory circuits, CMOS memory circuits
11	Erik Brunvand	Low latency self-timed flow-through FIFOs.	ARVLSI	1995	DBLP DOI BibTeX RDF	self-timed flow-through FIFO, linear flow-through FIFO, parallel FIFO, tree FIFO, square FIFO, folded FIFO, low latency type, field programmable gate arrays, VLSI, asynchronous circuits, CMOS logic circuits
11	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews	High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.	ARVLSI	1995	DBLP DOI BibTeX RDF	counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
11	Ted E. Williams	Performance of iterative computation in self-timed rings.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
11	Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson	Synchronization of pipelines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
11	Gordon J. Brebner	Configurable array logic circuits for computing network error detection codes.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
11	Steve Vinoski	RISE++: A Symbolic Environment for Scan-Based Testing.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
11	Srinivas Devadas	Optimizing interacting finite state machines using sequential don't cares.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
11	Robert Tjärnström	Automatic generation of timing specifications for CMOS transistor subnetworks.	EURO-DAC	1990	DBLP DOI BibTeX RDF
11	Michael Magee, William A. Hoff, Lance Gatrell, Martin Marietta, William J. Wolfe	Integrated Planning of Robotic and Computer Bision Based Spatial Reasoning Tasks.	IEA/AIE (Vol. 1)	1990	DBLP DOI BibTeX RDF
11	Miriam Leeser	Reasoning about the function and timing of integrated circuits with interval temporal logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
11	R. J. McDonald, Jerry G. Fossum	High-voltage device modeling for SPICE simulation of HVIC's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
11	C. Thomas Glover, M. Ray Mercer	A Method of Delay Fault Test Generation.	DAC	1988	DBLP BibTeX RDF
11	Peter Odryna, Kevin Nazareth, Carl Christensen	A workstation-mixed model circuit simulator.	DAC	1986	DBLP DOI BibTeX RDF
11	Matthew S. Hecht, Jeffrey D. Ullman	Characterizations of Reducible Flow Graphs.	J. ACM	1974	DBLP DOI BibTeX RDF