Search results for "DFT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto, Luigi Pomante	Reliable System Co-Design: The FIR Case Study.	DFT	2004	DBLP DOI BibTeX RDF
1	Nitin Parimi, Xiaoling Sun	Toggle-Masking for Test-per-Scan VLSI Circuits.	DFT	2004	DBLP DOI BibTeX RDF
1	Jing Huang 0001, Mariam Momenzadeh, Mehdi Baradaran Tahoori, Fabrizio Lombardi	Defect Characterization for Scaling of QCA Devices.	DFT	2004	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy 0001	First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.	DFT	2004	DBLP DOI BibTeX RDF
1	Adão Antônio de Souza Jr., Luigi Carro	Robust Low-Cost Analog Signal Acquisition with Self-Test Capabilities.	DFT	2004	DBLP DOI BibTeX RDF
1	Michele Favalli	Annotated Bit Flip Fault Model.	DFT	2004	DBLP DOI BibTeX RDF
1	Shanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi	Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment.	DFT	2004	DBLP DOI BibTeX RDF
1	Yukiya Miura	Fault Diagnosis of Analog Circuits by Operation-Region Model and X-Y Zoning Method.	DFT	2004	DBLP DOI BibTeX RDF
1	Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu	An Application-Independent Delay Testing Methodology for Island-Style FPGA.	DFT	2004	DBLP DOI BibTeX RDF	segment delay fault, FPGA, delay testing, path delay fault
1	John Y. Fong, Randy Acklin, John Roscher, Feng Li, Cindy Laird, Cezary Pietrzyk	Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories.	DFT	2004	DBLP DOI BibTeX RDF
1	Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson	Online Testable Reversible Logic Circuit Design using NAND Blocks.	DFT	2004	DBLP DOI BibTeX RDF
1	Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali	Defect Avoidance in a 3-D Heterogeneous Sensor.	DFT	2004	DBLP DOI BibTeX RDF
1	Michele Favalli	"Victim Gate" Crosstalk Fault Model.	DFT	2004	DBLP DOI BibTeX RDF
1	Stefano Bertazzoni, Domenico Di Giovenale, Marcello Salmeri, Arianna Mencattini, Adelio Salsano, M. Florean, Jeffery Wyss, Ricardo Rando, Silvano Lora	Monitoring Methodology for TID Damaging of SDRAM Devices based on Retention Time Analysis.	DFT	2004	DBLP DOI BibTeX RDF
1	Brian Peng, Ing-Yi Chen, Sy-Yen Kuo, Colin Bolger	IC HTOL Test Stress Condition Optimization.	DFT	2004	DBLP DOI BibTeX RDF
1	Hung-Yau Lin, Fu-Min Yeh, Ing-Yi Chen, Sy-Yen Kuo	An Efficient Perfect Algorithm for Memory Repair Problems.	DFT	2004	DBLP DOI BibTeX RDF
1	Ammar Aljer, Philippe Devienne	Co-Design and Refinement for Safety Critical Systems.	DFT	2004	DBLP DOI BibTeX RDF
1	Jerzy J. Dabrowski, Javier Gonzalez Bayon	Mixed Loopback BiST for RF Digital Transceivers.	DFT	2004	DBLP DOI BibTeX RDF
1	Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui	Learning Based on Fault Injection and Weight Restriction for Fault-Tolerant Hopfield Neural Networks.	DFT	2004	DBLP DOI BibTeX RDF
1	Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu	Failure Factor Based Yield Enhancement for SRAM Designs.	DFT	2004	DBLP DOI BibTeX RDF
1	Shanrui Zhang, Minsu Choi, Nohpill Park	Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with h-hot Addressing Scheme.	DFT	2004	DBLP DOI BibTeX RDF
1	Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri	An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost.	DFT	2004	DBLP DOI BibTeX RDF
1	Masaru Fukushi, Susumu Horiguchi	Reconfiguration Algorithm for Degradable Processor Arrays Based on Row and Column Rerouting.	DFT	2004	DBLP DOI BibTeX RDF
1	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Fast and Low-Cost Clock Deskew Buffer.	DFT	2004	DBLP DOI BibTeX RDF
1	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	Data Integrity Evaluations of Reed Solomon Codes for Storage Systems.	DFT	2004	DBLP DOI BibTeX RDF
1	Hamidreza Hashempour, Luca Schiano, Fabrizio Lombardi	Error-Resilient Test Data Compression Using Tunstall Codes.	DFT	2004	DBLP DOI BibTeX RDF
1	Roman Barsky, Israel A. Wagner	Reliability and Yield: A Joint Defect-Oriented Approach.	DFT	2004	DBLP DOI BibTeX RDF
1	Najwa Aaraj, Anis Nazer, Ali Chehab, Ayman I. Kayssi	Transient Current Testing of Dynamic CMOS Circuits.	DFT	2004	DBLP DOI BibTeX RDF
1	Gang Zeng, Hideo Ito	Non-Intrusive Test Compression for SOC Using Embedded FPGA Core.	DFT	2004	DBLP DOI BibTeX RDF
1	Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel	Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model.	DFT	2004	DBLP DOI BibTeX RDF
1	Ping-Hsun Hsieh, Ing-Yi Chen, Yu-Ting Lin, Sy-Yen Kuo	An XOR Based Reed-Solomon Algorithm for Advanced RAID Systems.	DFT	2004	DBLP DOI BibTeX RDF
1	Arvind Kumar, Sandip Tiwari	Testing and Defect Tolerance: A Rent's Rule Based Analysis and Implications on Nanoelectronics.	DFT	2004	DBLP DOI BibTeX RDF
1	Jennifer Dworak, James Wingfield, M. Ray Mercer	A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects.	DFT	2004	DBLP DOI BibTeX RDF
1	Tao Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer	Reliability Modeling and Assurance of Clockless Wave Pipeline.	DFT	2004	DBLP DOI BibTeX RDF
1	Michelle L. La Haye, Glenn H. Chapman, Cory Jung, Desmond Y. H. Cheung, Sunjaya Djaja, Benjamin Wang, Gary Liaw, Yves Audet	Characteristics of Fault-Tolerant Photodiode and Photogate Active Pixel Sensor (APS).	DFT	2004	DBLP DOI BibTeX RDF
1	Mohamed Abbas, Makoto Ikeda, Kunihiro Asada	Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime.	DFT	2004	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines.	DFT	2004	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors.	DFT	2004	DBLP DOI BibTeX RDF
1	Carlos Arthur Lang Lisbôa, Luigi Carro	Arithmetic Operators Robust to Multiple Simultaneous Upsets.	DFT	2004	DBLP DOI BibTeX RDF
1	Andrzej Krasniewski	Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs.	DFT	2004	DBLP DOI BibTeX RDF
1	Alexandre Schmid, Yusuf Leblebici	A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies.	DFT	2004	DBLP DOI BibTeX RDF
1	Yung-Yuan Chen, Kun-Feng Chen	Incorporating Signature-Monitoring Technique in VLIW Processors.	DFT	2004	DBLP DOI BibTeX RDF
1	Régis Leveugle, D. Cimonnet, Abdelaziz Ammari	System-Level Dependability Analysis with RT-Level Fault Injection Accuracy.	DFT	2004	DBLP DOI BibTeX RDF
1	Xiaopeng Wang, Marco Ottavi, Fabrizio Lombardi	Testing of Inter-Word Coupling Faults in Word-Oriented SRAMs.	DFT	2004	DBLP DOI BibTeX RDF	inter-word fault, testing, memory, detection, Coupling fault
1	Matteo Sonza Reorda, Massimo Violante	On-Line Analysis and Perturbation of CAN Networks.	DFT	2004	DBLP DOI BibTeX RDF
1	Lorena Anghel, Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero, Raoul Velazco	Coupling Different Methodologies to Validate Obsolete Microprocessors.	DFT	2004	DBLP DOI BibTeX RDF
1	Baosheng Wang, Yuejian Wu, André Ivanov	Designs for Reducing Test Time of Distributed Small Embedded SRAMs.	DFT	2004	DBLP DOI BibTeX RDF	Distributed Small Embedded SRAMs, Data Retention Fault Test, Response Analysis, Test Time
1	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	At-Speed Functional Verification of Programmable Devices.	DFT	2004	DBLP DOI BibTeX RDF
1	Hamidreza Hashempour, Fabrizio Lombardi	Compression of VLSI Test Data by Arithmetic Coding.	DFT	2004	DBLP DOI BibTeX RDF
1	Xiaopeng Wang, Marco Ottavi, Fred J. Meyer, Fabrizio Lombardi	On The Yield of Compiler-Based eSRAMs.	DFT	2004	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting an I-IP for In-Field SOC Test.	DFT	2004	DBLP DOI BibTeX RDF
1	Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars.	DFT	2004	DBLP DOI BibTeX RDF
1	Wangqi Qiu, Xiang Lu, Zhuo Li 0001, D. M. H. Walker, Weiping Shi	CodSim -- A Combined Delay Fault Simulator.	DFT	2003	DBLP DOI BibTeX RDF
1	Bai Hong Fang, Nicola Nicolici	Power-Constrained Embedded Memory BIST Architecture.	DFT	2003	DBLP DOI BibTeX RDF
1	Daniele Rossi 0001, S. Cavallotti, Cecilia Metra	Error Correcting Codes for Crosstalk Effect Minimization.	DFT	2003	DBLP DOI BibTeX RDF
1	Marco S. Dragic, Martin Margala	Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits.	DFT	2003	DBLP DOI BibTeX RDF
1	John Marty Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani	An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals.	DFT	2003	DBLP DOI BibTeX RDF
1	Vikram Iyengar, Anshuman Chandra	A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design.	DFT	2003	DBLP DOI BibTeX RDF
1	Vijay K. Jain, Glenn H. Chapman	Level-Hybrid Optoelectronic TESH Interconnection Network.	DFT	2003	DBLP DOI BibTeX RDF
1	Luca Schiano, Fabrizio Lombardi	On the Test and Diagnosis of the Perfect Shuffle.	DFT	2003	DBLP DOI BibTeX RDF
1	James Wingfield, Jennifer Dworak, M. Ray Mercer	Function-Based Dynamic Compaction and its Impact on Test Set Sizes.	DFT	2003	DBLP DOI BibTeX RDF
1	Konstantinos Rokas, Yiorgos Makris, Dimitris Gizopoulos	Low Cost Convolutional Code Based Concurrent Error Detection in FSMs.	DFT	2003	DBLP DOI BibTeX RDF
1	Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin	Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture.	DFT	2003	DBLP DOI BibTeX RDF
1	Cecilia Metra, T. M. Mak, Daniele Rossi 0001	Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors.	DFT	2003	DBLP DOI BibTeX RDF
1	Rob Aitken, Neeraj Dogra, Dhrumil Gandhi, Scott Becker	Redundancy, Repair, and Test Features of a 90nm Embedded SRAM Generator.	DFT	2003	DBLP DOI BibTeX RDF
1	Ching-Hwa Cheng	Design Scan Test Strategy for Single Phase Dynamic Circuits.	DFT	2003	DBLP DOI BibTeX RDF
1	Ying Zhang 0041, Krishnendu Chakrabarty	Fault Recovery Based on Checkpointing for Hard Real-Time Embedded Systems.	DFT	2003	DBLP DOI BibTeX RDF
1	Rafic A. Ayoubi, Haissam Ziade, Magdy A. Bayoumi	Fault Tolerant Hopfield Associative Memory on Torus.	DFT	2003	DBLP DOI BibTeX RDF
1	Eiko Sugawara, Masaru Fukushi, Susumu Horiguchi	Fault Tolerant Multi-Layer Neural Networks with GA Training.	DFT	2003	DBLP DOI BibTeX RDF
1	Gang Zeng, Hideo Ito	Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core.	DFT	2003	DBLP DOI BibTeX RDF
1	Fulvio Corno, Simonluca Tosato, Paolo Gabrielli	System-Level Analysis of Fault Effects in an Automotive Environment.	DFT	2003	DBLP DOI BibTeX RDF
1	Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante	Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels.	DFT	2003	DBLP DOI BibTeX RDF
1	Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy 0001	Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.	DFT	2003	DBLP DOI BibTeX RDF
1	Atul Maheshwari, Israel Koren, Wayne P. Burleson	Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits.	DFT	2003	DBLP DOI BibTeX RDF
1	Dirk K. de Vries, Paul L. C. Simon	Calibration of Open Interconnect Yield Models.	DFT	2003	DBLP DOI BibTeX RDF
1	Meng Lu, Yvon Savaria, Bing Qiu 0003, Jacques Taillefer	IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration.	DFT	2003	DBLP DOI BibTeX RDF
1	Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.	Quadruple Time Redundancy Adders.	DFT	2003	DBLP DOI BibTeX RDF
1	Kedarnath J. Balakrishnan, Nur A. Touba	Scan-Based BIST Diagnosis Using an Embedded Processor.	DFT	2003	DBLP DOI BibTeX RDF
1	Parag K. Lala	A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems.	DFT	2003	DBLP DOI BibTeX RDF
1	Michael Nicolaidis, Nadir Achouri, Lorena Anghel	A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities.	DFT	2003	DBLP DOI BibTeX RDF
1	Lorena Anghel, Raoul Velazco, S. Saleh, S. Deswaertes, A. El Moucary	Preliminary Validation of an Approach Dealing with Processor Obsolescence.	DFT	2003	DBLP DOI BibTeX RDF
1	Kartik Mohanram, Nur A. Touba	Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits.	DFT	2003	DBLP DOI BibTeX RDF
1	Adam B. Kinsman, Jonathan I. Hewitt, Nicola Nicolici	Embedded Compact Deterministic Test for IP-Protected Cores.	DFT	2003	DBLP DOI BibTeX RDF
1	Jerzy J. Dabrowski	BiST Model for IC RF-Transceiver Front-End.	DFT	2003	DBLP DOI BibTeX RDF
1	Julio Pérez, Matteo Sonza Reorda, Massimo Violante	Dependability Analysis of CAN Networks: An Emulation-Based Approach.	DFT	2003	DBLP DOI BibTeX RDF
1		18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings	DFT	2003	DBLP BibTeX RDF
1	Monica Alderighi, Fabio Casini, Sergio D'Angelo, Marcello Mancini, A. Marmo, Sandro Pastore, Giacomo R. Sechi	A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs.	DFT	2003	DBLP DOI BibTeX RDF
1	Cecilia Metra, Stefano Di Francescantonio, Martin Omaña 0001	Automatic Modification of Sequential Circuits for Self-Checking Implementation.	DFT	2003	DBLP DOI BibTeX RDF
1	Fengming Zhang, Young-Jun Lee, Thomas Kane, Luca Schiano, Mariam Momenzadeh, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi, Solomon Max, Phil Perkinson	A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment.	DFT	2003	DBLP DOI BibTeX RDF
1	Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri	Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard.	DFT	2003	DBLP DOI BibTeX RDF
1	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	Error Detection in Signed Digit Arithmetic Circuit with Parity Checker.	DFT	2003	DBLP DOI BibTeX RDF
1	John Marty Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani	A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits.	DFT	2003	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Fabio Salice, Donatella Sciuto, R. Zavaglia	An Integrated Design Approach for Self-Checking FPGAs.	DFT	2003	DBLP DOI BibTeX RDF
1	Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi	Thermal Management of High Performance Microprocessors.	DFT	2003	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori	Application-Dependent Testing of FPGA Interconnects.	DFT	2003	DBLP DOI BibTeX RDF
1	Sunjaya Djaja, Glenn H. Chapman, Desmond Y. H. Cheung, Yves Audet	Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS).	DFT	2003	DBLP DOI BibTeX RDF	photodiode APS, fault-tolerance, redundancy, SOC, CMOS image sensor, active pixel sensor
1	Hiroshi Takahashi, Yasunori Tsugaoka, Hidekazu Ayano, Yuzo Takamatsu	BIST Based Fault Diagnosis Using Ambiguous Test Set.	DFT	2003	DBLP DOI BibTeX RDF
1	Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng	Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip.	DFT	2003	DBLP DOI BibTeX RDF
1	Tao Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri	Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults.	DFT	2003	DBLP DOI BibTeX RDF
1	Abhijit Prasad, D. M. H. Walker	Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors.	DFT	2003	DBLP DOI BibTeX RDF

Publications at "DFT"( http://dblp.L3S.de/Venues/DFT )