Search results for "FPGAs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Akshay Sharma, Carl Ebeling, Scott Hauck	Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
16	Edward D. Moreno, Fábio Dacêncio Pereira, Rodolfo B. Chiaramonte	A VLIW-based cryptoprocessor on FPGAs architecture and performance issues (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
16	Jin Hwan Park	Reconfigurable Parallel Approximate String Matching on FPGAs.	DSD	2005	DBLP DOI BibTeX RDF
16	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
16	João Canas Ferreira, Miguel M. Silva	Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer.	IPDPS	2005	DBLP DOI BibTeX RDF
16	Andres Upegui, Eduardo Sanchez	Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs.	ICES	2005	DBLP DOI BibTeX RDF
16	R. James Duckworth	Embedded System Design with FPGAs Using HDLs (Lessons Learned and Pitfalls to Be Avoided).	MSE	2005	DBLP DOI BibTeX RDF
16	Jasmine Lam, John McAllister, Jennifer Dudley	Core-Based Methodology: An Automated Approach for Implementing a Complete System from Algorithms to a Heterogeneous Network including FPGAs.	FCCM	2005	DBLP DOI BibTeX RDF
16	Radu Teodorescu, Josep Torrellas	Prototyping Architectural Support for Program Rollback Using FPGAs.	FCCM	2005	DBLP DOI BibTeX RDF
16	Miguel A. Vega-Rodríguez, Raul Gutierrez-Gil, Jose M. Avila-Roman, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido	Genetic Algorithms Using Parallelism and FPGAs: The TSP as Case Study.	ICPP Workshops	2005	DBLP DOI BibTeX RDF
16	Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi	Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
16	Andrzej Krasniewski	A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory.	IOLTS	2005	DBLP DOI BibTeX RDF
16	Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes	Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading.	IOLTS	2005	DBLP DOI BibTeX RDF
16	Peter M. Kelly, T. Martin McGinnity, Liam P. Maguire	Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems.	ASAP	2005	DBLP DOI BibTeX RDF
16	Ling Zhuo, Viktor K. Prasanna	High-Performance and Area-Efficient Reduction Circuits on FPGAs.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
16	Renqiu Huang, Ranga Vemuri	On-Line Synthesis for Partially Reconfigurable FPGAs.	VLSI Design	2005	DBLP DOI BibTeX RDF
16	R. Manimegalai, E. Siva Soumya, Vaishnavi Muralidharan, Balaraman Ravindran, V. Kamakoti 0001, D. Bhatia	Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines.	VLSI Design	2005	DBLP DOI BibTeX RDF	Three-Dimensional FPGA, Reinforcement Learning (RL), Two-opt algorithm, Support Vector Machines (SVMs), Placement and Routing
16	Krishna Prasad Raghuraman, Haibo Wang 0005, Spyros Tragoudas	A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs.	VLSI Design	2005	DBLP DOI BibTeX RDF
16	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs.	VLSI Design	2005	DBLP DOI BibTeX RDF	Complex Logic Blocks, Routing Errors, Vertex Coloring problem, Fault Tolerance, Field Programmable Gate Arrays, Graph Theory, Single Event Upset
16	Damien Baumann, Jacques Tinembart	Designing Mathematical Morphology Algorithms on FPGAs: An Application to Image Processing.	CAIP	2005	DBLP DOI BibTeX RDF
16	Marvin Tom, Guy G. Lemieux	Logic block clustering of large designs for channel-width constrained FPGAs.	DAC	2005	DBLP DOI BibTeX RDF	channel width constraints, clustering, field-programmable gate arrays (FPGA), packing
16	Wai-Kei Mak	I/O placement for FPGAs with multiple I/O standards.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
16	Seok-Bum Ko, Jien-Chung Lo	Efficient Realization of Parity Prediction Functions in FPGAs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	parity prediciton functions, Davio''s expansion, AND/XOR expressions, FPGA, technology mapping
16	Seok-Bum Ko	Area Minimization of Exclusive-OR Intensive Circuits in FPGAs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	FPGA, XOR, ESOP
16	Abdsamad Benkrid, Khaled Benkrid, Danny Crookes	Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs.	ISVLSI	2004	DBLP DOI BibTeX RDF
16	Navaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis	Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources.	FPGA	2004	DBLP DOI BibTeX RDF
16	Ian Kuon, Aaron Egier, Jonathan Rose	Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
16	Andrea Lodi 0002, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Mario Toma, Fabio Campi	Routing architecture for multi-context FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
16	Alex Fit-Florea, Miroslav Halás, Fatih Kocan	Enhancing Reliability of Operational Interconnections in FPGAs.	DATE	2004	DBLP DOI BibTeX RDF
16	A. Manoj Kumar, Jayaram Bobba, V. Kamakoti 0001	MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis.	DATE	2004	DBLP DOI BibTeX RDF
16	Alex Panato, Sandro V. Silva, Flávio Rech Wagner, Marcelo O. Johann, Ricardo Reis 0001, Sergio Bampi	Design of Very Deep Pipelined Multipliers for FPGAs.	DATE	2004	DBLP DOI BibTeX RDF
16	Anurag Tiwari, Karen A. Tomko	Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs.	DATE	2004	DBLP DOI BibTeX RDF
16	Luo Jianwen, Jong Ching Chuen	Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs.	DSD	2004	DBLP DOI BibTeX RDF
16	Chang Woo Kang, Ali Iranli, Massoud Pedram	Technology mapping and packing for coarse-grained, anti-fuse based FPGAs.	ASP-DAC	2004	DBLP DOI BibTeX RDF
16	Jason Helge Anderson, Farid N. Najm	Interconnect capacitance estimation for FPGAs.	ASP-DAC	2004	DBLP DOI BibTeX RDF
16	Rawat Siripokarpirom	Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
16	R. Manimegalai, A. Manoj Kumar, B. Jayaram 0002, V. Kamakoti 0001	MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks.	FPL	2004	DBLP DOI BibTeX RDF
16	Dong-U Lee, Oskar Mencer, David J. Pearce 0001, Wayne Luk	Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
16	Wim Roelandts	FPGAs and the Era of Field Programmability.	FPL	2004	DBLP DOI BibTeX RDF
16	Andrzej Krasniewski	Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory.	FPL	2004	DBLP DOI BibTeX RDF
16	Gang Chen 0020, Jason Cong	Simultaneous Timing Driven Clustering and Placement for FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
16	Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko	BIST Based Interconnect Fault Location for FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
16	Donald W. Bouldin	Impacting Education Using FPGAs.	IPDPS	2004	DBLP DOI BibTeX RDF
16	A. Manoj Kumar, B. Jayaram 0002, R. Manimegalai, V. Kamakoti 0001	MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays.	IPDPS	2004	DBLP DOI BibTeX RDF
16	Steven D. Krueger, Peter-Michael Seidel	Design of an On-Line IEEE Floating-Point Addition Unit for FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF	IEEE rounding, Floating-point addition, on-line arithmetic
16	Hassan Al Atat, Iyad Ouaiss	Register Binding for FPGAs with Embedded Memory.	FCCM	2004	DBLP DOI BibTeX RDF
16	Jingzhao Ou, Viktor K. Prasanna	PyGen: A MATLAB/Simulink Based Tool for Synthesizing Parameterized and Energy Efficient Designs Using FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
16	Emre Özer 0001, Andy Nisbet, David Gregg	Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
16	Philip James-Roxby, Paul R. Schumacher, Charlie Ross	A Single Program Multiple Data Parallel Processing Platform for FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
16	Neil Steiner, Peter M. Athanas	An Alternate Wire Database for Xilinx FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
16	Renqiu Huang, Ranga Vemuri	Analysis and evaluation of a hybrid interconnect structure for FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
16	Fernanda Lima Kastensmidt, Gustavo Neuberger, Luigi Carro, Ricardo Reis 0001	Designing and testing fault-tolerant techniques for SRAM-based FPGAs.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	fault-tolerance, FPGA
16	John C. Lach, Jason Brandon, Kevin Skadron	A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs.	ICCD	2004	DBLP DOI BibTeX RDF
16	Fabio Sousa, Volker Mauer, Neimar Duarte, Ricardo P. Jasinski, Volnei A. Pedroni	Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
16	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs.	IOLTS	2004	DBLP DOI BibTeX RDF
16	Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee	Macro-models for high level area and power estimation on FPGAs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	model, FPGA, high-level synthesis, power estimation, RTL, area estimation
16	Andrzej Krasniewski	Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs.	DFT	2004	DBLP DOI BibTeX RDF
16	Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure	A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs.	VTS	2004	DBLP DOI BibTeX RDF
16	Mehdi Baradaran Tahoori	Application-Dependent Diagnosis of FPGAs.	ITC	2004	DBLP DOI BibTeX RDF
16	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	High Quality TPG for Delay Faults in Look-Up Tables of FPGAs.	DELTA	2004	DBLP DOI BibTeX RDF
16	Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali	Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs.	PRDC	2004	DBLP DOI BibTeX RDF
16	Nobuyuki Ohba, Kohji Takano	An SoC design methodology using FPGAs and embedded microprocessors.	DAC	2004	DBLP DOI BibTeX RDF	mixed-level verification, SoC, ASIC, FPGA prototyping
16	Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat	Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	FPGA, Cryptography, DES, linear cryptanalysis, efficient implementations
16	Wai-Kei Mak	I/O placement for FPGAs with multiple I/O standards.	FPGA	2003	DBLP DOI BibTeX RDF	I/O placement, I/O standards, field-programmable gate array, placement
16	Fei Li 0003, Deming Chen, Lei He 0001, Jason Cong	Architecture evaluation for power-efficient FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA power model, low power design, FPGA architecture
16	Prithviraj Banerjee, Vikram Saxena, Juan Ramon Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, Robert Anderson	Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
16	Akshay Sharma, Carl Ebeling, Scott Hauck	PipeRoute: a pipelining-aware router for FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	BFS, PipeRoute, retimed circuits, routing, pipelining, minimum spanning tree, retiming, pipelined circuits
16	Brandon Blodget, Scott McMillan, Patrick Lysaght	A Lightweight Approach for Embedded Reconfiguration of FPGAs.	DATE	2003	DBLP DOI BibTeX RDF
16	Ulrich Seidl, Klaus Eckl, Frank M. Johannes	Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information.	DATE	2003	DBLP DOI BibTeX RDF
16	Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha	An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs.	DSD	2003	DBLP DOI BibTeX RDF
16	Jorge Barreiros, Ernesto Costa	Global Routing for Lookup-Table Based FPGAs Using Genetic Algorithms.	FPL	2003	DBLP DOI BibTeX RDF
16	Fernando E. Ortiz, John R. Humphrey, James P. Durbano, Dennis W. Prather	A Study on the Design of Floating-Point Functions in FPGAs.	FPL	2003	DBLP DOI BibTeX RDF
16	Seonil Choi, Viktor K. Prasanna	Time and Energy Efficient Matrix Factorization Using FPGAs.	FPL	2003	DBLP DOI BibTeX RDF
16	Patrick Lysaght	Future Design Tools for Platform FPGAs.	SBCCI	2003	DBLP DOI BibTeX RDF
16	Herbert Walder, Christoph Steiger, Marco Platzner	Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.	IPDPS	2003	DBLP DOI BibTeX RDF	FGPA, placement, task
16	Jason D. Lohn, Gregory V. Larchev, Ronald F. DeMara	A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs.	ICES	2003	DBLP DOI BibTeX RDF
16	Xiaojun Wang, Brent E. Nelson	Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs.	FCCM	2003	DBLP DOI BibTeX RDF
16	Seokjin Lee, Yongseok Cheon, Martin D. F. Wong	A Min-Cost Flow Based Detailed Router for FPGAs.	ICCAD	2003	DBLP DOI BibTeX RDF	min-cost flow algorithm, Lagrangian relaxation, FPGA routing
16	Micaela Serra, Kenneth B. Kent	Using FPGAs to solve the Hamiltonian cycle problem.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
16	Andrea Lodi 0002, Carlo Chiesa, Fabio Campi, Mario Toma	A flexible LUT-based carry chain for FPGAs.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
16	Francisco Cardells-Tormo, Javier Valls-Coquillat	Quadrature direct digital frequency synthesizers: area-optimized design map for LUT-based FPGAs.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
16	Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung	Architectures for function evaluation on FPGAs.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
16	Monica Alderighi, Sergio D'Angelo, Marcello Mancini, Giacomo R. Sechi	A Fault Injection Tool for SRAM-based FPGAs.	IOLTS	2003	DBLP DOI BibTeX RDF
16	Monica Alderighi, Fabio Casini, Sergio D'Angelo, Marcello Mancini, A. Marmo, Sandro Pastore, Giacomo R. Sechi	A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs.	DFT	2003	DBLP DOI BibTeX RDF
16	Cristiana Bolchini, Fabio Salice, Donatella Sciuto, R. Zavaglia	An Integrated Design Approach for Self-Checking FPGAs.	DFT	2003	DBLP DOI BibTeX RDF
16	Seda Ogrenci Memik, Gokhan Memik, Roozbeh Jafari, Eren Kursun	Global resource sharing for synthesis of control data flow graphs on FPGAs.	DAC	2003	DBLP DOI BibTeX RDF	control data flow graph, FPGA, resource sharing
16	Navin Vemuri, Priyank Kalla, Russell Tessier	BDD-based logic synthesis for LUT-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	FPGA, decomposition, logic synthesis, BDD
16	Amit Singh 0001, Malgorzata Marek-Sadowska	Efficient circuit clustering for area and power reduction in FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF
16	Oswaldo Cadenas, Graham M. Megson	Improving mW/MHz Ratio in FPGAs Pipelined Designs.	DSD	2002	DBLP DOI BibTeX RDF
16	Seok-Bum Ko, Jien-Chung Lo	Efficient Decomposition Techniques for FPGAs.	HiPC	2002	DBLP DOI BibTeX RDF
16	Jacir Luiz Bordim, Yasuaki Ito, Koji Nakano	Accelerating the CKY Parsing Using FPGAs.	HiPC	2002	DBLP DOI BibTeX RDF
16	Lucídio dos Anjos Formiga Cabral, Júlio S. Aude, Nelson Maculan	TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
16	Alireza Kaviani	Using Design Hierarchy to Improve Quality of Results in FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
16	Ernest Jamro, Kazimierz Wiatr	Dynamic Constant Coefficient Convolvers Implemented in FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
16	Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José Manuel Martins Ferreira	On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
16	Théodore Marescaux, T. Andrei Bartic, Diederik Verkest, Serge Vernalde, Rudy Lauwereins	Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
16	Andrzej Krasniewski	Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
16	Jérémie Detrey, Florent de Dinechin	Multipartite Tables in JBits for the Evaluation of Functions on FPGAs.	IPDPS	2002	DBLP DOI BibTeX RDF
16	Anup Kumar Raghavan, Peter Sutton	JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs.	IPDPS	2002	DBLP DOI BibTeX RDF	JBits, FPGA design flow, Partial Bitstream, Xilinx Virtex, Partial Reconfiguration
16	Gerhard Lienhart, Andreas Kugel, Reinhard Männer	Using Floating-Point Arithmetic on FPGAs to Accelerate Scientific N-Body Simulations.	FCCM	2002	DBLP DOI BibTeX RDF