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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2996 occurrences of 1338 keywords
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Results
Found 4838 publication records. Showing 4828 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Kenroy A. Howard, Marian K. Kazimierczuk |
Eddy-current power loss in laminated iron cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 668-671, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Claude Arm, Jean-Marc Masgonty, Christian Piguet |
Double-Latch Clocking Scheme for Low-Power I.P. Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 217-224, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria |
Instruction-level power estimation for embedded VLIW cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, San Diego, California, USA, 2000, pp. 34-38, 2000, ACM, 1-58113-268-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni |
A Family of Self-Repair SRAM Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 214-218, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Memory Self-Repair, Memory BIST, BISR |
18 | Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel |
Zero-Aliasing Space Compression using a Single Periodic Output and its Application to Testing of Embedded Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 382-391, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Dimitrios Kagaris, Spyros Tragoudas |
Embedded cores using built-in mechanisms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 23-26, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | P. K. Jaini, Nur A. Touba |
Observing test response of embedded cores through surrounding logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 119-123, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Michael Gössel, Andrej A. Morosov, Egor S. Sogomonyan |
A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 49-57, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | HyungWon Kim 0001, John P. Hayes |
Delay Fault Testing of Designs with Embedded IP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 160-167, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Lode Nachtergaele, Dennis Moolenaar, Bart Vanhoof, Francky Catthoor, Hugo De Man |
System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 18(2), pp. 89-109, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Wei Zhao, Christos A. Papachristou |
Testing DSP Cores Based on Self-Test Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 166-172, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer |
Arithmetic built-in self-test for DSP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11), pp. 1358-1369, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Ingrid Biehl |
Definition and Existence of Super Complexity Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISAAC ![In: Algorithms and Computation, 5th International Symposium, ISAAC '94, Beijing, P. R. China, August 25-27, 1994, Proceedings, pp. 600-606, 1994, Springer, 3-540-58325-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Uwe Schöning |
Complexity Cores and Hard Problem Instances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGAL International Symposium on Algorithms ![In: Algorithms, International Symposium SIGAL '90, Tokyo, Japan, August 16-18, 1990, Proceedings, pp. 232-240, 1990, Springer, 3-540-52921-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
18 | Ronald V. Book, Ding-Zhu Du |
The existence and density of generalized complexity cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 34(3), pp. 718-730, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
18 | Uwe Schöning |
Complexity Cores and Hard-To-Prove Formulas. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSL ![In: CSL '87, 1st Workshop on Computer Science Logic, Karlsruhe, Germany, October 12-16, 1987, Proceedings, pp. 273-280, 1987, Springer, 3-540-50241-6. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
18 | Pekka Orponen, David A. Russo, Uwe Schöning |
Polynomial Levelability and Maximal Complexity Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 12th Colloquium, Nafplion, Greece, July 15-19, 1985, Proceedings, pp. 435-444, 1985, Springer, 3-540-15650-X. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
17 | M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt |
Accelerating Critical Section Execution with Asymmetric Multicore Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 30(1), pp. 60-70, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
heterogeneous cores, parallel programming, CMP, multicore, locks, critical sections, serialization |
17 | Takeshi Ogasawara |
Scalability limitations when running a Java web server on a chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SYSTOR ![In: Proceedings of of SYSTOR 2010: The 3rd Annual Haifa Experimental Systems Conference, Haifa, Israel, May 24-26, 2010, 2010, ACM, 978-1-60558-908-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance, multi-cores, JVMs, web servers |
17 | Gaurav Dhiman, Vasileios Kontorinis, Dean M. Tullsen, Tajana Rosing, Eric Saxe, Jonathan Chew |
Dynamic workload characterization for power efficient scheduling on CMP systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 437-442, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
power, multi-cores, workload characterization |
17 | Wook-Shin Han, Jinsoo Lee |
Dependency-aware reordering for parallelizing query optimization in multi-core CPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the ACM SIGMOD International Conference on Management of Data, SIGMOD 2009, Providence, Rhode Island, USA, June 29 - July 2, 2009, pp. 45-58, 2009, ACM, 978-1-60558-551-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
query optimization, multi-cores, parallel databases |
17 | Polychronis Xekalakis, Nikolas Ioannou, Marcelo Cintra |
Combining thread level speculation helper threads and runahead execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009, pp. 410-420, 2009, ACM, 978-1-60558-498-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multi-cores, thread-level speculation, helper threads, runahead execution |
17 | Jürgen Rückert, Barbara Paech |
The Guilet Dialog Model and Dialog Core for Graphical User Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TAMODIA/HCSE ![In: Engineering Interactive Systems, Second Conference on Human-Centered Software Engineering, HCSE 2008, and 7th International Workshop on Task Models and Diagrams, TAMODIA 2008, Pisa, Italy, September 25-26, 2008. Proceedings, pp. 197-204, 2008, Springer, 978-3-540-85991-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Dialog cores, Model-based user interfaces, Dialog models, UI engines |
17 | Haohua Zhang, Hai Zhao, Wei Cai, Ming Zhao, Guilan Luo |
Visualization and Cognition of Large-Scale Software Structure Using the k-Core Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IIH-MSP ![In: 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2008), Harbin, China, 15-17 August 2008, Proceedings, pp. 954-957, 2008, IEEE Computer Society, 978-0-7695-3278-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
k-Cores, Visualization, Software metrics, Complex networks, Software structure |
17 | John R. Feehrer, Paul Rotker, Milton Shih, Paul Gingras, Peter Yakutis, Stephen Phillips, John Heath, Sebastian Turullols |
Coherency Hub Design for Multi-Node Victoria Falls Server Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Interconnects ![In: 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 26-28 August 2008, Stanford, CA, USA, pp. 43-50, 2008, IEEE Computer Society, 978-0-7695-3380-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multi-threaded processor cores, multi-node CMT systems, serial interconnects, packet switching, cache coherency |
17 | Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos |
Optimal Selective Huffman Coding for Test-Data Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(8), pp. 1146-1152, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Embedded Testing Techniques, Selective Huffman Coding, Test-Data Compression, IP Cores |
17 | Scott Davidson 0001 |
How do we train today's students to become tomorrow's engineers? ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(4), pp. 408, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
DNA devices, nanomachine cores, CAD, training, engineers, university education |
17 | Shashank Pandit, Duen Horng Chau, Samuel Wang, Christos Faloutsos |
Netprobe: a fast and scalable system for fraud detection in online auction networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WWW ![In: Proceedings of the 16th International Conference on World Wide Web, WWW 2007, Banff, Alberta, Canada, May 8-12, 2007, pp. 201-210, 2007, ACM, 978-1-59593-654-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
bipartite cores, markov random fields, belief propagation, fraud detection |
17 | Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Bernard Lint, Asit Mallick, Koichi Yamada, Hong Wang 0003 |
Sequencer virtualization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 21th Annual International Conference on Supercomputing, ICS 2007, Seattle, Washington, USA, June 17-21, 2007, pp. 148-157, 2007, ACM, 978-1-59593-768-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
virtualization, multi-cores, MIMD |
17 | Reza Moraveji, Hamid Sarbazi-Azad, Maghsoud Abbaspour |
Optimal Placement of Frequently Accessed IPs in Mesh NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings, pp. 126-138, 2007, Springer, 978-3-540-74308-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Latency model, IPs/Cores mapping, System on chip, Network on chip, Mesh, Power model |
17 | Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu |
Searching for Global Test Costs Optimization in Core-Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(4), pp. 357-373, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
design space exploration, design for test, SOC testing, embedded cores testing |
17 | Chris Rowen, Steve Leibson |
Flexible architectures for engineering successful SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 692-697, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
processor cores, MPSOC, RISC, RTL, SOC |
17 | Frank Vahid, Susan Cotterell |
Tuning of Loop Cache Architectures to Programs in Embedded System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 8-13, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
customized architectures, embedded systems, low power, synthesis, memory hierarchy, cores, low energy, tuning, instruction fetching, architecture tuning, loop cache, filter cache |
17 | Frank Vahid, Rilesh Patel, Greg Stitt |
Propagating constants past software to hardware peripherals in fixed-application embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 29(5), pp. 25-30, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
embedded systems, low power, synthesis, system-on-a-chip, intellectual property, platforms, cores, tuning, constant propagation |
17 | Prasanna Sundararajan, Steve Guccione |
Run-Time defect tolerance using JBits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 193-198, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Java, FPGA, cores, defect tolerance, run-time reconfiguration |
17 | Frank Vahid, Ann Gordon-Ross |
A self-optimizing embedded microprocessor using a loop table for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001, pp. 219-224, 2001, ACM, 1-58113-371-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
parameterized architectures, self-optimizing architecture, embedded systems, low-power, system-on-a-chip, platforms, cores, tuning |
17 | Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian |
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 179-184, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
built-in self-test, embedded cores, EDA tools |
17 | Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky |
A first-step towards an architecture tuning methodology for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2000 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2000, San Jose, California, USA, November 7-18, 2000, pp. 187-192, 2000, ACM, 1-58113-338-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
parameterized architectures, embedded systems, low-power, system-on-a-chip, cores, tuning |
17 | Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba |
Static Compaction Techniques to Control Scan Vector Power Dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 35-42, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Static Compaction, Test Vector Compaction, Heat Minimization, Low Power, Built-In Self-Test, Design-for-Testability, Integrated Circuits, switching activity, Scan Chains, Peak power, Embedded Cores, Digital Testing |
17 | Frank Vahid, Tony Givargis |
The case for a configure-and-execute paradigm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Seventh International Workshop on Hardware/Software Codesign, CODES 1999, Rome, Italy, 1999, pp. 59-63, 1999, ACM, 1-58113-132-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
methodology, IP, system-on-a-chip, cores |
17 | Biing-Feng Wang |
Finding a k-Tree Core and a k-Tree Center of a Tree Network in Parallel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 9(2), pp. 186-191, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Trees, cores, centers, tree contraction, the Euler-tour technique |
17 | Rainer Dorsch, Hans-Joachim Wunderlich |
Accumulator based deterministic BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 412-421, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
hardware pattern generator, BIST, embedded cores |
17 | Shan-Chyun Ku, Wei-Kuan Shih, Biing-Feng Wang |
Efficient Parallel Algorithms for Optimally Locating a k-Leaf Tree in a Tree Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 16-19, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Trees, cores, tree contraction, the Euler-tour technique |
17 | Uri Abraham |
On system executions and states. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Intell. ![In: Appl. Intell. 3(1), pp. 17-30, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
Correctness of programs, system execution, cores of executions, global time, semantics of concurrency |
17 | Diana Bautista, Julio Sahuquillo, Houcine Hassan, Salvador Petit, José Duato |
Dynamic task set partitioning based on balancing resource requirements and utilization to reduce power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp. 521-526, 2010, ACM, 978-1-60558-639-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Yi-Hung Wei, Chuan-Yue Yang, Tei-Wei Kuo, Shih-Hao Hung, Yuan-Hua Chu |
Energy-efficient real-time scheduling of multimedia tasks on multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp. 258-262, 2010, ACM, 978-1-60558-639-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multimedia tasks scheduling, H.264, multiprocessor scheduling, energy-efficient scheduling |
17 | Joel C. Adams, Daniel J. Ernst, Thomas Murphy, Ariel Ortiz |
Multicore education: pieces of the parallel puzzle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCSE ![In: Proceedings of the 41st ACM technical symposium on Computer science education, SIGCSE 2010, Milwaukee, Wisconsin, USA, March 10-13, 2010, pp. 194-195, 2010, ACM, 978-1-4503-0006-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
parallel, concurrency, training, programming, curriculum, languages, multi-core, workshops, many-core, faculty |
17 | Chi Ching Chi, Ben H. H. Juurlink, Cor Meenderinck |
Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 24th International Conference on Supercomputing, 2010, Tsukuba, Ibaraki, Japan, June 2-4, 2010, pp. 105-114, 2010, ACM, 978-1-4503-0018-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
parallel, video, programming, H.264, decoding, cell |
17 | Todd Gamblin, Bronis R. de Supinski, Martin Schulz 0001, Robert J. Fowler, Daniel A. Reed |
Clustering performance data efficiently at massive scales. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 24th International Conference on Supercomputing, 2010, Tsukuba, Ibaraki, Japan, June 2-4, 2010, pp. 243-252, 2010, ACM, 978-1-4503-0018-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su |
A hyperscalar multi-core architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 77-78, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
cmps, dynamic multi-core chips, reconfigurable multi-core architectures, chip multiprocessors |
17 | Sunpyo Hong, Hyesoon Kim |
An integrated GPU power and performance model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 280-289, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
GPU architecture, performance, energy, analytical model, CUDA, power estimation |
17 | Vijay Anand Korthikanti, Gul Agha |
Towards optimizing energy costs of algorithms for shared memory architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2010: Proceedings of the 22nd Annual ACM Symposium on Parallelism in Algorithms and Architectures, Thira, Santorini, Greece, June 13-15, 2010, pp. 157-165, 2010, ACM, 978-1-4503-0079-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance, parallel algorithms, energy, shared memory architectures |
17 | Dong Hyuk Woo, Hsien-Hsin S. Lee |
COMPASS: a programmable data prefetcher using idle GPU shaders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010, pp. 297-310, 2010, ACM, 978-1-60558-839-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
compute shader, GPU, prefetch |
17 | Chenjie Yu, Peter Petrov |
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 132-137, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
L2 cache partitioning, off-chip bandwidth reduction |
17 | George L. Yuan, Ali Bakhoda, Tor M. Aamodt |
Complexity effective memory access scheduling for many-core accelerator architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 34-44, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
graphics processors, on-chip interconnection networks, memory controller |
17 | Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos |
A tagless coherence directory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 423-434, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
directory coherence, cache coherence, Bloom filters |
17 | Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt |
Coordinated control of multiple prefetchers in multi-core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 316-326, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
prefetching, multi-core, feedback control, memory systems |
17 | Sangmin Seo, Jaejin Lee, Zehra Sura |
Design and implementation of software-managed caches for multicores with local memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 55-66, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, Yonghyun Hwang, Lochi Yu, Daniel Gajski |
Hardware-dependent software synthesis for many-core embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 304-310, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Young-Su Kwon, Bontae Koo, Nak-Woong Eum |
Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 329-334, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | N. S. L. Phani Kumar, Sanjiv Satoor, Ian Buck |
Fast Parallel Expectation Maximization for Gaussian Mixture Models on GPUs Using CUDA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: 11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009, 25-27 June 2009, Seoul, Korea, pp. 103-109, 2009, IEEE, 978-0-7695-3738-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Michael Perrone |
Multicore Programming Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2009 Parallel Processing, 15th International Euro-Par Conference, Delft, The Netherlands, August 25-28, 2009. Proceedings, pp. 1-2, 2009, Springer, 978-3-642-03868-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Giovanni Squillero |
Design validation of multithreaded architectures using concurrent threads evolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
simulation based techniques, functional validation |
17 | Pradipta De, Vijay Mann, Umang Mittaly |
Handling OS jitter on multicore multithreaded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-12, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Aamir Shafi, Jawad Manzoor |
Towards efficient shared memory communications in MPJ express. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-7, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Bratin Saha, Xiaocheng Zhou, Hu Chen, Ying Gao, Shoumeng Yan, Mohan Rajagopalan, Jesse Fang, Peinan Zhang, Ronny Ronen, Avi Mendelson |
Programming model for a heterogeneous x86 platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2009, Dublin, Ireland, June 15-21, 2009, pp. 431-440, 2009, ACM, 978-1-60558-392-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
programming model, heterogeneous platforms |
17 | Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin |
Frequency and yield optimization using power gates in power-constrained designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 121-126, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optimization, yield, power gate, frequency |
17 | Ronny Ronen |
Larrabee: a many-core Intel architecture for visual computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009, pp. 225, 2009, ACM, 978-1-60558-413-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
graphics architecture, many-core computing, parrallel processing, processor arechitecture, software rendering |
17 | Jin Sun 0006, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang |
NBTI aware workload balancing in multi-core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 833-838, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Simon D. Hammond, Gihan R. Mudalige, J. A. Smith, Stephen A. Jarvis, J. A. Herdman, A. Vadgama |
WARPP: a toolkit for simulating high-performance parallel scientific codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SimuTools ![In: Proceedings of the 2nd International Conference on Simulation Tools and Techniques for Communications, Networks and Systems, SimuTools 2009, Rome, Italy, March 2-6, 2009, pp. 19, 2009, ICST/ACM, 978-963-9799-45-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
application performance modelling, simulation, performance modelling, high performance computing |
17 | Sai Prashanth Muralidhara, Mahmut T. Kandemir |
Communication Based Proactive Link Power Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, pp. 198-215, 2009, Springer, 978-3-540-92989-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Ghiath Al-Kadi, Andrei Sergeevich Terechko |
A Hardware Task Scheduler for Embedded Video Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, pp. 140-152, 2009, Springer, 978-3-540-92989-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Hardware task scheduler, task dependency patterns, H.264 video compression, embedded video processing |
17 | Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay |
Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 484-495, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
checkpoint-based architecture, hardware speculation, sst, chip multiprocessor, cmp, instruction-level parallelism, processor architecture, memory-level parallelism |
17 | Zhanglei Wang, Krishnendu Chakrabarty |
Test Data Compression Using Selective Encoding of Scan Slices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(11), pp. 1429-1440, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis |
Cost-Efficient SHA Hardware Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(8), pp. 999-1008, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Seng Lin Shee, Andrea Erdos, Sri Parameswaran |
Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 36(1), pp. 140-162, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
design, architecture, multiprocessor, SoC, pipelines, ASIPs, heterogeneous system |
17 | Matteo Monchiero, Ramon Canal, Antonio González 0001 |
Power/Performance/Thermal Design-Space Exploration for Multicore Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 19(5), pp. 666-681, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
simulation of, Modeling, evaluation, Measurement, Parallel Architectures, Shared memory, Energy-aware systems, multiple-processor systems |
17 | Euiseong Seo, Jinkyu Jeong, Seon-Yeong Park, Joonwon Lee |
Energy Efficient Scheduling of Real-Time Tasks on Multicore Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 19(11), pp. 1540-1552, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Georg Gottlob, Alan Nash |
Efficient core computation in data exchange. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 55(2), pp. 9:1-9:49, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
complexity, data integration, constraints, dependencies, data exchange, core, conjunctive queries, query evaluation, tractability, Chase, universal solutions |
17 | Ozgur Sinanoglu |
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(4), pp. 335-351, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Test power reduction, Scan power reduction, Serial transformations, Scan chain modification, Design for testability, Core-based testing |
17 | Taeho Kgil, Ali G. Saidi, Nathan L. Binkert, Steven K. Reinhardt, Krisztián Flautner, Trevor N. Mudge |
PicoServer: Using 3D stacking technology to build energy efficient servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(4), pp. 16:1-16:34, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
3D stacking technology, Tier-1/2/3 server, Low power, chip multiprocessor, full-system simulation |
17 | Rogelio Serrano, Juan J. Tapia, Oscar Montiel, Roberto Sepúlveda, Patricia Melin |
High Performance Parallel Programming of a GA Using Multi-core Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Soft Computing for Hybrid Intelligent Systems ![In: Soft Computing for Hybrid Intelligent Systems, pp. 307-314, 2008, Springer, 978-3-540-70811-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Barbara M. Chapman |
Managing Multicore with OpenMP (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
PVM/MPI ![In: Recent Advances in Parallel Virtual Machine and Message Passing Interface, 15th European PVM/MPI Users' Group Meeting, Dublin, Ireland, September 7-10, 2008. Proceedings, pp. 3-4, 2008, Springer, 978-3-540-87474-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Olivier Certner, Zheng Li, Pierre Palatin, Olivier Temam, Frederic Arzel, Nathalie Drach |
A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 740-745, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Magnus Själander, Andrei Sergeevich Terechko, Marc Duranton |
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 149-157, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Joe Rattner |
Intel's Tera-scale Computing Project: The first five years, the next five years. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 1, 2008, IEEE Computer Society, 978-1-4244-2070-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Mark D. Hill |
Amdahl's Law in the multicore era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 187, 2008, IEEE Computer Society, 978-1-4244-2070-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang |
Run-time power gating of on-chip routers using look-ahead routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 55-60, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Marina Biberstein, Yuval Harel, Andre Heilper |
Clock Synchronization in Cell BE Traces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2008 - Parallel Processing, 14th International Euro-Par Conference, Las Palmas de Gran Canaria, Spain, August 26-29, 2008, Proceedings, pp. 3-12, 2008, Springer, 978-3-540-85450-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Hongbo Zeng, Jun Wang, Ge Zhang 0007, Weiwu Hu |
An interconnect-aware power efficient cache coherence protocol for CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-11, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Sevin Fide, Stephen F. Jenks |
Architecture optimizations for synchronization and communication on chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | J. P. Grossman, Cliff Young, Joseph A. Bank, Kenneth M. Mackenzie, Doug Ierardi, John K. Salmon, Ron O. Dror, David E. Shaw |
Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 125-130, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Anton, simulation, embedded software, special-purpose hardware |
17 | Daniel D. Gajski, Samar Abdi, Ines Viskic |
Model Based Synthesis of Embedded Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEUS ![In: Software Technologies for Embedded and Ubiquitous Systems, 6th IFIP WG 10.2 International Workshop, SEUS 2008, Anacarpi, Capri Island, Italy, October 1-3, 2008, Proceedings, pp. 21-33, 2008, Springer, 978-3-540-87784-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | William Lloyd Bircher, Lizy K. John |
Analysis of dynamic power management on multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008, pp. 327-338, 2008, ACM, 978-1-60558-158-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ACPI, performance, operating system, power management, multi-core |
17 | Ravishankar Rao, Sarma B. K. Vrudhula |
Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 537-542, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Satyanarayana Nekkalapu, Haitham Akkary, Komal Jothi, Renjith Retnamma, Xiaoyu Song |
A simple latency tolerant processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 384-389, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Wangyuan Zhang, Tao Li 0006 |
Managing multi-core soft-error reliability through utility-driven cross domain optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 132-137, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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17 | Kai Zheng 0005, Yongxin Zhu 0001, Jun Xu |
Evaluation of Partitioning Methods for Stream Applications on a Heterogeneous Multi-core Processor Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC (2) ![In: 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), Shanghai, China, December 17-20, 2008, Volume II: Workshops, pp. 486-491, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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17 | Lin-Wang Wang, Byounghak Lee, Hongzhang Shan, Zhengji Zhao, Juan C. Meza, Erich Strohmaier, David H. Bailey |
Linearly scaling 3D fragment method for large-scale electronic structure calculations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Computing, SC 2008, November 15-21, 2008, Austin, Texas, USA, pp. 65, 2008, IEEE/ACM, 978-1-4244-2835-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Filip Blagojevic, Xizhou Feng, Kirk W. Cameron, Dimitrios S. Nikolopoulos |
Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 38-52, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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