Search results for "Cores"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Kenroy A. Howard, Marian K. Kazimierczuk	Eddy-current power loss in laminated iron cores.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
18	Claude Arm, Jean-Marc Masgonty, Christian Piguet	Double-Latch Clocking Scheme for Low-Power I.P. Cores.	PATMOS	2000	DBLP DOI BibTeX RDF
18	Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria	Instruction-level power estimation for embedded VLIW cores.	CODES	2000	DBLP DOI BibTeX RDF
18	Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni	A Family of Self-Repair SRAM Cores.	IOLTW	2000	DBLP DOI BibTeX RDF	Memory Self-Repair, Memory BIST, BISR
18	Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel	Zero-Aliasing Space Compression using a Single Periodic Output and its Application to Testing of Embedded Cores.	VLSI Design	2000	DBLP DOI BibTeX RDF
18	Dimitrios Kagaris, Spyros Tragoudas	Embedded cores using built-in mechanisms.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
18	P. K. Jaini, Nur A. Touba	Observing test response of embedded cores through surrounding logic.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
18	Michael Gössel, Andrej A. Morosov, Egor S. Sogomonyan	A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces.	VTS	1999	DBLP DOI BibTeX RDF
18	HyungWon Kim 0001, John P. Hayes	Delay Fault Testing of Designs with Embedded IP Cores.	VTS	1999	DBLP DOI BibTeX RDF
18	Lode Nachtergaele, Dennis Moolenaar, Bart Vanhoof, Francky Catthoor, Hugo De Man	System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
18	Wei Zhao, Christos A. Papachristou	Testing DSP Cores Based on Self-Test Programs.	DATE	1998	DBLP DOI BibTeX RDF
18	Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer	Arithmetic built-in self-test for DSP cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
18	Ingrid Biehl	Definition and Existence of Super Complexity Cores.	ISAAC	1994	DBLP DOI BibTeX RDF
18	Uwe Schöning	Complexity Cores and Hard Problem Instances.	SIGAL International Symposium on Algorithms	1990	DBLP DOI BibTeX RDF
18	Ronald V. Book, Ding-Zhu Du	The existence and density of generalized complexity cores.	J. ACM	1987	DBLP DOI BibTeX RDF
18	Uwe Schöning	Complexity Cores and Hard-To-Prove Formulas.	CSL	1987	DBLP DOI BibTeX RDF
18	Pekka Orponen, David A. Russo, Uwe Schöning	Polynomial Levelability and Maximal Complexity Cores.	ICALP	1985	DBLP DOI BibTeX RDF
17	M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt	Accelerating Critical Section Execution with Asymmetric Multicore Architectures.	IEEE Micro	2010	DBLP DOI BibTeX RDF	heterogeneous cores, parallel programming, CMP, multicore, locks, critical sections, serialization
17	Takeshi Ogasawara	Scalability limitations when running a Java web server on a chip multiprocessor.	SYSTOR	2010	DBLP DOI BibTeX RDF	performance, multi-cores, JVMs, web servers
17	Gaurav Dhiman, Vasileios Kontorinis, Dean M. Tullsen, Tajana Rosing, Eric Saxe, Jonathan Chew	Dynamic workload characterization for power efficient scheduling on CMP systems.	ISLPED	2010	DBLP DOI BibTeX RDF	power, multi-cores, workload characterization
17	Wook-Shin Han, Jinsoo Lee	Dependency-aware reordering for parallelizing query optimization in multi-core CPUs.	SIGMOD Conference	2009	DBLP DOI BibTeX RDF	query optimization, multi-cores, parallel databases
17	Polychronis Xekalakis, Nikolas Ioannou, Marcelo Cintra	Combining thread level speculation helper threads and runahead execution.	ICS	2009	DBLP DOI BibTeX RDF	multi-cores, thread-level speculation, helper threads, runahead execution
17	Jürgen Rückert, Barbara Paech	The Guilet Dialog Model and Dialog Core for Graphical User Interfaces.	TAMODIA/HCSE	2008	DBLP DOI BibTeX RDF	Dialog cores, Model-based user interfaces, Dialog models, UI engines
17	Haohua Zhang, Hai Zhao, Wei Cai, Ming Zhao, Guilan Luo	Visualization and Cognition of Large-Scale Software Structure Using the k-Core Analysis.	IIH-MSP	2008	DBLP DOI BibTeX RDF	k-Cores, Visualization, Software metrics, Complex networks, Software structure
17	John R. Feehrer, Paul Rotker, Milton Shih, Paul Gingras, Peter Yakutis, Stephen Phillips, John Heath, Sebastian Turullols	Coherency Hub Design for Multi-Node Victoria Falls Server Systems.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	multi-threaded processor cores, multi-node CMT systems, serial interconnects, packet switching, cache coherency
17	Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos	Optimal Selective Huffman Coding for Test-Data Compression.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Embedded Testing Techniques, Selective Huffman Coding, Test-Data Compression, IP Cores
17	Scott Davidson 0001	How do we train today's students to become tomorrow's engineers?	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	DNA devices, nanomachine cores, CAD, training, engineers, university education
17	Shashank Pandit, Duen Horng Chau, Samuel Wang, Christos Faloutsos	Netprobe: a fast and scalable system for fraud detection in online auction networks.	WWW	2007	DBLP DOI BibTeX RDF	bipartite cores, markov random fields, belief propagation, fraud detection
17	Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Bernard Lint, Asit Mallick, Koichi Yamada, Hong Wang 0003	Sequencer virtualization.	ICS	2007	DBLP DOI BibTeX RDF	virtualization, multi-cores, MIMD
17	Reza Moraveji, Hamid Sarbazi-Azad, Maghsoud Abbaspour	Optimal Placement of Frequently Accessed IPs in Mesh NoCs.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	Latency model, IPs/Cores mapping, System on chip, Network on chip, Mesh, Power model
17	Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu	Searching for Global Test Costs Optimization in Core-Based Systems.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	design space exploration, design for test, SOC testing, embedded cores testing
17	Chris Rowen, Steve Leibson	Flexible architectures for engineering successful SOCs.	DAC	2004	DBLP DOI BibTeX RDF	processor cores, MPSOC, RISC, RTL, SOC
17	Frank Vahid, Susan Cotterell	Tuning of Loop Cache Architectures to Programs in Embedded System Design.	ISSS	2002	DBLP DOI BibTeX RDF	customized architectures, embedded systems, low power, synthesis, memory hierarchy, cores, low energy, tuning, instruction fetching, architecture tuning, loop cache, filter cache
17	Frank Vahid, Rilesh Patel, Greg Stitt	Propagating constants past software to hardware peripherals in fixed-application embedded systems.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF	embedded systems, low power, synthesis, system-on-a-chip, intellectual property, platforms, cores, tuning, constant propagation
17	Prasanna Sundararajan, Steve Guccione	Run-Time defect tolerance using JBits.	FPGA	2001	DBLP DOI BibTeX RDF	Java, FPGA, cores, defect tolerance, run-time reconfiguration
17	Frank Vahid, Ann Gordon-Ross	A self-optimizing embedded microprocessor using a loop table for low power.	ISLPED	2001	DBLP DOI BibTeX RDF	parameterized architectures, self-optimizing architecture, embedded systems, low-power, system-on-a-chip, platforms, cores, tuning
17	Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian	A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	built-in self-test, embedded cores, EDA tools
17	Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky	A first-step towards an architecture tuning methodology for low power.	CASES	2000	DBLP DOI BibTeX RDF	parameterized architectures, embedded systems, low-power, system-on-a-chip, cores, tuning
17	Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba	Static Compaction Techniques to Control Scan Vector Power Dissipation.	VTS	2000	DBLP DOI BibTeX RDF	Static Compaction, Test Vector Compaction, Heat Minimization, Low Power, Built-In Self-Test, Design-for-Testability, Integrated Circuits, switching activity, Scan Chains, Peak power, Embedded Cores, Digital Testing
17	Frank Vahid, Tony Givargis	The case for a configure-and-execute paradigm.	CODES	1999	DBLP DOI BibTeX RDF	methodology, IP, system-on-a-chip, cores
17	Biing-Feng Wang	Finding a k-Tree Core and a k-Tree Center of a Tree Network in Parallel.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	Trees, cores, centers, tree contraction, the Euler-tour technique
17	Rainer Dorsch, Hans-Joachim Wunderlich	Accumulator based deterministic BIST.	ITC	1998	DBLP DOI BibTeX RDF	hardware pattern generator, BIST, embedded cores
17	Shan-Chyun Ku, Wei-Kuan Shih, Biing-Feng Wang	Efficient Parallel Algorithms for Optimally Locating a k-Leaf Tree in a Tree Network.	ICPP	1997	DBLP DOI BibTeX RDF	Trees, cores, tree contraction, the Euler-tour technique
17	Uri Abraham	On system executions and states.	Appl. Intell.	1993	DBLP DOI BibTeX RDF	Correctness of programs, system execution, cores of executions, global time, semantics of concurrency
17	Diana Bautista, Julio Sahuquillo, Houcine Hassan, Salvador Petit, José Duato	Dynamic task set partitioning based on balancing resource requirements and utilization to reduce power consumption.	SAC	2010	DBLP DOI BibTeX RDF
17	Yi-Hung Wei, Chuan-Yue Yang, Tei-Wei Kuo, Shih-Hao Hung, Yuan-Hua Chu	Energy-efficient real-time scheduling of multimedia tasks on multi-core processors.	SAC	2010	DBLP DOI BibTeX RDF	multimedia tasks scheduling, H.264, multiprocessor scheduling, energy-efficient scheduling
17	Joel C. Adams, Daniel J. Ernst, Thomas Murphy, Ariel Ortiz	Multicore education: pieces of the parallel puzzle.	SIGCSE	2010	DBLP DOI BibTeX RDF	parallel, concurrency, training, programming, curriculum, languages, multi-core, workshops, many-core, faculty
17	Chi Ching Chi, Ben H. H. Juurlink, Cor Meenderinck	Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine.	ICS	2010	DBLP DOI BibTeX RDF	parallel, video, programming, H.264, decoding, cell
17	Todd Gamblin, Bronis R. de Supinski, Martin Schulz 0001, Robert J. Fowler, Daniel A. Reed	Clustering performance data efficiently at massive scales.	ICS	2010	DBLP DOI BibTeX RDF
17	Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su	A hyperscalar multi-core architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cmps, dynamic multi-core chips, reconfigurable multi-core architectures, chip multiprocessors
17	Sunpyo Hong, Hyesoon Kim	An integrated GPU power and performance model.	ISCA	2010	DBLP DOI BibTeX RDF	GPU architecture, performance, energy, analytical model, CUDA, power estimation
17	Vijay Anand Korthikanti, Gul Agha	Towards optimizing energy costs of algorithms for shared memory architectures.	SPAA	2010	DBLP DOI BibTeX RDF	performance, parallel algorithms, energy, shared memory architectures
17	Dong Hyuk Woo, Hsien-Hsin S. Lee	COMPASS: a programmable data prefetcher using idle GPU shaders.	ASPLOS	2010	DBLP DOI BibTeX RDF	compute shader, GPU, prefetch
17	Chenjie Yu, Peter Petrov	Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms.	DAC	2010	DBLP DOI BibTeX RDF	L2 cache partitioning, off-chip bandwidth reduction
17	George L. Yuan, Ali Bakhoda, Tor M. Aamodt	Complexity effective memory access scheduling for many-core accelerator architectures.	MICRO	2009	DBLP DOI BibTeX RDF	graphics processors, on-chip interconnection networks, memory controller
17	Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos	A tagless coherence directory.	MICRO	2009	DBLP DOI BibTeX RDF	directory coherence, cache coherence, Bloom filters
17	Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt	Coordinated control of multiple prefetchers in multi-core systems.	MICRO	2009	DBLP DOI BibTeX RDF	prefetching, multi-core, feedback control, memory systems
17	Sangmin Seo, Jaejin Lee, Zehra Sura	Design and implementation of software-managed caches for multicores with local memory.	HPCA	2009	DBLP DOI BibTeX RDF
17	Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, Yonghyun Hwang, Lochi Yu, Daniel Gajski	Hardware-dependent software synthesis for many-core embedded systems.	ASP-DAC	2009	DBLP DOI BibTeX RDF
17	Young-Su Kwon, Bontae Koo, Nak-Woong Eum	Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor.	ASP-DAC	2009	DBLP DOI BibTeX RDF
17	N. S. L. Phani Kumar, Sanjiv Satoor, Ian Buck	Fast Parallel Expectation Maximization for Gaussian Mixture Models on GPUs Using CUDA.	HPCC	2009	DBLP DOI BibTeX RDF
17	Michael Perrone	Multicore Programming Challenges.	Euro-Par	2009	DBLP DOI BibTeX RDF
17	Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Giovanni Squillero	Design validation of multithreaded architectures using concurrent threads evolution.	SBCCI	2009	DBLP DOI BibTeX RDF	simulation based techniques, functional validation
17	Pradipta De, Vijay Mann, Umang Mittaly	Handling OS jitter on multicore multithreaded systems.	IPDPS	2009	DBLP DOI BibTeX RDF
17	Aamir Shafi, Jawad Manzoor	Towards efficient shared memory communications in MPJ express.	IPDPS	2009	DBLP DOI BibTeX RDF
17	Bratin Saha, Xiaocheng Zhou, Hu Chen, Ying Gao, Shoumeng Yan, Mohan Rajagopalan, Jesse Fang, Peinan Zhang, Ronny Ronen, Avi Mendelson	Programming model for a heterogeneous x86 platform.	PLDI	2009	DBLP DOI BibTeX RDF	programming model, heterogeneous platforms
17	Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin	Frequency and yield optimization using power gates in power-constrained designs.	ISLPED	2009	DBLP DOI BibTeX RDF	optimization, yield, power gate, frequency
17	Ronny Ronen	Larrabee: a many-core Intel architecture for visual computing.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	graphics architecture, many-core computing, parrallel processing, processor arechitecture, software rendering
17	Jin Sun 0006, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang	NBTI aware workload balancing in multi-core systems.	ISQED	2009	DBLP DOI BibTeX RDF
17	Simon D. Hammond, Gihan R. Mudalige, J. A. Smith, Stephen A. Jarvis, J. A. Herdman, A. Vadgama	WARPP: a toolkit for simulating high-performance parallel scientific codes.	SimuTools	2009	DBLP DOI BibTeX RDF	application performance modelling, simulation, performance modelling, high performance computing
17	Sai Prashanth Muralidhara, Mahmut T. Kandemir	Communication Based Proactive Link Power Management.	HiPEAC	2009	DBLP DOI BibTeX RDF
17	Ghiath Al-Kadi, Andrei Sergeevich Terechko	A Hardware Task Scheduler for Embedded Video Processing.	HiPEAC	2009	DBLP DOI BibTeX RDF	Hardware task scheduler, task dependency patterns, H.264 video compression, embedded video processing
17	Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay	Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor.	ISCA	2009	DBLP DOI BibTeX RDF	checkpoint-based architecture, hardware speculation, sst, chip multiprocessor, cmp, instruction-level parallelism, processor architecture, memory-level parallelism
17	Zhanglei Wang, Krishnendu Chakrabarty	Test Data Compression Using Selective Encoding of Scan Slices.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
17	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	Cost-Efficient SHA Hardware Accelerators.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
17	Seng Lin Shee, Andrea Erdos, Sri Parameswaran	Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	design, architecture, multiprocessor, SoC, pipelines, ASIPs, heterogeneous system
17	Matteo Monchiero, Ramon Canal, Antonio González 0001	Power/Performance/Thermal Design-Space Exploration for Multicore Architectures.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF	simulation of, Modeling, evaluation, Measurement, Parallel Architectures, Shared memory, Energy-aware systems, multiple-processor systems
17	Euiseong Seo, Jinkyu Jeong, Seon-Yeong Park, Joonwon Lee	Energy Efficient Scheduling of Real-Time Tasks on Multicore Processors.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF
17	Georg Gottlob, Alan Nash	Efficient core computation in data exchange.	J. ACM	2008	DBLP DOI BibTeX RDF	complexity, data integration, constraints, dependencies, data exchange, core, conjunctive queries, query evaluation, tractability, Chase, universal solutions
17	Ozgur Sinanoglu	Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Test power reduction, Scan power reduction, Serial transformations, Scan chain modification, Design for testability, Core-based testing
17	Taeho Kgil, Ali G. Saidi, Nathan L. Binkert, Steven K. Reinhardt, Krisztián Flautner, Trevor N. Mudge	PicoServer: Using 3D stacking technology to build energy efficient servers.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	3D stacking technology, Tier-1/2/3 server, Low power, chip multiprocessor, full-system simulation
17	Rogelio Serrano, Juan J. Tapia, Oscar Montiel, Roberto Sepúlveda, Patricia Melin	High Performance Parallel Programming of a GA Using Multi-core Technology.	Soft Computing for Hybrid Intelligent Systems	2008	DBLP DOI BibTeX RDF
17	Barbara M. Chapman	Managing Multicore with OpenMP (Extended Abstract).	PVM/MPI	2008	DBLP DOI BibTeX RDF
17	Olivier Certner, Zheng Li, Pierre Palatin, Olivier Temam, Frederic Arzel, Nathalie Drach	A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs.	DATE	2008	DBLP DOI BibTeX RDF
17	Magnus Själander, Andrei Sergeevich Terechko, Marc Duranton	A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures.	DSD	2008	DBLP DOI BibTeX RDF
17	Joe Rattner	Intel's Tera-scale Computing Project: The first five years, the next five years.	HPCA	2008	DBLP DOI BibTeX RDF
17	Mark D. Hill	Amdahl's Law in the multicore era.	HPCA	2008	DBLP DOI BibTeX RDF
17	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang	Run-time power gating of on-chip routers using look-ahead routing.	ASP-DAC	2008	DBLP DOI BibTeX RDF
17	Marina Biberstein, Yuval Harel, Andre Heilper	Clock Synchronization in Cell BE Traces.	Euro-Par	2008	DBLP DOI BibTeX RDF
17	Hongbo Zeng, Jun Wang, Ge Zhang 0007, Weiwu Hu	An interconnect-aware power efficient cache coherence protocol for CMPs.	IPDPS	2008	DBLP DOI BibTeX RDF
17	Sevin Fide, Stephen F. Jenks	Architecture optimizations for synchronization and communication on chip multiprocessors.	IPDPS	2008	DBLP DOI BibTeX RDF
17	J. P. Grossman, Cliff Young, Joseph A. Bank, Kenneth M. Mackenzie, Doug Ierardi, John K. Salmon, Ron O. Dror, David E. Shaw	Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	Anton, simulation, embedded software, special-purpose hardware
17	Daniel D. Gajski, Samar Abdi, Ines Viskic	Model Based Synthesis of Embedded Software.	SEUS	2008	DBLP DOI BibTeX RDF
17	William Lloyd Bircher, Lizy K. John	Analysis of dynamic power management on multi-core processors.	ICS	2008	DBLP DOI BibTeX RDF	ACPI, performance, operating system, power management, multi-core
17	Ravishankar Rao, Sarma B. K. Vrudhula	Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors.	ICCAD	2008	DBLP DOI BibTeX RDF
17	Satyanarayana Nekkalapu, Haitham Akkary, Komal Jothi, Renjith Retnamma, Xiaoyu Song	A simple latency tolerant processor.	ICCD	2008	DBLP DOI BibTeX RDF
17	Wangyuan Zhang, Tao Li 0006	Managing multi-core soft-error reliability through utility-driven cross domain optimization.	ASAP	2008	DBLP DOI BibTeX RDF
17	Kai Zheng 0005, Yongxin Zhu 0001, Jun Xu	Evaluation of Partitioning Methods for Stream Applications on a Heterogeneous Multi-core Processor Simulator.	EUC (2)	2008	DBLP DOI BibTeX RDF
17	Lin-Wang Wang, Byounghak Lee, Hongzhang Shan, Zhengji Zhao, Juan C. Meza, Erich Strohmaier, David H. Bailey	Linearly scaling 3D fragment method for large-scale electronic structure calculations.	SC	2008	DBLP DOI BibTeX RDF
17	Filip Blagojevic, Xizhou Feng, Kirk W. Cameron, Dimitrios S. Nikolopoulos	Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE.	HiPEAC	2008	DBLP DOI BibTeX RDF