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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1797 occurrences of 735 keywords
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Results
Found 1918 publication records. Showing 1918 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Michael J. Lyons 0003, David M. Brooks |
The design of a bloom filter hardware accelerator for ultra low power systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 371-376, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
wireless sensor network, hardware accelerator, bloom filter |
1 | Sonali Chouhan, M. Balakrishnan, Ranjan Bose |
An experimental validation of system level design space exploration methodology for energy efficient sensor nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 355-358, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
computation-radio energy trade-off, wireless sensor networks, error correcting codes, low energy, energy measurement |
1 | Abhishek A. Sinkar, Nam Sung Kim |
Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 189-194, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
adaptive voltage positioning, multicore processor |
1 | Steven C. Jocke, Jonathan F. Bolus, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun |
A 2.6 µW sub-threshold mixed-signal ECG SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 117-118, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
sub-threshold SoC, sub-threshold operation, system on chip, electrocardiogram |
1 | Yankin Tanurhan |
Dealing with disaggregation in ever-changing world of semiconductors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 363-364, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
data center design, processor management, virtualization, storage, memory systems, energy efficient design, cooling |
1 | Jianwei Dai, Lei Wang 0003 |
Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 159-164, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low-power technique, way-tag array, cache |
1 | Zainul Charbiwala, Younghun Kim, Sadaf Zahedi, Jonathan Friedman, Mani B. Srivastava |
Energy efficient sampling for event detection in wireless sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 419-424, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
wireless sensor networks, detection, compressive sensing |
1 | Xiaoming Chen 0003, Yu Wang 0002, Yu Cao 0001, Yuchun Ma, Huazhong Yang |
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 39-44, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd |
1 | Jiana Lou, Xiaobo Wu |
Design of multi-mode 4-switch buck-boost controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 311-314, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
buck-boost controller, seamless transition, valley current mode |
1 | Joo-Young Kim 0001, Seungjin Lee 0001, Jinwook Oh, Minsu Kim, Hoi-Jun Yoo |
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 365-370, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
energy efficient object recognition, multimedia processor, workload-aware dynamic power management |
1 | David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat |
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 3-8, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
short-channel effects, subthreshold logic, variability, cmos digital integrated circuits, ultra-low power, gate leakage |
1 | Veera Papirla, Aarul Jain, Chaitali Chakrabarti |
Low power robust signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 303-306, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
algorithmic noise tolerance, redundant binary arithmetic, soft DSP |
1 | Wei Xu 0021, Jibang Liu, Tong Zhang 0002 |
Data manipulation techniques to reduce phase change memory write energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 237-242, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power, phase change memory |
1 | Jongmin Lee 0002, Soontae Kim |
An energy-delay efficient 2-level data cache architecture for embedded system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 343-346, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
2-level data cache, early cache hit predictor, one-way write |
1 | Noriko Takagi, Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura |
Cooperative shared resource access control for low-power chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 177-182, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power, chip multiprocessors, cache partitioning, dvfs, resource conflict |
1 | Raid Zuhair Ayoub, Tajana Simunic Rosing |
Predict and act: dynamic thermal management for multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 99-104, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
temperature prediction, characterization, thermal management |
1 | Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
Design and analysis of ultra-thin-body SOI based subthreshold SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 9-14, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
poisson's equation, subthreshold SRAM, ultra-thin-body, soi, static noise margin |
1 | Percy V. Gilbert |
Advances in process technology & IBM collaborative ecosystem for leadership power performance SOC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 1-2, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
keynote |
1 | Amlan Ghosh, Rahul M. Rao, Richard B. Brown |
A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 45-50, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fine-grain body-biasing, process variation compensation, slewrate |
1 | Se Hun Kim, Saibal Mukhopadhyay, Wayne H. Wolf |
Experimental analysis of sequence dependence on energy saving for error tolerant image processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 347-350, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
voltage over-scaling, low power, DCT |
1 | P. V. Ratna Kumar, Kaushik Bhattacharyya, Tamal Das, Pradip Mandal |
Improvement of power efficiency in switched capacitor DC-DC converter by shoot-through current elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 81-86, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
shoot-through current, switched capacitor converter, time interleaving |
1 | Jörg Henkel, Ali Keshavarzi, Naehyuck Chang, Tahir Ghani (eds.) |
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009 ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![ACM, 978-1-60558-684-7 The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
1 | Dominic Maurath, Charalambos M. Andreou, Yiannos Manoli |
A novel 0.5 V 15 µW 1.3 MHz temperature-compensated analog PWM-controller for switch-mode converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 323-326, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
PWM modulator, voltage reference, subthreshold operation |
1 | Hui Zeng, Matt T. Yourst, Kanad Ghose |
An energy-efficient checkpointing mechanism for out of order commit processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 183-188, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
checkpoint, microprocessor |
1 | Sushu Zhang, Karam S. Chatha, Goran Konjevod |
Near optimal battery-aware energy management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 249-254, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power design, dynamic power management, dynamic voltage/frequency scaling |
1 | Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke |
Enabling ultra low voltage system operation by tolerating on-chip cache failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 307-310, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fault-tolerant cache, low voltage operation, dynamic voltage scaling |
1 | Jungseob Lee, Nam Sung Kim |
Optimizing total power of many-core processors considering voltage scaling limit and process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 201-206, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
voltage and frequency scaling, process variations, parallel applications, many-core processor |
1 | Pedro Chaparro, José González 0002, Qiong Cai, Greg Chrysler |
Dynamic thermal management using thin-film thermoelectric cooling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 111-116, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
thermal control, thin-film thermoelectric cooling, low-power, microarchitecture, dynamic thermal management |
1 | Sudhanshu Khanna, Benton H. Calhoun |
Serial sub-threshold circuits for ultra-low-power systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 27-32, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
bit width, serial systems, leakage, ultra low power, sub-threshold |
1 | Thidapat Chantem, Xiaobo Sharon Hu, Robert P. Dick |
Online work maximization under a peak temperature constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 105-110, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
temperature-constraint optimization, performance, reliability, DVFS |
1 | Satendra Kumar Maurya, Lawrence T. Clark |
Low power fast and dense longest prefix match content addressable memory for IP routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 389-394, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
content addressable memory (CAM), internet protocol (IP) routing, ternary content addressable memory (TCAM), longest prefix match |
1 | Thorlindur Thorolfsson, Nariman Moezzi Madani, Paul D. Franzon |
A low power 3D integrated FFT engine using hypercube memory division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 231-236, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FFT, scaling, 3DIC |
1 | Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu |
Power-management-based Chien search for low power BCH decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 299-302, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
BCH decoder, Chien search, low power, power management |
1 | Mian Dong, Yung-Seok Kevin Choi, Lin Zhong 0001 |
Power-saving color transformation of mobile graphical user interfaces on OLED-based displays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 339-342, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
OLED display, low power, graphic user interface |
1 | Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi |
Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 87-92, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
boost converter, inductor design, SSD, charge pump |
1 | Mackenzie R. Scott, Rajeevan Amirtharajah |
Pulse width modulation for reduced peak power full-swing on-chip interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 213-218, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power interconnect, peak power, pulse width modulation |
1 | Kiyoo Itoh 0001 |
Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 273-274, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet |
1 | Norman P. Jouppi, Yuan Xie 0001 |
Emerging technologies and their impact on system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 427-428, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
new non-volatile memory technology, emerging technology, 3d integration |
1 | Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek A. Sinkar, Nam Sung Kim |
Statistical static timing analysis considering leakage variability in power gated designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 57-62, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
process variations, leakage, power gating, ssta |
1 | Guihai Yan, Yinhe Han 0001, Hui Liu, Xiaoyao Liang, Xiaowei Li 0001 |
MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 395-400, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
efficiency, DVFS, timing adaptability |
1 | Hui Shao, Chi-Ying Tsui, Wing-Hung Ki |
A single inductor dual input dual output DC-DC converter with hybrid supplies for solar energy harvesting applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 69-74, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
PV cells, dual-input-dual-output, single inductor, energy harvesting, DC-DC converter, MPPT |
1 | Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy 0001 |
Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 195-200, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
significance driven computation, variation aware, voltage over-scaling, low power, motion estimation |
1 | Guangyu Sun 0003, Xiaoxia Wu, Yuan Xie 0001 |
Exploration of 3D stacked L2 cache design for high performance and efficient thermal control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 295-298, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
thermal control, performance, 3D, L2 caches |
1 | Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 51-56, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
body bias clustering, performance compensation, layout, manufacturing variability, subthreshold circuits |
1 | Ehsan Pakbaznia, Massoud Pedram |
Minimizing data center cooling and server power costs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 145-150, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
datacenter |
1 | Flavio Carbognani, Luca Henzen |
Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 279-282, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
flipflops, low power design, clock, digital circuits, adiabatic |
1 | Ki Chul Chun, Pulkit Jain, Chris H. Kim |
A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 119-120, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
3T DRAM, gain cell, retention time, cache, static power, embedded DRAM |
1 | Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin |
Frequency and yield optimization using power gates in power-constrained designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 121-126, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optimization, yield, power gate, frequency |
1 | Joseph Nayfach-Battilana, Jose Renau |
SOI, interconnect, package, and mainboard thermal characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 327-330, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SOI modeling, package modeling, thermal modeling, interconnect modeling |
1 | Thomas F. Wenisch |
Thinking outside the box: power management at the system level & beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 151-152, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
idle power, powernap, data center, servers |
1 | Hussain A. Alzaher, Noman Tasadduq |
A CMOS low power current-mode polyphase filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 75-80, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CMOS analog integrated circuits, low power current mode circuit, polyphase filter |
1 | Sherief Reda, Aung Si, R. Iris Bahar |
Reducing the leakage and timing variability of 2D ICcs using 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 283-286, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
3D integrated circuit, timing, variability, leakage |
1 | Kaushik Roy 0001 |
Ultra low voltage CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 425-426, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
adaptive supply scaling, nano-scale cmos system, ultra low voltage design, ultra-dynamic voltage scaling |
1 | Karthik Kumar, Yamini Nimmagadda, Yung-Hsiang Lu |
Ranking servers based on energy savings for computation offloading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 267-272, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ranking servers, energy savings, computation offloading |
1 | Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin |
Dynamic power gating with quality guarantees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 377-382, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
execution units, low power, power management, microarchitecture, power gating |
1 | Vijay Raghunathan |
Green at the micro-scale: towards self-powered embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 431-432, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
energy harvesting embedded system, micro-scale green computing, self-powered system |
1 | Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich |
The opportunity cost of low power design: a case study in circuit tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 133-138, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power design, productivity, circuit tuning |
1 | Hui Zeng, Ju-Young Jung, Kanad Ghose, Dmitry Ponomarev 0001 |
Energy-efficient renaming with register versioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 171-176, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
microprocessor, register renaming |
1 | Ge Chen, Saeid Nooshabadi, Steven G. Duvall |
An optimization strategy for low energy and high performance for the on-chip interconnect signalling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 287-290, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
interconnect signaling, low energy |
1 | Mojy Chian |
Challenges and opportunities in low-power design enablement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 361-362, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
keynote |
1 | Suman Datta |
Low voltage tunnel transistor architecture and its viability for energy efficient logic applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 277-278, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
design, tunnel, transistor |
1 | Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay |
Slew-aware clock tree design for reliable subthreshold circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 15-20, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
slew, clocks, subthreshold |
1 | Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King |
PPT: joint performance/power/thermal management of DRAM memory for multi-core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 93-98, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
page allocation, scheduling, power, temperature, DRAM memory |
1 | Vishwani D. Agrawal |
A tutorial on test power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 237-238, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Karthik Kumar, Yamini Nimmagadda, Yu-Ju Hong, Yung-Hsiang Lu |
Energy conservation by adaptive feature loading for mobile content-based image retrieval. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 153-158, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Karthick Rajamani, Charles Lefurgy, Soraya Ghiasi, Juan Rubio 0001, Heather Hanson, Tom W. Keller |
Power management solutions for computer systems and datacenters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 135-136, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Norman P. Jouppi |
System implications of integrated photonics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 183-184, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi |
A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 45-50, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Takayasu Sakurai |
Next-generation power-aware design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 383-384, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Yu-Shiang Lin, Dennis Sylvester |
Single stage static level shifter design for subthreshold to I/O voltage conversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 197-200, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Hao Xu 0010, Ranga Vemuri, Wen-Ben Jone |
Dynamic virtual ground voltage estimation for power gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 27-32, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Rami A. Abdallah, Naresh R. Shanbhag |
Error-resilient low-power Viterbi decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 111-116, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Behnam Ghavami, Hossein Pedram |
Design of dual threshold voltages asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 185-188, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Mingoo Seok, Dennis Sylvester, David T. Blaauw |
Optimal technology selection for minimizing energy and variability in low voltage applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 9-14, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Arvind Madan, Bharadwaj Amrutur |
Power reduction in on-chip interconnection network by serialization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 201-204, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Youngjin Cho, Younghyun Kim 0001, Yongsoo Joo, Kyungsoo Lee, Naehyuck Chang |
Simultaneous optimization of battery-aware voltage regulator scheduling with dynamic voltage and frequency scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 309-314, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Pulkit Jain, Tony Tae-Hyoung Kim, John Keane 0001, Chris H. Kim |
A multi-story power delivery technique for 3D integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 57-62, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Parthasarathy Ranganathan |
Power management from cores to datacenters: where are we going to get the next ten-fold improvements? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 139-140, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Jaswinder Ahuja |
Towards a green electronic world: a collaborative approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 1-2, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Gu-Yeon Wei, David M. Brooks, Ali Durlov Khan, Xiaoyao Liang |
Instruction-driven clock scheduling with glitch mitigation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 357-362, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Bodhisatya Sarker, Jaswinder Ahuja, Arijit Dutta, Srinath D., Kaip Sridhar, Radhakrishnan Nair, Jayant Lahiri |
Penalty for power reduction -: performance or schedule or yield? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 303-304, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Maziar Goudarzi, Tohru Ishihara |
Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 93-98, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | T. Venkata Kalyan, Madhu Mutyam |
Word-interleaved cache: an energy efficient data cache architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 265-270, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Koustav Bhattacharya, Nagarajan Ranganathan |
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 99-104, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Michael Kadin, Sherief Reda |
Frequency planning for multi-core processors under thermal constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 213-216, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 3-8, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Nathaniel J. Guilar, Erin G. Fong, Travis Kleeburg, Diego R. Yankelevich, Rajeevan Amirtharajah |
Energy harvesting photodiodes with integrated 2D diffractive storage capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 63-68, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Inchoon Yeo, Eun Jung Kim 0001 |
Hybrid dynamic thermal management based on statistical characteristics of multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 321-326, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | José González 0002, Qiong Cai, Pedro Chaparro, Grigorios Magklis, Ryan N. Rakvic, Antonio González 0001 |
Thread fusion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 363-368, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Jing-Hu Li, Yu-nan Fu, Yong-sheng Wang |
A 1-V piecewise curvature-corrected CMOS bandgap reference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 289-294, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Jie Jin, Chi-Ying Tsui |
A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 253-258, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Shaobo Liu, Qinru Qiu, Qing Wu 0002 |
A probabilistic technique for full-chip leakage estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 205-208, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Charbel J. Akl, Magdy A. Bayoumi |
Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 69-74, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Hamed Aminzadeh, Khalil Mafinezhad |
On the power efficiency of cascode compensation over Miller compensation in two-stage operational amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 283-288, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Younghyun Kim 0001, Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Nam Ik Cho |
Extending the lifetime of media recorders constrained by battery and flash memory size. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 159-164, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Depak Balemarthy, Roy Paily |
A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 295-300, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao |
Clock gating for power optimization in ASIC design cycle theory & practice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 307-308, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
A physical level study and optimization of CAM-based checkpointed register alias table. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 233-236, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Sonali Chouhan, M. Balakrishnan, Ranjan Bose |
A framework for energy consumption based design space exploration for wireless sensor nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 329-334, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Eric P. Villasenor, Daeho Seo, Mithuna Thottethodi |
Power-efficient clustering via incomplete bypassing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 369-374, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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