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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 397 occurrences of 269 keywords
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Results
Found 1116 publication records. Showing 1053 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Eli Chiprout, Janusz Rajski, Markus Robinson |
Parallel PLA fault simulation based on Boolean vector operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1988 IEEE International Conference on Computer-Aided Design, ICCAD 1988, Santa Clara, CA, USA, November 7-10, 1988. Digest of Technical Papers, pp. 194-197, 1988, IEEE Computer Society, 0-8186-0869-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
19 | William E. Engeler, Menahem Lowy, John Pedicone, John Bloomer, James Richotte, David Chan |
A high speed static CMOS PLA architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 348-351, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
19 | Jing-Yang Jou |
A testable PLA design with low overhead and ease of test generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 450-453, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
19 | Rainer Amann, Bernhard Eschermann, Utz G. Baitinger |
PLA based finite state machines using Johnson counters as state memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 267-270, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
19 | Markus Robinson, Janusz Rajski |
An Algorithmic Branch and Bound Method for PLA Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1988, Washington, D.C., USA, September 1988, pp. 784-795, 1988, IEEE Computer Society, 0-8186-0870-6. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
19 | Daniele D. Caviglia, Vincenzo Piuri, Mauro Santomauro |
About folded-PLA area and folding evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 5(3-4), pp. 193-215, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
19 | Yue-Sun Kuo, T. C. Hu |
An effective algorithm for optimal PLA column folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 5(3-4), pp. 217-230, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
19 | Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli |
Multiple-Valued Minimization for PLA Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(5), pp. 727-750, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
19 | Andreas Frenzke |
PLA - Flächenreduktion durch Faltung - ein Beitrag zur Optimierung von programmierbaren logischen Anordnungen. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1987 |
RDF |
|
19 | Rainer Amann |
Algorithmische Entwurfsverfahren für kombinierte PLA-ROM-Steuerwerke unter Verwendung von Zählern. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1987 |
RDF |
|
19 | Yue-Sun Kuo, C. Chen |
A Heuristic Algorithm for PLA Block Folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Sci. Eng. ![In: J. Inf. Sci. Eng. 2(1), pp. 43-57, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP BibTeX RDF |
|
19 | Sergio Cesare Brofferio, Michele Taliercio |
PLA implementation of a differential predictive coder for digital television signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 4(4), pp. 331-343, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
19 | Sun Young Hwang, Robert W. Dutton, Tom Blank |
A Best-First Search Algorithm for Optimal PLA Folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(3), pp. 433-442, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
19 | Darrell Makarenko, John Tartar |
A Statistical Analysis of PLA Folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(1), pp. 39-51, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
19 | Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli |
PLATYPUS: A PLA Test Pattern Generation Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(4), pp. 633-644, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
19 | Teruhiko Yamada |
Syndrome-testable design and syndrome computing method for large PLA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 17(4), pp. 17-23, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
19 | Chidchanok Lursinsap |
Methods for Cell Compilation With Constraints (Vlsi, Pla, Routing, Silicon) ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1986 |
RDF |
|
19 | Qingjian Yu, Omar Wing |
Interval-graph-based PLA folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 3(1), pp. 33-48, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
19 | Ming Huei Young, Saburo Muroga |
Minimal covering problem and PLA minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 14(6), pp. 337-364, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
19 | Ming Huei Young, Saburo Muroga |
Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 34(6), pp. 523-541, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
19 | Robert P. Treuer, Hideo Fujiwara, Vinod K. Agarwal |
Implementing a Built-In Self-Test PLA Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 2(2), pp. 37-48, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
19 | Vinod K. Agarwal, Janusz Rajski |
Testing Properties and Applications of Inverter-Free PLA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1985, Philadelphia, PA, USA, November 1985, pp. 500-507, 1985, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP BibTeX RDF |
|
19 | James Jacob, Nripendra N. Biswas |
: A Testable PLA Design with Minimal Hardware and Test Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1985, Philadelphia, PA, USA, November 1985, pp. 583-588, 1985, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP BibTeX RDF |
|
19 | Stanley J. Krolikoski |
The Squeeze Algorithm for Pla Minimization (Logic, Computer-Aided, Circuit Design) ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1985 |
RDF |
|
19 | Bella Bose, Der Jei Lin |
PLA Implementation of k-out-of-n Code TSC Checker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(6), pp. 583-588, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
Code disjoint, k-out-of-n codes, fault detection, self-testing, totally self-checking checkers, fault secure |
19 | Hideo Fujiwara |
A New PLA Design for Universal Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(8), pp. 745-750, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
19 | Tsutomu Sasao |
Input Variable Assignment and Output Phase Optimization of PLA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(10), pp. 879-894, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
complexity of logic circuits, decoder assignment, essential prime implicants, output phase optimization, logic design, programmable logic array, Adder, switching theory |
19 | Javad Khakbaz |
A Testable PLA Design with Low Overhead and High Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(8), pp. 743-745, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
19 | Jack R. Egan, C. L. Liu 0001 |
Bipartite Folding and Partitioning of a PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(3), pp. 191-199, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
19 | Christos A. Papachriston, James M. Reuter |
Microassembly and area reduction techniques for PLA microcode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 17th annual workshop on Microprogramming, MICRO 1984, New Orleans, Louisiana, USA, October 30 - November 2, 1984, pp. 86-94, 1984, ACM/IEEE. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP BibTeX RDF |
|
19 | Helmut Schnelle |
Concurrent Parsing In Programmable Logic Array (PLA-) Nets Problems And Proposals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COLING ![In: 10th International Conference on Computational Linguistics and 22nd Annual Meeting of the Association for Computational Linguistics, Proceedings of COLING '84, July 2-6, 1984, Stanford University, California, USA., pp. 150-153, 1984, ACL. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP BibTeX RDF |
|
19 | J. L. Lewandowski, C. L. Liu 0001 |
A branch and bound algorithm for optimal pla folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 21st Design Automation Conference, DAC '84, Albuquerque, New Mexico, June 25-27, 1984, pp. 426-433, 1984, ACM/IEEE, 0-8186-0542-1. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP BibTeX RDF |
|
19 | Andreas Roth 0003 |
Backtrack-Algorithmen für ausgewählte Probleme beim Entwurf von Schaltsystemen mit programmierbaren logischen Feldern (PLA's). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1984 |
RDF |
|
19 | Mohamed Hmimid |
Assemblage et génération automatique des dispositifs périphériques de PLA complexes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1984 |
RDF |
|
19 | Henry Derantonian |
Génération automatique de partie(s) contrôle(s) de microprocesseurs sous forme de PLA spécialisés. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1984 |
RDF |
|
19 | Wentai Liu, Daniel E. Atkins |
Bounds on the saved area ratio due to PLA folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 20th Design Automation Conference, DAC '83, Miami Beach, Florida, USA, June 27-29, 1983, pp. 538-544, 1983, ACM/IEEE, 0-8186-0026-8. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
19 | Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto |
A new integrated system for PLA testing and verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 20th Design Automation Conference, DAC '83, Miami Beach, Florida, USA, June 27-29, 1983, pp. 57-63, 1983, ACM/IEEE, 0-8186-0026-8. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
19 | Shmuel Wimer, N. Sharfman |
HOPLA-PLA optimization and synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 20th Design Automation Conference, DAC '83, Miami Beach, Florida, USA, June 27-29, 1983, pp. 790-794, 1983, ACM/IEEE, 0-8186-0026-8. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
19 | Jorge Martínez-Carballido, V. Michael Powers |
PRONTO: Quick PLA product reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 20th Design Automation Conference, DAC '83, Miami Beach, Florida, USA, June 27-29, 1983, pp. 545-552, 1983, ACM/IEEE, 0-8186-0026-8. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
19 | M. W. Stebnisky, M. J. McGinnis, Joseph C. Werbickas, Rathin Putatunda, A. Feller |
APSS: An automatic PLA synthesis system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 20th Design Automation Conference, DAC '83, Miami Beach, Florida, USA, June 27-29, 1983, pp. 430-435, 1983, ACM/IEEE, 0-8186-0026-8. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
19 | Gary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
An Algorithm for Optimal PLA Folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1(2), pp. 63-77, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
19 | Werner Grass |
A depth-first branch-and-bound algorithm for optimal PLA folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 19th Design Automation Conference, DAC '82, Las Vegas, Nevada, USA, June 14-16, 1982, pp. 133-140, 1982, ACM/IEEE. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
19 | Jack R. Egan, C. L. Liu 0001 |
Optimal bipartite folding of PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 19th Design Automation Conference, DAC '82, Las Vegas, Nevada, USA, June 14-16, 1982, pp. 141-146, 1982, ACM/IEEE. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
19 | Bill Teel, Doran Wilde |
A logic minimizer for VLSI PLA design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 19th Design Automation Conference, DAC '82, Las Vegas, Nevada, USA, June 14-16, 1982, pp. 156-162, 1982, ACM/IEEE. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
19 | Sungho Kang, William M. van Cleemput |
Automatic PLA synthesis from a DDL-P description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 18th Design Automation Conference, DAC '81, Nashville, Tennessee, USA, June 29 - July 1, 1981, pp. 391-397, 1981, ACM/IEEE. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP BibTeX RDF |
|
19 | Jean-François Paillotin |
Optimization of the PLA area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 18th Design Automation Conference, DAC '81, Nashville, Tennessee, USA, June 29 - July 1, 1981, pp. 406-410, 1981, ACM/IEEE. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP BibTeX RDF |
|
19 | I. Suwa, William J. Kubitz |
A computer-aided-design system for segmented-folded PLA macro-cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 18th Design Automation Conference, DAC '81, Nashville, Tennessee, USA, June 29 - July 1, 1981, pp. 398-405, 1981, ACM/IEEE. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP BibTeX RDF |
|
19 | Martin S. Schmokler |
Design of Large ALUs Using Multiple PLA Macros. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 24(1), pp. 2-14, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
|
19 | Daniel L. Ostapko, Se June Hong |
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(9), pp. 617-627, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
|
19 | Samuel H. Fuller, G. A. Mathew |
Implementing microprogram storage with PLA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 5(2), pp. 6-11, 1976. The full citation details ...](Pics/full.jpeg) |
1976 |
DBLP DOI BibTeX RDF |
|
19 | Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia |
"Timing closure by design, " a high frequency microprocessor design methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 712-717, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
chip integration, dynamic circuits0, CAD, methodology, microprocessor, timing analysis, PLA, timing closure |
19 | Fred J. Taylor, Rabinder Gill, Jim Joseph, Jeff Radke |
A 20 Bit Logarithmic Number System Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(2), pp. 190-200, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
logarithmic number system processor, arithmetic processor, partitioned memory, integrated Schottky logic, 20 bit, satellite computers, performance evaluation, performance evaluation, architecture, computer architecture, digital arithmetic, PLA, microprocessor chips, table lookup, table lookup, ROM, field effect integrated circuits |
19 | Mamoru Tanaka, Shinji Ozawa, Shinsaku Mori |
Rewritable Progammable Logic Array of Current Mode Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(3), pp. 229-234, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
Array logic, functional memory, logic-in-memory, associative memory, PLA, LSI, CML |
18 | Steve Ferrera, Nicholas P. Carter |
A magnetoelectronic macrocell employing reconfigurable threshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 143-151, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
PLA/CPLD, magnetoelectronic circuits, wired-and logic, threshold logic, lookup table, non-volatility |
18 | Behrooz Parhami |
Tight Upper Bounds on the Minimum Precision Required of the Divisor and the Partial Remainder in High-Radix Division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(11), pp. 1509-1514, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
digit-selector PLA, high-radix division, p-d plot, quotient digit selection, SRT division, Digit-recurrence division |
18 | Teruhiko Yamada, Toshinori Kotake, Hiroshi Takahashi, Koji Yamazaki |
Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 269-274, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
sequential PLA, seqnetial test, redundancy identification, design for testability, redundant fault |
18 | Michael K. Gowan, Larry L. Biro, Daniel B. Jackson |
Power Considerations in the Design of the Alpha 21264 Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 726-731, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
technology mapping, programmable logic devices, PLA-style logic blocks |
18 | Vivek Tiwari, Deo Singh, Suresh Rajgopal, Gaurav Mehta, Rakesh Patel, Franklin Baez |
Reducing Power in High-Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 732-737, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
technology mapping, programmable logic devices, PLA-style logic blocks |
18 | Jason Cong, Songjie Xu |
Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 704-707, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
technology mapping, programmable logic devices, PLA-style logic blocks |
18 | Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes, Sven Wuytack, Gjalt G. de Jong, Francky Catthoor, Diederik Verkest, Paul Six, Hugo De Man |
Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 76-81, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
technology mapping, programmable logic devices, PLA-style logic blocks |
18 | Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala |
A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(7), pp. 881-886, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
1-out-of-N code, minimum gate delay, NOR array, NOR-NOR PLA, fault tolerant computing, logic testing, delays, logic design, translator, error detection codes, logic arrays, totally self-checking checker |
18 | Louise Trevillyan, William H. Joyner Jr., C. Leonard Berman |
Global Flow Analysis in Automatic Logic Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(1), pp. 77-81, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
PLA's, Automatic logic design, global flow analysis, compilers, control logic |
18 | Hao-Yung Lo, Yoshinao Aoki |
Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 34(8), pp. 681-691, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
ROM's, Arithmetic units error correction, binary antilogarithm generation, binary logarithm generation, differential group programmable logic arrays (DGPLA's), PLA's |
18 | Christos A. Papachristou |
Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(10), pp. 961-968, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
Addition and multiplication mod M, discrete functions, optimal residue encoding, PLA's, programmable array logic (PAL), residue-based functions, ROM's, VLSI, associative memories |
18 | Javad Khakbaz |
Totally Self-Checking Checker for 1-out-of-n Code Using Two-Rail Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(7), pp. 677-681, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
code disjoint, 1-out-of-n code, programmable logic array (PLA) totally self-checking (TSC), Checker, two-rail code |
18 | Howard Trickey |
Good Layouts for Pattern Recognizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(6), pp. 514-520, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
Control logic design, programmable logic arrays (PLA's), string pattern recognition, dynamic programming, partitioning, regular expressions, VLSI layout, silicon compilers |
18 | Hideo Fujiwara, Kozo Kinoshita |
A Design of Programmable Logic Arrays with Universal Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(11), pp. 823-828, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
Easily testable design, programmable logic arrays (PLA's), fault detection, fault location, logic circuits, universal test sets |
18 | Wilfried Daehn, Joachim Mucha |
A Hardware Approach to Self-Testing of Large Programmable Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(11), pp. 829-833, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
programmable logic array (PLA), Built-in test, pattern generation, nonlinear feedback shift registers |
18 | Thaddeus Kobylarz, Atef Al-Najjar |
An Examination of the Cost Function for Programmable Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(8), pp. 586-590, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
programmable logic arrays (PLA's), cyclic tables, minimal covers, multiple output combinational circuits, minimization, Cost functions |
18 | Roy A. Wood |
A High Density Programmable Logic Array Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(9), pp. 602-608, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
Array folding techniques, array logic, array optimization, folded array configuration, programmable logic array (PLA) |
18 | J. Paul Roth |
Programmed Logic Array Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 27(2), pp. 174-176, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
two-level minimization, programmed logic arrays (PLA's), Minimization |
18 | Mabo Robert Ito, Robert D. Cameron |
Combined Binary Code Translation and Parallel-to-Serial Conversion Using Stored Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 27(9), pp. 833-841, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
ASCII code, code converter, code tree, microprogrammed machine, programmed logic array (PLA), read-only memory (ROM), sequential machine, Morse code |
12 | Dmitrij Lagutin, Sasu Tarkoma |
Public Key Signatures and Lightweight Security Solutions in a Wireless Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEW2AN ![In: Smart Spaces and Next Generation Wired/Wireless Networking, 9th International Conference, NEW2AN 2009 and Second Conference on Smart Spaces, ruSMART 2009, St. Petersburg, Russia, September 15-18, 2009. Proceedings, pp. 253-265, 2009, Springer, 978-3-642-04188-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
wireless networks, Network security, public key cryptography, hash chains |
12 | Bruce Trask, Angel Roman |
Leveraging model driven engineering in software product line architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPLC ![In: Software Product Lines, 13th International Conference, SPLC 2009, San Francisco, California, USA, August 24-28, 2009, Proceedings, pp. 323, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
12 | Jun Du, Qiang Huo |
A feature compensation approach using piecewise linear approximation of an explicit distortion model for noisy speech recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2008, March 30 - April 4, 2008, Caesars Palace, Las Vegas, Nevada, USA, pp. 4721-4724, 2008, IEEE, 1-4244-1484-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Ralph K. Straumann, Ross S. Purves |
Delineation of Valleys and Valley Floors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GIScience ![In: Geographic Information Science, 5th International Conference, GIScience 2008, Park City, UT, USA, September 23-26, 2008. Proceedings, pp. 320-336, 2008, Springer, 978-3-540-87472-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Landform, geomorphometry, valley floor, delineation, valley |
12 | Harika Manem, Peter C. Paliwoda, Garrett S. Rose |
A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 249-254, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
PMLA, FPGA, hybrid |
12 | Tao Jiang, Yucai Feng, Bin Zhang, Jie Shi, Yuanzhen Wang |
Finding Motifs of Financial Data Streams in Real Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISICA ![In: Advances in Computation and Intelligence, Third International Symposium, ISICA 2008, Wuhan, China, December 19-21, 2008 Proceedings, pp. 546-555, 2008, Springer, 978-3-540-92136-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Maryam Razavian, Ramtin Khosravi |
Modeling variability in the component and connector view of architecture using UML. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: The 6th ACS/IEEE International Conference on Computer Systems and Applications, AICCSA 2008, Doha, Qatar, March 31 - April 4, 2008, pp. 801-809, 2008, IEEE Computer Society, 978-1-4244-1967-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Nathaniel Ross Pinckney, Thomas Barr, Michael Dayringer, Matthew McKnett, Nan Jiang 0009, Carl Nygaard, David Money Harris, Joel Stanley, Braden Phillips |
A MIPS R2000 implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 102-107, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
RISC, MIPS |
12 | Andy An-Kai Jeng, Rong-Hong Jan |
The r-Neighborhood Graph: An Adjustable Structure for Topology Control in Wireless Ad Hoc Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 18(4), pp. 536-549, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
energy-efficient, Wireless ad hoc networks, topology control, localized algorithm |
12 | Wenjing Rao, Alex Orailoglu, Ramesh Karri |
Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007, 25-28 June 2007, Edinburgh, UK, Proceedings, pp. 216-224, 2007, IEEE Computer Society, 0-7695-2855-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Amrinder S. Nain, Franklin Chung, Michael Rule, Julie A. Jadlowiec, Phil G. Campbell, Cristina H. Amon, Metin Sitti |
Microrobotically Fabricated Biological Scaffolds for Tissue Engineering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2007 IEEE International Conference on Robotics and Automation, ICRA 2007, 10-14 April 2007, Roma, Italy, pp. 1918-1923, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Christophe Doignon, Michel de Mathelin |
A Degenerate Conic-Based Method for a Direct Fitting and 3-D Pose of Cylinders with a Single Perspective View. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2007 IEEE International Conference on Robotics and Automation, ICRA 2007, 10-14 April 2007, Roma, Italy, pp. 4220-4225, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Tsutomu Sasao, Munehiro Matsuura |
An Implementation of an Address Generator Using Hash Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 69-76, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Yohei Hasegawa, Hideharu Amano |
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 796-799, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Michael Crocker, Michael T. Niemier, Xiaobo Sharon Hu |
Fault Models and Yield Analysis for QCA-based PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 435-440, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan |
Multi-Dimensional Circuit and Micro-Architecture Level Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 275-280, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh |
Power minimization for dynamic PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(6), pp. 616-624, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Tianmiao Wang, Jun Wei 0005, Da Liu, Lei Hu, Wenyong Liu |
An Internet Robot Assistant Tele-neurosurgery System Case. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: 2006 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS 2006, October 9-15, 2006, Beijing, China, pp. 2845-2849, 2006, IEEE, 1-4244-0258-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Garrett S. Rose, Mircea R. Stan |
A programmable majority logic array using molecular scale electronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 225, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Jun Zheng 0003, Emma E. Regentova, Radhika Varadarajan |
Dynamic Planning of Personalized Location Areas for Future PCS Networks with a Simulated Annealing Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 63rd IEEE Vehicular Technology Conference, VTC Spring 2006, 7-10 May 2006, Melbourne, Australia, pp. 608-612, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Yanhong Liu, Samarjit Chakraborty, Radu Marculescu |
Generalized Rate Analysis for Media-Processing Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 16-18 August 2006, Sydney, Australia, pp. 305-314, 2006, IEEE Computer Society, 0-7695-2676-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Uthman Alsaiari, Resve A. Saleh |
Testable and self-repairable structured logic design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert |
Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 15-18 June 2006, Istanbul, Turkey, pp. 179-185, 2006, IEEE Computer Society, 0-7695-2614-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Daesung Lee 0001, Ki-Chang Kim, Year Back Yoo |
IPBio: Embedding Biometric Data in IP Header for Per-Packet Authentication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA Workshops ![In: Frontiers of High Performance Computing and Networking - ISPA 2006 Workshops, ISPA 2006 International Workshops, FHPCN, XHPC, S-GRACE, GridGIS, HPC-GTP, PDCE, ParDMCom, WOMP, ISDF, and UPWN, Sorrento, Italy, December 4-7, 2006, Proceedings, pp. 927-938, 2006, Springer, 3-540-49860-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Meng Yang 0013, Lingli Wang, A. E. A. Almaini |
Fast Conversion for Large Canonical OR-Coincidence Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1643-1646, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Jason Cong, Hui Huang 0001, Xin Yuan 0005 |
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(1), pp. 3-23, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA, technology mapping, CPLD, PLD |
12 | Gan Deng, Gunther Lenz, Douglas C. Schmidt |
Addressing Domain Evolution Challenges in Software Product Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MoDELS (Satellite Events) ![In: Satellite Events at the MoDELS 2005 Conference, MoDELS 2005 International Workshops, Doctoral Symposium, Educators Symposium, Montego Bay, Jamaica, October 2-7, 2005, Revised Selected Papers, pp. 247-261, 2005, Springer, 3-540-31780-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Model Transformation, Model-driven development, Product-line Architectures |
12 | André DeHon |
Design of programmable interconnect for sublithographic programmable logic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 127-137, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Manhattan mesh, sublithographic architecture, programmable logic arrays, nanowires, programmable interconnect |
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