Search results for "PLA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Eli Chiprout, Janusz Rajski, Markus Robinson	Parallel PLA fault simulation based on Boolean vector operations.	ICCAD	1988	DBLP DOI BibTeX RDF
19	William E. Engeler, Menahem Lowy, John Pedicone, John Bloomer, James Richotte, David Chan	A high speed static CMOS PLA architecture.	ICCD	1988	DBLP DOI BibTeX RDF
19	Jing-Yang Jou	A testable PLA design with low overhead and ease of test generation.	ICCD	1988	DBLP DOI BibTeX RDF
19	Rainer Amann, Bernhard Eschermann, Utz G. Baitinger	PLA based finite state machines using Johnson counters as state memories.	ICCD	1988	DBLP DOI BibTeX RDF
19	Markus Robinson, Janusz Rajski	An Algorithmic Branch and Bound Method for PLA Test Pattern Generation.	ITC	1988	DBLP DOI BibTeX RDF
19	Daniele D. Caviglia, Vincenzo Piuri, Mauro Santomauro	About folded-PLA area and folding evaluation.	Integr.	1987	DBLP DOI BibTeX RDF
19	Yue-Sun Kuo, T. C. Hu	An effective algorithm for optimal PLA column folding.	Integr.	1987	DBLP DOI BibTeX RDF
19	Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli	Multiple-Valued Minimization for PLA Optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1987	DBLP DOI BibTeX RDF
19	Andreas Frenzke	PLA - Flächenreduktion durch Faltung - ein Beitrag zur Optimierung von programmierbaren logischen Anordnungen.		1987	RDF
19	Rainer Amann	Algorithmische Entwurfsverfahren für kombinierte PLA-ROM-Steuerwerke unter Verwendung von Zählern.		1987	RDF
19	Yue-Sun Kuo, C. Chen	A Heuristic Algorithm for PLA Block Folding.	J. Inf. Sci. Eng.	1986	DBLP BibTeX RDF
19	Sergio Cesare Brofferio, Michele Taliercio	PLA implementation of a differential predictive coder for digital television signals.	Integr.	1986	DBLP DOI BibTeX RDF
19	Sun Young Hwang, Robert W. Dutton, Tom Blank	A Best-First Search Algorithm for Optimal PLA Folding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1986	DBLP DOI BibTeX RDF
19	Darrell Makarenko, John Tartar	A Statistical Analysis of PLA Folding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1986	DBLP DOI BibTeX RDF
19	Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli	PLATYPUS: A PLA Test Pattern Generation Tool.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1986	DBLP DOI BibTeX RDF
19	Teruhiko Yamada	Syndrome-testable design and syndrome computing method for large PLA's.	Syst. Comput. Jpn.	1986	DBLP DOI BibTeX RDF
19	Chidchanok Lursinsap	Methods for Cell Compilation With Constraints (Vlsi, Pla, Routing, Silicon)		1986	RDF
19	Qingjian Yu, Omar Wing	Interval-graph-based PLA folding.	Integr.	1985	DBLP DOI BibTeX RDF
19	Ming Huei Young, Saburo Muroga	Minimal covering problem and PLA minimization.	Int. J. Parallel Program.	1985	DBLP DOI BibTeX RDF
19	Ming Huei Young, Saburo Muroga	Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF
19	Robert P. Treuer, Hideo Fujiwara, Vinod K. Agarwal	Implementing a Built-In Self-Test PLA Design.	IEEE Des. Test	1985	DBLP DOI BibTeX RDF
19	Vinod K. Agarwal, Janusz Rajski	Testing Properties and Applications of Inverter-Free PLA's.	ITC	1985	DBLP BibTeX RDF
19	James Jacob, Nripendra N. Biswas	: A Testable PLA Design with Minimal Hardware and Test Set.	ITC	1985	DBLP BibTeX RDF
19	Stanley J. Krolikoski	The Squeeze Algorithm for Pla Minimization (Logic, Computer-Aided, Circuit Design)		1985	RDF
19	Bella Bose, Der Jei Lin	PLA Implementation of k-out-of-n Code TSC Checker.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	Code disjoint, k-out-of-n codes, fault detection, self-testing, totally self-checking checkers, fault secure
19	Hideo Fujiwara	A New PLA Design for Universal Testability.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF
19	Tsutomu Sasao	Input Variable Assignment and Output Phase Optimization of PLA's.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	complexity of logic circuits, decoder assignment, essential prime implicants, output phase optimization, logic design, programmable logic array, Adder, switching theory
19	Javad Khakbaz	A Testable PLA Design with Low Overhead and High Fault Coverage.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF
19	Jack R. Egan, C. L. Liu 0001	Bipartite Folding and Partitioning of a PLA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1984	DBLP DOI BibTeX RDF
19	Christos A. Papachriston, James M. Reuter	Microassembly and area reduction techniques for PLA microcode.	MICRO	1984	DBLP BibTeX RDF
19	Helmut Schnelle	Concurrent Parsing In Programmable Logic Array (PLA-) Nets Problems And Proposals.	COLING	1984	DBLP BibTeX RDF
19	J. L. Lewandowski, C. L. Liu 0001	A branch and bound algorithm for optimal pla folding.	DAC	1984	DBLP BibTeX RDF
19	Andreas Roth 0003	Backtrack-Algorithmen für ausgewählte Probleme beim Entwurf von Schaltsystemen mit programmierbaren logischen Feldern (PLA's).		1984	RDF
19	Mohamed Hmimid	Assemblage et génération automatique des dispositifs périphériques de PLA complexes.		1984	RDF
19	Henry Derantonian	Génération automatique de partie(s) contrôle(s) de microprocesseurs sous forme de PLA spécialisés.		1984	RDF
19	Wentai Liu, Daniel E. Atkins	Bounds on the saved area ratio due to PLA folding.	DAC	1983	DBLP BibTeX RDF
19	Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto	A new integrated system for PLA testing and verification.	DAC	1983	DBLP BibTeX RDF
19	Shmuel Wimer, N. Sharfman	HOPLA-PLA optimization and synthesis.	DAC	1983	DBLP BibTeX RDF
19	Jorge Martínez-Carballido, V. Michael Powers	PRONTO: Quick PLA product reduction.	DAC	1983	DBLP BibTeX RDF
19	M. W. Stebnisky, M. J. McGinnis, Joseph C. Werbickas, Rathin Putatunda, A. Feller	APSS: An automatic PLA synthesis system.	DAC	1983	DBLP BibTeX RDF
19	Gary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli	An Algorithm for Optimal PLA Folding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1982	DBLP DOI BibTeX RDF
19	Werner Grass	A depth-first branch-and-bound algorithm for optimal PLA folding.	DAC	1982	DBLP DOI BibTeX RDF
19	Jack R. Egan, C. L. Liu 0001	Optimal bipartite folding of PLA.	DAC	1982	DBLP DOI BibTeX RDF
19	Bill Teel, Doran Wilde	A logic minimizer for VLSI PLA design.	DAC	1982	DBLP DOI BibTeX RDF
19	Sungho Kang, William M. van Cleemput	Automatic PLA synthesis from a DDL-P description.	DAC	1981	DBLP BibTeX RDF
19	Jean-François Paillotin	Optimization of the PLA area.	DAC	1981	DBLP BibTeX RDF
19	I. Suwa, William J. Kubitz	A computer-aided-design system for segmented-folded PLA macro-cells.	DAC	1981	DBLP BibTeX RDF
19	Martin S. Schmokler	Design of Large ALUs Using Multiple PLA Macros.	IBM J. Res. Dev.	1980	DBLP DOI BibTeX RDF
19	Daniel L. Ostapko, Se June Hong	Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's).	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF
19	Samuel H. Fuller, G. A. Mathew	Implementing microprogram storage with PLA's.	SIGARCH Comput. Archit. News	1976	DBLP DOI BibTeX RDF
19	Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia	"Timing closure by design, " a high frequency microprocessor design methodology.	DAC	2000	DBLP DOI BibTeX RDF	chip integration, dynamic circuits0, CAD, methodology, microprocessor, timing analysis, PLA, timing closure
19	Fred J. Taylor, Rabinder Gill, Jim Joseph, Jeff Radke	A 20 Bit Logarithmic Number System Processor.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	logarithmic number system processor, arithmetic processor, partitioned memory, integrated Schottky logic, 20 bit, satellite computers, performance evaluation, performance evaluation, architecture, computer architecture, digital arithmetic, PLA, microprocessor chips, table lookup, table lookup, ROM, field effect integrated circuits
19	Mamoru Tanaka, Shinji Ozawa, Shinsaku Mori	Rewritable Progammable Logic Array of Current Mode Logic.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	Array logic, functional memory, logic-in-memory, associative memory, PLA, LSI, CML
18	Steve Ferrera, Nicholas P. Carter	A magnetoelectronic macrocell employing reconfigurable threshold logic.	FPGA	2004	DBLP DOI BibTeX RDF	PLA/CPLD, magnetoelectronic circuits, wired-and logic, threshold logic, lookup table, non-volatility
18	Behrooz Parhami	Tight Upper Bounds on the Minimum Precision Required of the Divisor and the Partial Remainder in High-Radix Division.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	digit-selector PLA, high-radix division, p-d plot, quotient digit selection, SRT division, Digit-recurrence division
18	Teruhiko Yamada, Toshinori Kotake, Hiroshi Takahashi, Koji Yamazaki	Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	sequential PLA, seqnetial test, redundancy identification, design for testability, redundant fault
18	Michael K. Gowan, Larry L. Biro, Daniel B. Jackson	Power Considerations in the Design of the Alpha 21264 Microprocessor.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
18	Vivek Tiwari, Deo Singh, Suresh Rajgopal, Gaurav Mehta, Rakesh Patel, Franklin Baez	Reducing Power in High-Performance Microprocessors.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
18	Jason Cong, Songjie Xu	Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
18	Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes, Sven Wuytack, Gjalt G. de Jong, Francky Catthoor, Diederik Verkest, Paul Six, Hugo De Man	Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
18	Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala	A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	1-out-of-N code, minimum gate delay, NOR array, NOR-NOR PLA, fault tolerant computing, logic testing, delays, logic design, translator, error detection codes, logic arrays, totally self-checking checker
18	Louise Trevillyan, William H. Joyner Jr., C. Leonard Berman	Global Flow Analysis in Automatic Logic Design.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	PLA's, Automatic logic design, global flow analysis, compilers, control logic
18	Hao-Yung Lo, Yoshinao Aoki	Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	ROM's, Arithmetic units error correction, binary antilogarithm generation, binary logarithm generation, differential group programmable logic arrays (DGPLA's), PLA's
18	Christos A. Papachristou	Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	Addition and multiplication mod M, discrete functions, optimal residue encoding, PLA's, programmable array logic (PAL), residue-based functions, ROM's, VLSI, associative memories
18	Javad Khakbaz	Totally Self-Checking Checker for 1-out-of-n Code Using Two-Rail Codes.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	code disjoint, 1-out-of-n code, programmable logic array (PLA) totally self-checking (TSC), Checker, two-rail code
18	Howard Trickey	Good Layouts for Pattern Recognizers.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	Control logic design, programmable logic arrays (PLA's), string pattern recognition, dynamic programming, partitioning, regular expressions, VLSI layout, silicon compilers
18	Hideo Fujiwara, Kozo Kinoshita	A Design of Programmable Logic Arrays with Universal Tests.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	Easily testable design, programmable logic arrays (PLA's), fault detection, fault location, logic circuits, universal test sets
18	Wilfried Daehn, Joachim Mucha	A Hardware Approach to Self-Testing of Large Programmable Logic Arrays.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	programmable logic array (PLA), Built-in test, pattern generation, nonlinear feedback shift registers
18	Thaddeus Kobylarz, Atef Al-Najjar	An Examination of the Cost Function for Programmable Logic Arrays.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	programmable logic arrays (PLA's), cyclic tables, minimal covers, multiple output combinational circuits, minimization, Cost functions
18	Roy A. Wood	A High Density Programmable Logic Array Chip.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	Array folding techniques, array logic, array optimization, folded array configuration, programmable logic array (PLA)
18	J. Paul Roth	Programmed Logic Array Optimization.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	two-level minimization, programmed logic arrays (PLA's), Minimization
18	Mabo Robert Ito, Robert D. Cameron	Combined Binary Code Translation and Parallel-to-Serial Conversion Using Stored Logic Arrays.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	ASCII code, code converter, code tree, microprogrammed machine, programmed logic array (PLA), read-only memory (ROM), sequential machine, Morse code
12	Dmitrij Lagutin, Sasu Tarkoma	Public Key Signatures and Lightweight Security Solutions in a Wireless Environment.	NEW2AN	2009	DBLP DOI BibTeX RDF	wireless networks, Network security, public key cryptography, hash chains
12	Bruce Trask, Angel Roman	Leveraging model driven engineering in software product line architectures.	SPLC	2009	DBLP BibTeX RDF
12	Jun Du, Qiang Huo	A feature compensation approach using piecewise linear approximation of an explicit distortion model for noisy speech recognition.	ICASSP	2008	DBLP DOI BibTeX RDF
12	Ralph K. Straumann, Ross S. Purves	Delineation of Valleys and Valley Floors.	GIScience	2008	DBLP DOI BibTeX RDF	Landform, geomorphometry, valley floor, delineation, valley
12	Harika Manem, Peter C. Paliwoda, Garrett S. Rose	A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	PMLA, FPGA, hybrid
12	Tao Jiang, Yucai Feng, Bin Zhang, Jie Shi, Yuanzhen Wang	Finding Motifs of Financial Data Streams in Real Time.	ISICA	2008	DBLP DOI BibTeX RDF
12	Maryam Razavian, Ramtin Khosravi	Modeling variability in the component and connector view of architecture using UML.	AICCSA	2008	DBLP DOI BibTeX RDF
12	Nathaniel Ross Pinckney, Thomas Barr, Michael Dayringer, Matthew McKnett, Nan Jiang 0009, Carl Nygaard, David Money Harris, Joel Stanley, Braden Phillips	A MIPS R2000 implementation.	DAC	2008	DBLP DOI BibTeX RDF	RISC, MIPS
12	Andy An-Kai Jeng, Rong-Hong Jan	The r-Neighborhood Graph: An Adjustable Structure for Topology Control in Wireless Ad Hoc Networks.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	energy-efficient, Wireless ad hoc networks, topology control, localized algorithm
12	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays.	DSN	2007	DBLP DOI BibTeX RDF
12	Amrinder S. Nain, Franklin Chung, Michael Rule, Julie A. Jadlowiec, Phil G. Campbell, Cristina H. Amon, Metin Sitti	Microrobotically Fabricated Biological Scaffolds for Tissue Engineering.	ICRA	2007	DBLP DOI BibTeX RDF
12	Christophe Doignon, Michel de Mathelin	A Degenerate Conic-Based Method for a Direct Fitting and 3-D Pose of Cylinders with a Single Perspective View.	ICRA	2007	DBLP DOI BibTeX RDF
12	Tsutomu Sasao, Munehiro Matsuura	An Implementation of an Address Generator Using Hash Memories.	DSD	2007	DBLP DOI BibTeX RDF
12	Yohei Hasegawa, Hideharu Amano	Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays.	FPL	2007	DBLP DOI BibTeX RDF
12	Michael Crocker, Michael T. Niemier, Xiaobo Sharon Hu	Fault Models and Yield Analysis for QCA-based PLAs.	FPL	2007	DBLP DOI BibTeX RDF
12	Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan	Multi-Dimensional Circuit and Micro-Architecture Level Optimization.	ISQED	2007	DBLP DOI BibTeX RDF
12	Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh	Power minimization for dynamic PLAs.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Tianmiao Wang, Jun Wei 0005, Da Liu, Lei Hu, Wenyong Liu	An Internet Robot Assistant Tele-neurosurgery System Case.	IROS	2006	DBLP DOI BibTeX RDF
12	Garrett S. Rose, Mircea R. Stan	A programmable majority logic array using molecular scale electronics.	FPGA	2006	DBLP DOI BibTeX RDF
12	Jun Zheng 0003, Emma E. Regentova, Radhika Varadarajan	Dynamic Planning of Personalized Location Areas for Future PCS Networks with a Simulated Annealing Algorithm.	VTC Spring	2006	DBLP DOI BibTeX RDF
12	Yanhong Liu, Samarjit Chakraborty, Radu Marculescu	Generalized Rate Analysis for Media-Processing Platforms.	RTCSA	2006	DBLP DOI BibTeX RDF
12	Uthman Alsaiari, Resve A. Saleh	Testable and self-repairable structured logic design.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert	Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array Structures.	AHS	2006	DBLP DOI BibTeX RDF
12	Daesung Lee 0001, Ki-Chang Kim, Year Back Yoo	IPBio: Embedding Biometric Data in IP Header for Per-Packet Authentication.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
12	Meng Yang 0013, Lingli Wang, A. E. A. Almaini	Fast Conversion for Large Canonical OR-Coincidence Functions.	APCCAS	2006	DBLP DOI BibTeX RDF
12	Jason Cong, Hui Huang 0001, Xin Yuan 0005	Technology mapping and architecture evalution for k/m-macrocell-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	FPGA, technology mapping, CPLD, PLD
12	Gan Deng, Gunther Lenz, Douglas C. Schmidt	Addressing Domain Evolution Challenges in Software Product Lines.	MoDELS (Satellite Events)	2005	DBLP DOI BibTeX RDF	Model Transformation, Model-driven development, Product-line Architectures
12	André DeHon	Design of programmable interconnect for sublithographic programmable logic arrays.	FPGA	2005	DBLP DOI BibTeX RDF	Manhattan mesh, sublithographic architecture, programmable logic arrays, nanowires, programmable interconnect