Search results for "VLSI-SoC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Zamani, Hossein Pedram, Farhad Mehdipour	An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Cristiano Lazzari, Cristiano Santos, Adriel Ziesemer, Lorena Anghel, Ricardo Reis 0001	Efficient timing closure with a transistor level design flow.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Julien Goulier, Eric André, Marc Renaudin	A new analytical approach of the impact of jitter on continuous time delta sigma converters.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	YuQing Yang 0002, Terry Sculley, Jacob Abraham	A 128dB dynamic range 1kHz bandwidth stereo ADC with 114dB THD.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Yikui Dong, Steve Howard, Freeman Zhong, Scott Lowrie, Ken Paradis, Jan Kolnik, Jeff Burleson	AC-coupling strategy for high-speed transceivers of 10Gbps and beyond.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Ilker Hamzaoglu, Ozgur Tasdizen, Esra Sahin	An efficient H.264 intra frame coder system design.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Sheng-Yu Peng, Paul E. Hasler, David V. Anderson	An analog programmable multi-dimensional radial basis function based classifier.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1		IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007	VLSI-SoC	2007	DBLP BibTeX RDF
1	Shiv Balakrishnan, Chris Eddington	Efficient DSP algorithm development for FPGA and ASIC technologies.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis 0001, Gilson I. Wirth, Ralf Brederlow, Christian Pacha	Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau	Estimating design time for system circuits.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Jorge Fernandez Villena, Wil H. A. Schilders, L. Miguel Silveira	Parametric structure-preserving model order reduction.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Sameer Sharma, L. G. Johnson	First order quasi-static SOI MOSFET channel capacitance model.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt	A low-power CAM using a 12-transistor design cell.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Ricardo Augusto da Luz Reis, Adam Osseiran, Hans-Jörg Pfleiderer (eds.)	VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia	VLSI-SoC	2007	DBLP BibTeX RDF
1	M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas	A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Dimitrios N. Serpanos, Wayne H. Wolf	VLSI models of network-on-chip interconnect.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Adriel Ziesemer, Cristiano Lazzari	Transistor level automatic layout generator for non-complementary CMOS cells.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Srimoyee Sen, Urmimala Roy, Chaitanya Kshirsagar, Navakanta Bhat, Chandan Kumar Sarkar	Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Hua Tang	Hierarchical statistical analysis of performance variation for continuous-time delta-sigma modulators.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Krishna Santhanam, Kenneth S. Stevens	Dynamic gates with hysteresis and configurable noise tolerance.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Vijay Sundaresan, Srividhya Rammohan, Ranga Vemuri	Power invariant secure IC design methodology using reduced complementary dynamic and differential logic.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Jungsoo Kim, Kyungsu Kang, Heejun Shim, Woong Hwangbo, Chong-Min Kyung	Fast estimation of software energy consumption using IPI(Inter-Prefetch Interval) energy model.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci	A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis	Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Vyas Krishnan, Srinivas Katkoori	Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Run Chen, Liyuan Liu, Dongmei Li, Zhihua Wang 0001	Full custom design of a three-stage amplifier with 5500MHz·pF/mW Performance in 0.18 mum CMO S.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Davide Pandini, Giuseppe Desoli, Alessandro Cremonesi	Computing and design for software and silicon manufacturing.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Robert K. Henderson, Bruce Rae, David R. Renshaw, Edoardo Charbon	Oversampled Time Estimation Techniques for Precision Photonic Detectors.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	K. Schultz, Ketan Paranjape	SOC Debug Challenges and Tools.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Yann Oddos, Katell Morin-Allory, Dominique Borrione	On-Line Test Vector Generation from Temporal Constraints Written in PSL.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin	Security evaluation of dual rail logic against DPA attacks.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Ming Zhang 0017, Norbert Seifert, T. M. Mak, Kee Sup Kim	Soft Error Resilient System Design through Error Correction.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Shampa Chakraverty, Arvind Batra, Aman Rathi	Directed Convergence Heuristic: A fast & novel approach to Steiner Tree Construction.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Anna Bernasconi 0001, Valentina Ciriani, Roberto Cordone	EXOR Projected Sum of Products.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	A. Domman	An overview of where the fields of SoCs, HDI and MEMS are heading to and how to characterize them.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Sujan Pandey, Tudor Murgan, Manfred Glesner	Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer	Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Beate Muranko, Rolf Drechsler	Technical Documentation of Software and Hardware in Embedded Systems.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi	Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen	Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Shan Jiang, Manh Anh Do, Kiat Seng Yeo	A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Justin Xu, Cheng-Chew Lim	Modelling Heterogeneous Interactions in SoC Verification.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Ricardo C. Goncalves da Silva, Henri Boudinov, Luigi Carro	A low power high performance CMOS voltage-mode quaternary full adder.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Chin-Cheng Kuo, Chien-Nan Jimmy Liu	On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Margrit R. Krug, Marcelo Lubaszewski, Marcelo de Souza Moraes	Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Malav Shah, Dipankar Nagchoudhuri	BIST Scheme for Low Heat Dissipation and Reduced Test Application Time.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Tudor Murgan, Oliver Mitea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner	Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Pierre Vanhauwaert, Régis Leveugle, Philippe Roche	Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Vagner S. Rosa, Eduardo A. C. da Costa, Sergio Bampi	A VHDL Generation Tool for Optimized Parallel FIR Filters.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Sinan Yalcin, Ilker Hamzaoglu	A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto, Tetsuro Matsuno	A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Carlotta Guiducci, Claudio Stagni, M. Brocchi, Massimo Lanzoni, Bruno Riccò, Augusto Nascetti, Davide Caputo, Giampiero de Cesare	Innovative Optoelectronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo	A New Phase Noise Model for TSPC based divider.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin	State-holding in Look-Up Tables: application to asynchronous logic.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis	Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Ron Press, Jay Jahangiri	The Demand and Practical Approach for 100x Test Compression.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Mehmet Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici	A Predictable Communication Scheme for Embedded Multiprocessor Systems.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík	MDCT IP Core Generator with Architectural Model Simulation.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Ravindra V. Kshirsagar, Rajendra M. Patrikar	Design of a Reconfigurable Multiprocessor Core for Higher Performance and Reliability of Embedded Systems.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Bilge Saglam Akgul, Lakshmi N. Chakrapani, Pinar Korkmaz, Krishna V. Palem	Probabilistic CMOS Technology: A Survey and Future Directions.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Marco Giorgetta, Marco D. Santambrogio, Donatella Sciuto, Paola Spoletini	A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Yngvar Berg, Omid Mirmotahari, Snorre Aunet	Pseudo Floating-Gate Inverter with Feedback Control.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro	Automatic Dataflow Execution with Reconfiguration and Dynamic Instruction Merging.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz	Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Antonis Papanikolaou, Miguel Miranda, Hua Wang, Francky Catthoor, M. Satyakiran, Pol Marchal, Ben Kaczer, C. Bruynseraede, Zsolt Tokei	Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Pablo García Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli	A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Luís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira	Variation-Aware, Library Compatible Delay Modeling Strategy.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Pierre G. Paulin, Essaid Bensoudane	An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Ramachandruni Venkata Kamala, M. B. Srinivas	High-Throughput Montgomery Modular Multiplication.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Rodrigo M. Passos, José Augusto Miranda Nacif, Raquel A. F. Mini, Antonio Alfredo Ferreira Loureiro, Antônio Otávio Fernandes, Claudionor José Nunes Coelho Jr.	System-level Dynamic Power Management Techniques for Communication Intensive Devices.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Sam Kavusi, Kunal Ghosh, Abbas El Gamal	Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Matteo Murgida, Alessandro Panella, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto	Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Wagston T. Staehler, Eduardo A. Berriel, Altamiro Amadeu Susin, Sergio Bampi	Architecture of an HDTV Intraframe Predictor for a H.264 Decoder.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Livier Lizarraga, Salvador Mir, Gilles Sicard, Ahcène Bounceur	Study of a BIST Technique for CMOS Active Pixel Sensors.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Jacques Benkowski	The system is really in the SoC : new investment opportunities.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Jean-Pierre Schoellkopf	Design challenges for the 45 nm node and below.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Bert Gyselinckx, Ruud J. M. Vullers, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov	Human++: Emerging Technology for Body Area Networks.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Alain J. Martin	Can Asynchronous Techniques Help the SoC Designer?	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Augusto da Luz Reis	An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu	CAT platform for analogue and mixed-signal test evaluation and optimization.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Shekhar Borkar	Introduction to panel discussion Probabilistic & statistical design - the wave of the future.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Senthamaraikannan Raghunath, Syed Mahfuzul Aziz	High Speed Area Efficient Multi-resolution 2-D 9/7 filter DWT Processor.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Shih-Chieh Wu, Chun-Yao Wang	PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Xue-mi Zhao, Zhiying Wang 0003, Hongyi Lu, Kui Dai	A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Se Hun Kim, Vincent John Mooney	Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Shoji Kawahito	Circuit and Device Technologies for CMOS functional Image Sensors.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Sujan Pandey, Nurten Utlu, Manfred Glesner	Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Ulrich Bockelmann	Detecting DNA by field effect transistor arrays.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann 0001, Wolfgang Rosenstiel	Organic Computing at the System on Chip Level.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Hanene Ben Fradj, Cécile Belleudy, Michel Auguin	Main Memory Energy Optimization for Multi-Task Applications.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Motoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi	Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Jeff Brateman, Changjiu Xian, Yung-Hsiang Lu	Energy-Effcient Scheduling for Autonomous Mobile Robots.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Hamid Shojaei, Mohammad Sayyaran	Signal Coverage Computation in Formal Verification.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Hsin-Chou Chi, Chia-Ming Wu	An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.	A Fast SAT Solver Strategy Based on Negated Clauses.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Ramon Tortosa Navas, Antonio Aceituno, José M. de la Rosa 0001, Francisco V. Fernández 0001, Ángel Rodríguez-Vázquez	Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time Sigma-Delta Modulator.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara	A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits.	VLSI-SoC	2006	DBLP DOI BibTeX RDF

Publications at "VLSI-SoC"( http://dblp.L3S.de/Venues/VLSI-SoC )