Search results for "adders"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Keklik Alptekin Bayam, Siddika Berna Örs	Differential Power Analysis resistant hardware implementation of the RSA cryptosystem.	ISCAS	2008	DBLP DOI BibTeX RDF
9	Basant K. Mohanty, Pramod Kumar Meher	Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder.	ASAP	2008	DBLP DOI BibTeX RDF
9	Basant K. Mohanty, Pramod Kumar Meher	Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform.	ASAP	2008	DBLP DOI BibTeX RDF
9	Ivan D. Castellanos, James E. Stine	Compressor trees for decimal partial product reduction.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	VLSI, decimal arithmetic
9	Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin, Kenan Unlu	Hierarchical Soft Error Estimation Tool (HSEET).	ISQED	2008	DBLP DOI BibTeX RDF	Reliability, Soft Errors, Flip-Flop, Combinational Logic
9	Hyoung Jin Yun, Jang Woong Park, Myung Hoon Sunwoo	Data-aided algorithm based frequency synchronizer for DVB-S2.	ICUIMC	2008	DBLP DOI BibTeX RDF	coarse frequency synchronizer, data-aided (DA) algorithm, digital video broadcasting-satellite second generation (DVBS2), initial frequency synchronizer
9	Sundeepkumar Agarwal, Pavankumar V. K., Yokesh R.	Energy-Efficient, High Performance Circuits for Arithmetic Units.	VLSI Design	2008	DBLP DOI BibTeX RDF
9	Nadia Nedjah, Luiza de Macedo Mourelle	Reconfigurable hardware for neural networks: binary versus stochastic.	Neural Comput. Appl.	2007	DBLP DOI BibTeX RDF	Neural network hardware, Stochastic computing
9	Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna	High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	G.1.0.g Parallel algorithms, C.3.e Reconfigurable hardware
9	Kyosun Kim, Kaijie Wu 0001, Ramesh Karri	The Robust QCA Adder Designs Using Composable QCA Building Blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
9	Tad Hogg, Greg Snider	Defect-tolerant Logic with Nanoscale Crossbar Circuits.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	fault modeling, nanotechnology, molecular electronics, circuit reliability
9	Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi	Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme.	ICSAMOS	2007	DBLP DOI BibTeX RDF
9	Toshinori Sato, Yuji Kunitake	Exploiting Input Variations for Energy Reduction.	PATMOS	2007	DBLP DOI BibTeX RDF	typical-case design, dynamic retiming, reliable microarchitecture, robust microarchitecture, DVFS, deep sub-micron
9	Hector Kirschenbaum, Alejandro De la Plaza	Voltage Pump Based on Self Clocked Cells.	ISVLSI	2007	DBLP DOI BibTeX RDF
9	Chin-Liang Wang, Yuan Ouyang, Feng-Hsing Huang	A Low-Complexity Peak-to-Average Power Ratio Reduction Technique for OFDM Systems Using Guided Scrambling Coding.	VTC Spring	2007	DBLP DOI BibTeX RDF
9	Jinbo Xu, Yong Dou, Junfeng Li, Xingming Zhou, Qiang Dou	FPGA Accelerating Algorithms of Active Shape Model in People Tracking Applications.	DSD	2007	DBLP DOI BibTeX RDF
9	Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun, Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan	Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations.	SiPS	2007	DBLP DOI BibTeX RDF
9	Eduardo Mesquita, Helen Franck, Luciano Volcan Agostini, José Luís Güntzel	RIC Fast Adder and its Set Tolerant Implementation in FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
9	Gustavo Liñán Cembrano	Focal plane processors & pixel level processing: mimicking natural vision systems to solve image processing problems.	SBCCI	2007	DBLP DOI BibTeX RDF	analog image processing, neural networks, CMOS image sensors, focal plane
9	Sudhakar Maddi, M. B. Srinivas	A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA.	SBCCI	2007	DBLP DOI BibTeX RDF	sum-carry logic, RSA, ECC, reconfigurable architectures, montgomery multiplication, unified architectures
9	Nachiket Kapre, André DeHon	Optimistic Parallelization of Floating-Point Accumulation.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
9	Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman	Robust Energy-Efficient Adder Topologies.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
9	Michal Bidlo	Evolutionary Design of Generic Combinational Multipliers Using Development.	ICES	2007	DBLP DOI BibTeX RDF
9	Lukás Sekanina	Evolution of Polymorphic Self-checking Circuits.	ICES	2007	DBLP DOI BibTeX RDF
9	Edgar Ferrer, Dorothy Bollman, Oscar Moreno	A Fast Finite Field Multiplier.	ARC	2007	DBLP DOI BibTeX RDF
9	Yong Dou, Jinbo Xu	FPGA-Accelerated Active Shape Model for Real-Time People Tracking.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	FPGA, Active Shape Model, People Tracking
9	Zbysek Gajda, Lukás Sekanina	Reducing the number of transistors in digital circuits using gate-level evolutionary design.	GECCO	2007	DBLP DOI BibTeX RDF	digital circuits, evolvable hardware, evolutionary design
9	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura	On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--.	ISMVL	2007	DBLP DOI BibTeX RDF
9	Tsutomu Sasao	An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays.	ISMVL	2007	DBLP DOI BibTeX RDF
9	Henning Gundersen, Yngvar Berg	Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices.	ISMVL	2007	DBLP DOI BibTeX RDF
9	Nilanjan Banerjee, Jung Hwan Choi, Kaushik Roy 0001	A process variation aware low power synthesis methodology for fixed-point FIR filters.	ISLPED	2007	DBLP DOI BibTeX RDF	fixed-point FIR filters, variation aware, low-power, synthesis
9	Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy 0001	Low-power process-variation tolerant arithmetic units using input-based elastic clocking.	ISLPED	2007	DBLP DOI BibTeX RDF	elastic clocking, process tolerant, low power
9	Oscar Gustafsson	A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Juha Yli-Kaakinen, Tapio Saramäki	A Simplified Structure for FIR Filters with an Adjustable Fractional Delay.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Rachit Agarwal 0001, Emanuel M. Popovici, Brendan O'Flynn, Michael E. O'Sullivan	A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Shrutisagar Chandrasekaran, Abbes Amira	Novel Sparse OBC based Distributed Arithmetic Architecture for Matrix Transforms.	ISCAS	2007	DBLP DOI BibTeX RDF
9	John Moskal, Erdal Oruklu, Jafar Saniie	Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Awni Itradat, M. Omair Ahmad, Ali M. Shatnawi	Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional Units.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel High-Speed Redundant Binary to Binary converter using Prefix Networks.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Steffen Tarnick	Design of Embedded m-out-of-n Code Checkers Using Complete Parallel Counters.	IOLTS	2007	DBLP DOI BibTeX RDF
9	Piotr Zajac, Jacques Henri Collet	Production Yield and Self-Configuration in the Future Massively Defective Nanochips.	DFT	2007	DBLP DOI BibTeX RDF
9	Timothy J. Dysart, Peter M. Kogge	Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder.	DFT	2007	DBLP DOI BibTeX RDF
9	Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee	Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors.	VTS	2007	DBLP DOI BibTeX RDF
9	John P. Hayes, Ilia Polian, Bernd Becker 0001	An Analysis Framework for Transient-Error Tolerance.	VTS	2007	DBLP DOI BibTeX RDF
9	Sanjiv Kumar Mangal, Raghavendra B. Deshmukh, Rahul M. Badghare, Rajendra M. Patrikar	FPGA Implementation of Low Power Parallel Multiplier.	VLSI Design	2007	DBLP DOI BibTeX RDF
9	Dongku Kang, Hunsoo Choo, Khurram Muhammad, Kaushik Roy 0001	Layout-driven architecture synthesis for high-speed digital filters.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
9	Sangjin Hong, Kyoung-Su Park, Jun-Hee Mun	Design and implementation of a high-speed matrix multiplier based on word-width decomposition.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
9	George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	testability conditions, datapath testing, floating-point unit testing, Test generation, processor testing
9	Tsutomu Sasao	Analysis and synthesis of weighted-sum functions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
9	Seyed Ebrahim Esmaeili, Nabil I. Khachab, Moustafa Y. Ghannam	Effect of Glitches on the Efficiency of Components' Region-Constrained Placement as a Fast Approach to Reduce FPGA's Dynamic Power Consumption.	ISVLSI	2006	DBLP DOI BibTeX RDF
9	Johannes Grad, James E. Stine	Dual-Mode High-Speed Low-Energy Binary Addition.	ISVLSI	2006	DBLP DOI BibTeX RDF
9	Anup Hosangadi, Farzan Fallah, Ryan Kastner	Optimizing high speed arithmetic circuits using three-term extraction.	DATE	2006	DBLP DOI BibTeX RDF
9	Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff	Soft delay error analysis in logic circuits.	DATE	2006	DBLP DOI BibTeX RDF
9	Ahmet Akkas	Dual-Mode Quadruple Precision Floating-Point Adder.	DSD	2006	DBLP DOI BibTeX RDF	Quadruple precision, dualmode, computer arithmetic, floating-point, adder, double precision
9	Chuan He, Guan Qin, Mi Lu, Wei Zhao 0001	An Optimized Finite Difference Computing Engine on FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
9	Kazuo Sakiyama, Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems.	ARC	2006	DBLP DOI BibTeX RDF	RSA, Elliptic Curve Cryptography (ECC), Public-Key Cryptography (PKC), Reconfigurable architecture, FPGA implementation
9	Mariusz Bajger, Amos Omondi	Implementations of Square-Root and Exponential Functions for Large FPGAs.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
9	Jason George, Bo Marr, Bilge Saglam Akgul, Krishna V. Palem	Probabilistic arithmetic and energy efficient embedded signal processing.	CASES	2006	DBLP DOI BibTeX RDF	PCMOS, probabilistic arithmetic, low power, DSP, probabilistic computing
9	A. Prasad Vinod 0001, Ankita Singla, Chip-Hong Chang	Improved differential coefficients-based low power FIR filters. Part I. Fundamentals.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Kiran Puttaswamy, Gabriel H. Loh	The impact of 3-dimensional integration on the design of arithmetic units.	ISCAS	2006	DBLP DOI BibTeX RDF
9	K. Supramaniam, Yong Lian	Complexity reduction for frequency-response masking filters using cyclotomic polynomial prefilters.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede	A fast dual-field modular arithmetic logic unit and its hardware implementation.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Ali Bastani, Charles A. Zukowski	A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology.	ISQED	2006	DBLP DOI BibTeX RDF
9	Andrea Boni, Alessandro Zorat	FPGA Implementation of Support Vector Machines with Pseudo-Logarithmic Number Representation.	IJCNN	2006	DBLP DOI BibTeX RDF
9	Himanshu Thapliyal, Anvesh Ramasahayam, Vivek Reddy Kotha, Kunul Gottimukkula, M. B. Srinivas	Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder.	DELTA	2006	DBLP DOI BibTeX RDF
9	Shyue-Kung Lu, Ting-Yu Chen, Wei-Yuan Liu	Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits.	PRDC	2006	DBLP DOI BibTeX RDF
9	Tze-Yun Sung, Mao-Jen Sun, Yaw-Shih Shieh, Hsi-Chin Hsin	Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation.	PSIVT	2006	DBLP DOI BibTeX RDF	parallel-pipelined architecture, memory-efficiency, DCT, high-performances, IDCT
9	Rodney Van Meter, Kae Nemoto, W. J. Munro, Kohei M. Itoh	Distributed Arithmetic on a Quantum Multicomputer.	ISCA	2006	DBLP DOI BibTeX RDF
9	Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung, Ming-Chien Tsai	High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability.	APCCAS	2006	DBLP DOI BibTeX RDF
9	Tapio Saramäki, Juha Yli-Kaakinen	A Novel Systematic Approach for Synthesizing Multiplication-Free Highly-Selective FIR Half-Band Decimators and Interpolators.	APCCAS	2006	DBLP DOI BibTeX RDF
9	Chih-Peng Fan	Cost-Effective Hardware Sharing Architectures of Fast 8×8 and 4×4 Integer Transforms for H.264/AVC.	APCCAS	2006	DBLP DOI BibTeX RDF
9	Håkan Johansson, Oscar Gustafsson, J. Johansson, Lars Wanhammar	Adjustable Fractional-Delay FIR Filters Using the Farrow Structure and Multirate Techniques.	APCCAS	2006	DBLP DOI BibTeX RDF
9	Basant K. Mohanty, Pramod Kumar Meher	Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform.	APCCAS	2006	DBLP DOI BibTeX RDF
9	Su-Hon Lin, Ming-Hwa Sheu, Jing-Shiun Lin, Wen-Tsai Sheu	Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1).	APCCAS	2006	DBLP DOI BibTeX RDF
9	Basant K. Mohanty, Pramod Kumar Meher	VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT.	APCCAS	2006	DBLP DOI BibTeX RDF
9	Chih-Peng Fan, Mau-Shih Lee, Guo-An Su	A Low Multiplier and Multiplication Costs 256-point FFT Implementation with Simplified Radix-24 SDF Architecture.	APCCAS	2006	DBLP DOI BibTeX RDF
9	A. Prasad Vinod 0001, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla	Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis.	APCCAS	2006	DBLP DOI BibTeX RDF
9	Jiajia Chen 0002, Chip-Hong Chang, A. Prasad Vinod 0001	Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics.	APCCAS	2006	DBLP DOI BibTeX RDF
9	Ajay Kumar Verma, Paolo Ienne	Towards the automatic exploration of arithmetic-circuit architectures.	DAC	2006	DBLP DOI BibTeX RDF
9	Daniel Larkin, Andrew Kinane, Noel E. O'Connor	Towards Hardware Acceleration of Neuroevolution for Multimedia Processing Applications on Mobile Devices.	ICONIP (3)	2006	DBLP DOI BibTeX RDF
9	Ahmad A. Hiasat	VLSI implementation of new arithmetic residue to binary decoders.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
9	Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang	A micropower low-voltage multiplier with reduced spurious switching.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
9	Koushik Maharatna, Swapna Banerjee, Eckhard Grass, Milos Krstic, Alfonso Troya	Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
9	Hun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, Chein-Wei Jen	A memory-efficient realization of cyclic convolution and its application to discrete cosine transform.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
9	Saraju P. Mohanty, N. Ranganathan	Energy-efficient datapath scheduling using multiple voltages and dynamic clocking.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	dynamic frequency clocking, low-power datapath synthesis, multiple voltage scheduling, time-constrained scheduling, High-level synthesis, resource-constrained scheduling
9	Ahmad A. Al-Yamani, Edward J. McCluskey	Test chip experimental results on high-level structural test.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	test experiment, Structural test, VLSI test, complex gates
9	Gustavo A. Ruiz, Juan A. Michell, Angel M. Burón	Parallel-pipeline 8×8 forward 2-D ICT processor chip for image coding.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
9	Phakphoom Boonyanant, Sawasd Tantaratana	Design and hybrid realization of FIR Nyquist filters with quantized coefficients and low sensitivity to timing jitter.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
9	Radu Zlatanovici, Borivoje Nikolic	Power - Performance Optimization for Custom Digital Circuits.	PATMOS	2005	DBLP DOI BibTeX RDF
9	Ming Z. Zhang, Hau T. Ngo, Adam R. Livingston, Vijayan K. Asari	An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels.	ISVLSI	2005	DBLP DOI BibTeX RDF	2-D convolution, symmetric kernel, pipelined architecture, systolic architecture
9	Ling Zhuo, Viktor K. Prasanna	Sparse Matrix-Vector multiplication on FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, reconfigurable architecture, high performance, floating-point, sparse matrix
9	Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie 0001	Reliability-Centric High-Level Synthesis.	DATE	2005	DBLP DOI BibTeX RDF
9	Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Ivan E. Sutherland	GasP Control for Domino Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
9	Tongquan Wei, Kaijie Wu 0001, Ramesh Karri, Alex Orailoglu	Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands.	ASP-DAC	2005	DBLP DOI BibTeX RDF
9	Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	Design of a radix-2m hybrid array multiplier using carry save adder format.	SBCCI	2005	DBLP DOI BibTeX RDF	hybrid multiplier, low power, carry save adder
9	Khan Wahid, Vassil S. Dimitrov, Graham A. Jullien	Error-Free Computation of 8x8 2-D DCT and IDCT Using Two-Dimensional Algebraic Integer Quantization.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
9	Masaharu Imai, Akira Kitajima	Verification Challenges in Configurable Processor Design with ASIP Meister.	CHARME	2005	DBLP DOI BibTeX RDF
9	Juha Yli-Kaakinen, Tapio Saramäki	Design and implementation of multiplierless adjustable fractional-delay all-pass filters.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
9	Li-Hsun Chen, Oscal T.-C. Chen, Teng-Yi Wang, Yung-Cheng Ma	A multiplication-accumulation computation unit with optimized compressors and minimized switching activities.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
9	Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan	A new formulation of fast diminished-one multioperand modulo 2n/+1 adder.	ISCAS (1)	2005	DBLP DOI BibTeX RDF