Search results for "co-synthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Pao-Ann Hsiung	Formal synthesis and code generation of embedded real-time software.	CODES	2001	DBLP DOI BibTeX RDF	embedded real-time software, scheduling, Petri Nets, code generation
19	Wen-Nung Lie, Bo-Er Wei	Intermediate view synthesis from binocular images for stereoscopic applications.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
19	Sihem Ben Sassi, Rafik Braham, Abdelfattah Belghith	Neural Speech Synthesis System for Arabic Language Using CELP Algorithm.	AICCSA	2001	DBLP DOI BibTeX RDF
19	Han Bin Kim, Dong Sam Ha, Takeshi Takahashi 0003, Takahiro J. Yamaguchi	A new approach to built-in self-testable datapath synthesis based on integer linear programming.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
19	Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Sequential synthesis using S1S.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
19	Giancarlo Calvagno, Gian Antonio Mian, Roberto Rinaldo	Synthesis filter bank optimization in two-dimensional separable subband coding systems.	IEEE Trans. Image Process.	2000	DBLP DOI BibTeX RDF
19	Kostas Masselos, S. Theoharis, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis	Low power synthesis of sum-of-products computation (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
19	Dariusz Kania	Decomposition-Based Synthesis and its Application in PAL-Oriented Technology Mapping.	EUROMICRO	2000	DBLP DOI BibTeX RDF
19	Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh	Fast and accurate estimation of floorplans in logic/high-level synthesis.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
19	Tomás Bautista, Antonio Núñez	Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells.	ISQED	2000	DBLP DOI BibTeX RDF
19	Victor Kim, Prithviraj Banerjee, Kaushik De	Fine-Grained Parallel VLSI Synthesis for Commercial CAD on a Network of Workstations.	ICPP	2000	DBLP DOI BibTeX RDF
19	Kenneth Y. Yun, David L. Dill	Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations).	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
19	Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha	High-level synthesis of low-power control-flow intensive circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
19	Martin Radetzki, Ansgar Stammermann, Wolfram Putzke-Röming, Wolfgang Nebel	Data Type Analysis for Hardware Synthesis from Object-Oriented Models.	DATE	1999	DBLP DOI BibTeX RDF
19	Bharat P. Dave	CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems.	DATE	1999	DBLP DOI BibTeX RDF
19	Xiaowei Li 0001, Paul Y. S. Cheung	Exploiting Test Resource Optimization in Data Path Synthesis for BIST.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
19	Craig A. Lindley, Anne-Marie Vercoustre	Generic Viewer Interaction Semantics for Dynamic Virtual Video Synthesis.	VISUAL	1999	DBLP DOI BibTeX RDF
19	Robert A. Thacker, Wendy Belluomini, Chris J. Myers	Timed Circuit Synthesis Using Implicit Methods.	VLSI Design	1999	DBLP DOI BibTeX RDF
19	Sandeep Bhatia, Niraj K. Jha	Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
19	Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey	Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
19	Enric Pastor, Jordi Cortadella, Alex Kondratyev, Oriol Roig	Structural methods for the synthesis of speed-independent circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
19	Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi	Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
19	Andrew A. Duncan, David C. Hendry, Peter Gray	An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA Systems.	FCCM	1998	DBLP DOI BibTeX RDF
19	Unni Narayanan, Peichen Pan, C. L. Liu 0001	Low power logic synthesis under a general delay model.	ISLPED	1998	DBLP DOI BibTeX RDF
19	Lech Józwiak, Niek Ederveen, Adam Postula	Solving Synthesis Problems with Genetic Algorithms.	EUROMICRO	1998	DBLP DOI BibTeX RDF
19	Dirk Eisenbiegler, Ramayya Kumar, Christian Blumenröhr	A constructive approach towards correctness of synthesis-application within retiming.	ED&TC	1997	DBLP DOI BibTeX RDF
19	Shan Lu 0004, Seiji Igi, Hideaki Matsuo, Yuji Nagashima	Towards a Dialogue System Based on Recognition and Synthesis of Japanese Sign Language.	Gesture Workshop	1997	DBLP DOI BibTeX RDF
19	Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan	Synthesis of initializable asynchronous circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
19	Claudionor José Nunes Coelho Jr., Giovanni De Micheli	Analysis and synthesis of concurrent digital circuits using control-flow expressions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
19	Jutta Eusterbrock	A Multi-Layer Architecture for Knowledge-Based System Synthesis.	ISMIS	1996	DBLP DOI BibTeX RDF
19	Jem Daalder, Peter W. Eklund, Kenji Ohmori	High-Level Synthesis Optimization with Genetic Algorithms.	PRICAI	1996	DBLP DOI BibTeX RDF
19	Raghava V. Cherabuddi, Jijun Chen, Magdy A. Bayoumi	A Graph-Based Approach to the Synthesis of Multi-Chip Module Architectures.	VLSI Design	1996	DBLP DOI BibTeX RDF
19	Éric Badouel, Luca Bernardinello, Philippe Darondeau	Polynomial Algorithms for the Synthesis of Bounded Nets.	TAPSOFT	1995	DBLP DOI BibTeX RDF
19	S. C. Leung, Hon Fung Li	A syntax-directed translation for the synthesis of delay-insensitive circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
19	Kaushik De, Chitra Natarajan, Devi Nair, Prithviraj Banerjee	RSYN: a system for automated synthesis of reliable multilevel circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
19	Hong-Shin Jun, Sun-Young Hwang	Design of a pipelined datapath synthesis system for digital signal processing.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
19	Kaushik De, Balkrishna Ramkumar, Prithviraj Banerjee	A portable parallel algorithm for logic synthesis using transduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
19	TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang	Logic synthesis for field-programmable gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
19	Said Amellal, Bozena Kaminska	Functional synthesis of digital systems with TASS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
19	Claudionor José Nunes Coelho Jr., Giovanni De Micheli	Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints.	ICCAD	1994	DBLP DOI BibTeX RDF
19	Miriam Leeser, Richard Chapman 0001, Mark D. Aagaard, Mark H. Linderman, Stephan Meier	High level synthesis and generating FPGAs with the BEDROC system.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
19	Vijay Nagasamy, Neerav Berry, Carlos Dangelo	Specification, Planning, and Synthesis in a VHDL Design Environment.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
19	Mark D. Aagaard, Miriam Leeser	Verifying a Logic Synthesis Tool in Nuprl: A Case Study in Software Verification.	CAV	1992	DBLP DOI BibTeX RDF
19	Srinivas Devadas, Kurt Keutzer	A unified approach to the synthesis of fully testable sequential machines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
19	TingTing Hwang, Robert Michael Owens, Mary Jane Irwin	Exploiting communication complexity for multilevel logic synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
19	Raul Camposano	From Behavior to Structure: High-Level Synthesis.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
19	Gregory S. Whitcomb, A. Richard Newton	Abstract Data Types and High-Level Synthesis.	DAC	1990	DBLP DOI BibTeX RDF
19	Henry Massalin, Calton Pu	Threads and Input/Output in the Synthesis Kernel.	SOSP	1989	DBLP DOI BibTeX RDF
19	Dorothy E. Setliff, Rob A. Rutenbar	ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software.	DAC	1989	DBLP DOI BibTeX RDF
19	TingTing Hwang, Robert Michael Owens, Mary Jane Irwin	Multi-Level Logic Synthesis Using Communication Complexity.	DAC	1989	DBLP DOI BibTeX RDF
19	O. A. Buset, Mohamed I. Elmasry	ACE: A Hierarchical Graphical Interface for Architectual Synthesis.	DAC	1989	DBLP DOI BibTeX RDF
19	Debasish Banerjee	A Methodology for Synthesis of Recursive Functional Programs.	ACM Trans. Program. Lang. Syst.	1987	DBLP DOI BibTeX RDF
19	T. Shinsha, T. Kubo, Y. Sakataya, J. Koshishita, Koichiro Ishihara	Incremental logic synthesis through gate logic structure identification.	DAC	1986	DBLP DOI BibTeX RDF
18	Anna Bernasconi 0001, Valentina Ciriani, Roberto Cordone	The optimization of kEP-SOPs: Computational complexity, approximability and experiments.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	multilevel logic synthesis, optimization, approximation algorithm, testing, Automatic synthesis
18	Wei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng	Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential.	EUC Workshops	2007	DBLP DOI BibTeX RDF	Cycle-by-cycle Power Differential, Low Power, High-Level Synthesis, Integer Linear Programming, Operation Scheduling, Data-Path Synthesis
18	Steve Zelinka, Michael Garland	Surfacing by numbers.	Graphics Interface	2006	DBLP BibTeX RDF	geometry synthesis, texture synthesis, selection
18	Saraju P. Mohanty, N. Ranganathan	Energy-efficient datapath scheduling using multiple voltages and dynamic clocking.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	dynamic frequency clocking, low-power datapath synthesis, multiple voltage scheduling, time-constrained scheduling, High-level synthesis, resource-constrained scheduling
18	Matthew Stone, Douglas DeCarlo, Insuk Oh, Christian Rodriguez, Adrian Stere, Alyssa Lees, Christoph Bregler	Speaking with hands: creating animated conversational characters from recordings of human performance.	ACM Trans. Graph.	2004	DBLP DOI BibTeX RDF	animation, motion capture, speech synthesis, conversational agents, motion synthesis, language generation
18	Victor N. Kravets, Prabhakar Kudva	Implicit enumeration of structural changes in circuit optimization.	DAC	2004	DBLP DOI BibTeX RDF	optimization, decomposition, technology mapping, physical synthesis, re-synthesis
18	Jason Cong, Yizhou Lin, Wangning Long	SPFD-based global rewiring.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA synthesis, SPFD, SPFD-based global rewiring, logical re-synthesis
18	Salil Raje, Reinaldo A. Bergamaschi	Generalized resource sharing.	ICCAD	1997	DBLP DOI BibTeX RDF	clique-partitioning-based algorithms, generalized resource sharing, global clique partitioning based framework, interconnect cost estimation, merging cost estimation, sharing possibilities, high level synthesis, high-level synthesis, functional unit, functional units
18	Hans-Georg Martin	Retiming for Circuits with Enable Registers.	EUROMICRO	1996	DBLP DOI BibTeX RDF	enable registers, circuit retiming, combinational paths, D-Flipflops, retiming algorithm, sequential elements, high level synthesis, high level synthesis, digital circuits
18	Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar	A multiplier generator for Xilinx FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
18	Craig Farnsworth, David A. Edwards, Jianwei Liu, Shiv S. Sikand	A hybrid asynchronous system design environment.	ASYNC	1995	DBLP DOI BibTeX RDF	hybrid asynchronous system design environment, hybrid design scheme, asynchronous circuit synthesis, Tangram silicon complier, synchronous design techniques, concurrency, high level synthesis, asynchronous circuits, power reduction, performance gains, micropipelines
17	Matthias Bo Stuart, Mikkel Bystrup Stensgaard, Jens Sparsø	Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	routing, system-on-chip, mapping, network-on-chip, synthesis, configuration
17	Mark Thompson 0001, Hristo Nikolov, Todor P. Stefanov, Andy D. Pimentel, Cagkan Erbas, Simon Polstra, Ed F. Deprettere	A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	system-level design and synthesis, rapid prototyping, design space exploration
17	Jiwon Hahn, Qiang Xie, Pai H. Chou	Rappit: framework for synthesis of host-assisted scripting engines for adaptive embedded systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	adaptive systems, scripting, software synthesis
17	Pao-Ann Hsiung, Cheng-Yi Lin	Synthesis of real-time embedded software with local and global deadlines.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	quasi-dynamic scheduling, real-time petri nets, code generation, software synthesis, real-time embedded software
17	Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli	Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification.	ISSS	1996	DBLP DOI BibTeX RDF	low power, High level synthesis, finite state machines, gated clocks
17	Chun Zhang, Yu Hu 0002, Lingli Wang, Lei He 0001, Jiarong Tong	Building a faster boolean matcher using bloom filter.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, SAT, bloom filter, boolean matching, re-synthesis
17	Robin Bergenthum, Jörg Desel, Sebastian Mauser	Comparison of Different Algorithms to Synthesize a Petri Net from a Partial Language.	Trans. Petri Nets Other Model. Concurr.	2009	DBLP DOI BibTeX RDF	Partial Order Behavior, Region Theory, Petri Net, Synthesis Algorithm
17	Armando Solar-Lezama, Christopher Grant Jones, Rastislav Bodík	Sketching concurrent data structures.	PLDI	2008	DBLP DOI BibTeX RDF	concurrency, synthesis, sketching, sat, spin
17	Alisa Devlic, Michal Koziuk, Wybe Horsman	Synthesizing Context for a Sports Domain on a Mobile Device.	EuroSSC	2008	DBLP DOI BibTeX RDF	context synthesis, context operators, sport scenario, context modeling
17	Michael Pucher, Gudrun Schuchmann, Peter Fröhlich 0003	Regionalized Text-to-Speech Systems: Persona Design and Application Scenarios.	COST 2102 School (Vietri)	2008	DBLP DOI BibTeX RDF	sociolect, persona design, speech synthesis, dialect
17	Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu	Type-matching clock tree for zero skew clock gating.	DAC	2008	DBLP DOI BibTeX RDF	physical design, gated clock, clock network synthesis
17	Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler	Numerical Function Generators Using LUT Cascades.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	LUT cascades, numerical function generators (NFGs), nonuniform segmentation, FPGA implementation, automatic synthesis
17	Ajay Kumar Verma, Paolo Ienne	Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands.	ASP-DAC	2007	DBLP DOI BibTeX RDF	multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers
17	Rachel Heck, Michael Gleicher	Parametric motion graphs.	SI3D	2007	DBLP DOI BibTeX RDF	motion capture, motion synthesis, motion graphs
17	Ge Jin, James K. Hahn	High-Resolution Video from Series of Still Photographs.	ISVC (1)	2006	DBLP DOI BibTeX RDF	Image Segmentation, Optical Flow, Video Synthesis
17	Ronghua Liang, Tinan Huang, Meleagros A. Krokos, Jinglong Fan	Visual Perception Modeling for Intelligent Avatars.	ICAT	2006	DBLP DOI BibTeX RDF	sensor perception, motion path synthesis, visual perception, Color model
17	Yan-Wen Guo 0001, Xiaodong Xu, Xi Chen, Jin Wang, Qunsheng Peng 0001	Synthesizing Variational Direction and Scale Texture on Planar Region.	PCM	2006	DBLP DOI BibTeX RDF	texture direction and scale, Computer graphics, texture synthesis, feature matching
17	Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu	Register binding for clock period minimization.	DAC	2006	DBLP DOI BibTeX RDF	high-level synthesis, clock skew, timing optimization
17	Claude Jard, Thierry Jéron	TGV: theory, principles and algorithms.	Int. J. Softw. Tools Technol. Transf.	2005	DBLP DOI BibTeX RDF	Test generation/synthesis, Model-checking, Protocols, Reactive systems, Conformance testing, Transition systems
17	Nadine E. Miner, Thomas P. Caudell	Using wavelets to synthesize stochastic-based sounds for immersive virtual environments.	ACM Trans. Appl. Percept.	2005	DBLP DOI BibTeX RDF	audio perception, virtual reality, wavelets, immersive environments, Sound synthesis
17	Ismail Assayad, Sergio Yovine	Compositional Constraints Generation for Concurrent Real-Time Loops with Interdependent Iterations.	IICS	2005	DBLP DOI BibTeX RDF	Execution constraints synthesis, Concurrent loops, Compositionality
17	Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee	Macro-models for high level area and power estimation on FPGAs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	model, FPGA, high-level synthesis, power estimation, RTL, area estimation
17	Michael W. Whalen, Johann Schumann, Bernd Fischer 0002	Synthesizing Certified Code.	FME	2002	DBLP DOI BibTeX RDF	automatic program synthesis, code certification, program verification, automated theorem proving, proof-carrying code
17	Salim Ouadjaout, Marie-France Albenge, Dominique Houzet	VSIA Interface Cosynthesis.	DELTA	2002	DBLP DOI BibTeX RDF	VSIA, SoC, Co-design, interface synthesis
17	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	Bisimulation relation, complete-1-distinguishability, finite state machine equivalence, sequential logic synthesis, equivalence checking
17	Bernhard K. Aichernig	Test-Case Calculation through Abstraction.	FME	2001	DBLP DOI BibTeX RDF	test-case synthesis, abstraction rules, testing, scenarios, contract, refinement calculus
17	M. Balakrishnan, Heman Khanna	Allocation of FIFO structures in RTL data paths.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	synthesis, RTL, ILP, FIFO, data path
17	Colin Potts	Requirements Models in Context.	RE	1997	DBLP DOI BibTeX RDF	formal specification, requirements engineering, abstraction, synthesis, requirements models
17	Wendy Belluomini, Chris J. Myers	Efficient Timing Analysis Algorithms for Timed State Space Exploration.	ASYNC	1997	DBLP DOI BibTeX RDF	timing analysis algorithms, timed state space exploration, timed circuit synthesis, geometric regions, computational complexity, timing, asynchronous circuits, partial orders
17	Raghava V. Cherabuddi, Magdy A. Bayoumi, H. Krishnamurthy	A low power based system partitioning and binding technique for multi-chip module architectures.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	binding technique, multi-chip module architectures, high-level synthesis framework, inter-chip buses, stochastic evolution based technique, multichip modules, switching activity, MCM, functional units, system partitioning, benchmark designs
17	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ICCAD	1996	DBLP DOI BibTeX RDF	sequential logic synthesis and verification, finite state machine equivalence, bisimulation relation, 1-distinguishability, 1-equivalence, formal verification
17	Kyosun Kim, Ramesh Karri, Miodrag Potkonjak	Heterogeneous built-in resiliency of application specific programmable processors.	ICCAD	1996	DBLP DOI BibTeX RDF	HBIR, ASPP, fault tolerance, synthesis
17	Balakrishnan Iyer, Maciej J. Ciesielski	Metamorphosis: state assignment by retiming and re-encoding.	ICCAD	1996	DBLP DOI BibTeX RDF	Sequential Logic, Finite State Machine, Logic Synthesis, State Assignment, State Encoding
17	Pradeep Prabhakaran, Prithviraj Banerjee	Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs.	ICCD	1996	DBLP DOI BibTeX RDF	parallel algorithms, multiprocessors, High-level synthesis, network of workstations, hierarchical graphs, force-directed scheduling
17	Tarek Ben Ismail, Mohamed Abid, Ahmed Amine Jerraya	COSMOS: a codesign approach for communicating systems.	CODES	1994	DBLP DOI BibTeX RDF	System Design Model, Hardware/Software Codesign, Communication Synthesis
17	Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi	Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms.	ASP-DAC	2008	DBLP DOI BibTeX RDF