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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 246 occurrences of 199 keywords
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Results
Found 384 publication records. Showing 378 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
129 | Paul Metzgen |
A high performance 32-bit ALU for programmable logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 61-70, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ALU, Apex 20KE, Nios, FPGA, programmable logic, soft processors |
117 | Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno |
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA, pp. 162-172, 2001, IEEE Computer Society, 0-7695-1034-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
116 | James Phillips, Stamatis Vassiliadis |
High-Performance 3-1 Interlock Collapsing ALU's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(3), pp. 257-268, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
3-1 interlock collapsing ALU, execution interlocks, multiple instruction issuing machines, parallel architectures, delay, digital arithmetic, CMOS technology, critical path, reduced instruction set computing, Boolean equations |
102 | Steven S. Gorshe, Bella Bose |
A self-checking ALU design with efficient codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 157-161, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
self-checking ALU design, self-testing ALU, VLSI, logic testing, built-in self test, integrated circuit testing, logic design, error detection codes, error detecting codes, integrated logic circuits, unidirectional errors |
93 | Soontae Kim |
Reducing ALU and Register File Energy by Dynamic Zero Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: Proceedings of the 26th IEEE International Performance Computing and Communications Conference, IPCCC 2007, April 11-13, 2007, New Orleans, Louisiana, USA, pp. 365-371, 2007, IEEE Computer Society, 1-4244-1138-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
93 | R. D. (Shawn) Blanton, John P. Hayes |
Design of a fast, easily testable ALU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 9-16, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
ALU, adder design, L-testable design, level-testable, carry-lookahead addition, fault diagnosis, logic testing, integrated circuit testing, automatic testing, digital arithmetic, integrated circuit design, adders, logic arrays, test patterns, area overhead, functional faults, carry logic, arithmetic-logic unit, 8 bit |
82 | Shruti R. Patil, Xiaofeng Yao, Hao Meng, Jianping Wang, David J. Lilja |
Design of a spintronic arithmetic and logic unit using magnetic tunnel junctions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008, pp. 171-178, 2008, ACM, 978-1-60558-077-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
alu design, magnetic tunnel junction, spintronic alu design, spintronics |
81 | Yu Zhou, Hui Guo |
Application Specific Low Power ALU Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC (1) ![In: 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), Shanghai, China, December 17-20, 2008, Volume I, pp. 214-220, 2008, IEEE Computer Society, 978-0-7695-3492-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
80 | Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy 0001 |
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 248-251, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
DSM leakage control and scaling trends, dual supply ALU design, low power techniques |
69 | Ronald D. Blanton, John P. Hayes |
On the design of fast, easily testable ALU's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(2), pp. 220-223, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
69 | Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao, Michael Nicolaidis |
An SFS Berger check prediction ALU and its application to self-checking processor designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4), pp. 525-540, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
68 | R. S. Hogg, W. I. Hughes, David W. Lloyd |
A Novel Asynchronous ALU for Massively Parallel Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 282-289, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit |
68 | Hiromichi Yamada, Takashi Hotta, Takahiro Nishiyama, Fumio Murabayashi, Tatsumi Yamauchi, Hideo Sawamoto |
A 13.3ns double-precision floating-point ALU and multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 466-470, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
double-precision floating-point ALU, floating-point multiplier, carry select addition, prerounding techniques, noise tolerant precharge circuit, two-cycle latency, 13.3 ns, 0.3 micron, 2.5 V, 150 MHz, normalization, floating point arithmetic, CMOS integrated circuits, multiplying circuits, CMOS technology, arithmetic logic unit |
62 | Yves Quentin |
Origin of the Alu family: a family of Alu-like monomers gave birth to the left and the right arms of the Alu elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Nucleic Acids Res. ![In: Nucleic Acids Res. 20(13), pp. 3397-3401, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
57 | Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura |
A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
57 | Steven Hsu, Amit Agarwal 0001, Kaushik Roy 0001, Ram Krishnamurthy 0001, Shekhar Borkar |
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 103-106, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dual-Vt/Vcc, flip-flop, hot spot, level converter |
57 | Mark G. Arnold |
LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 675-684, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
57 | Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam |
A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 376-386, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Complexity-effective design, Temporal Redundancy, Instruction Reuse |
57 | Warren A. Hunt Jr., Bishop Brock |
The Verification of a Bit-slice ALU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hardware Specification, Verification and Synthesis ![In: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings, pp. 282-306, 1989, Springer, 3-540-97226-9. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
48 | Muhammad Taha, Tarek Helmy, Reda Abo Alez |
Agent Based Arabic Language Understanding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Web Intelligence/IAT Workshops ![In: Proceedings of the 2007 IEEE/WIC/ACM International Conference on Web Intelligence and International Conference on Intelligent Agent Technology - Workshops, 2-5 November 2007, Silicon Valley, CA, USA, pp. 429-432, 2007, IEEE Computer Society, 0-7695-3028-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
48 | Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, Brian Towles |
Exploring the VLSI Scalability of Stream Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), Anaheim, California, USA, February 8-12, 2003, pp. 153-164, 2003, IEEE Computer Society, 0-7695-1871-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
47 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
An algorithm for mapping loops onto coarse-grained reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2003 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'03). San Diego, California, USA, June 11-13, 2003, pp. 183-188, 2003, ACM, 1-58113-647-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
ALU array, memory bandwidth utilization, coarse-grained reconfigurable architecture, mapping algorithm |
45 | Bhaskar Chatterjee, Manoj Sachdev |
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(11), pp. 1296-1304, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Francesco Pessolano, R. I. M. P. Meijer |
A 260ps Quasi-static ALU in 90nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 372-380, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Kunihiro Yamada, Yukihisa Naoe, Masanori Kojima, Tadanori Mizuno |
A New MPEG-2 Solution Using a 2nd ALU in the RISC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES ![In: Knowledge-Based Intelligent Information and Engineering Systems, 7th International Conference, KES 2003, Oxford, UK, September 3-5, 2003, Proceedings, Part II, pp. 734-740, 2003, Springer, 3-540-40804-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
45 | Karthikeyan Sankaralingam, Vincent Ajay Singh, Stephen W. Keckler, Doug Burger |
Routed Inter-ALU Networks for ILP Scalability and Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 170-, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
44 | Makoto Ozone, Tatsuo Hiramatsu, Katsunori Hirase, Kazuhisa Iizuka |
Reconfigurable Processor LSI Based on ALU Array with Limitations of Connections of ALUs for Software Radio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Sixth International Conference on Information Technology: New Generations, ITNG 2009, Las Vegas, Nevada, USA, 27-29 April 2009, pp. 837-842, 2009, IEEE Computer Society, 978-0-7695-3596-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ALU array, software define radio, data flow graph, reconfigurable processor |
44 | Wenzhe Luo, Graham A. Jullien, Neil M. Wigley, William C. Miller, Zhongde Wang |
An array processor for inner product computations using a Fermat number ALU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 270-281, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
inner product computations, Fermat number ALU, parallel independent computations, polynomial mapping, computational ring, parallel architectures, residue number systems |
42 | Konstantina Miteloudi, Joppe W. Bos, Olivier Bronchain, Björn Fay, Joost Renes |
PQ.V.ALU.E: Post-Quantum RISC-V Custom ALU Extensions on Dilithium and Kyber. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2023, pp. 1505, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
|
42 | Konstantina Miteloudi, Joppe W. Bos, Olivier Bronchain, Björn Fay, Joost Renes |
PQ.V.ALU.E: Post-quantum RISC-V Custom ALU Extensions on Dilithium and Kyber. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CARDIS ![In: Smart Card Research and Advanced Applications - 22nd International Conference, CARDIS 2023, Amsterdam, The Netherlands, November 14-16, 2023, Revised Selected Papers, pp. 190-209, 2023, Springer, 978-3-031-54408-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
36 | Miroslav N. Velev |
Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 97-113, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Hugo de Garis, Thayne Batty, Wang Ce |
FemtoComputing: New Architectural Ideas for Procedural and Evolutionary Computers Whose Components Switch in Femto-Seconds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 2005 NASA / DoD Conference on Evolvable Hardware (EH 2005), 29 June - 1 July 2005, Washington, DC, USA, pp. 301-306, 2005, IEEE Computer Society, 0-7695-2399-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Michael Nicolaidis |
Carry checking/parity prediction adders and ALUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(1), pp. 121-128, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Kwong-Sak Leung, Kin-Hong Lee, Sin Man Cheang |
Parallel Programs Are More Evolvable than Sequential Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroGP ![In: Genetic Programming, 6th European Conference, EuroGP 2003, Essex, UK, April 14-16, 2003. Proceedings, pp. 107-118, 2003, Springer, 3-540-00971-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Ivo Bolsens |
Challenges and Opportunities for FPGA Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 391-392, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha |
Early Zero Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 545-, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
half-adder form, branch penalties, branch resolution, zero detection, speculative execution, ILP |
36 | F. Kampf, P. Koch, K. Roy, M. Sullivan, Z. Delalic, S. DasGupta |
Optimization of a digital neuron design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 23rd Annual Simulation Symposium (ANSS-23 1990), Nashville, Tennessee, USA, 1990, pp. 73-80, 1990, IEEE Computer Society, 0-8186-2067-6. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
35 | David W. Matula, Asger Munk Nielsen |
Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 140-147, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
pipelined packet forwarding floating point, packet forwarding floating point format, rounder design, packet forwarding format, standard binary IEEE 754 floating point format, multiplication algorithms, ALU pipeline paradigm, data hazards, pipelined floating point operations, execution phases, multiplier packet forwarding pipelines, execution phase, logic levels, multiplier pipelines, forwarding pipelines, IEEE 754 binary floating point compatibility, pipeline arithmetic, data dependent operations |
34 | Xingtuo Zhang, Yiyi Zhang, Alu Xu, Chunli Meng, Zhonghuan Su |
Electrical Insulator Surface Condition Analysis Based on Joint Fully Convolutional and Multiscale Spatial Pooling Attention Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 72, pp. 1-11, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Stéphane D'Alu, Hervé Rivano, Olivier Simonin 0001 |
TDoA for In-Flight Relative Localization in UAV Swarm using Ultra-Wide Band. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPIN-WiP ![In: WiP Proceedings of the Thirteenth International Conference on Indoor Positioning and Indoor Navigation - Work-in-Progress Papers (IPIN-WiP 2023) co-located with 13th International Conference on Indoor Positioning and Indoor Navigation (IPIN 2023), Nuremberg, Germany, September 25 - 28, 2023., 2023, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
|
34 | Fabrizio Vecchio, Francesca Miraglia, Francesca Alù, Elda Judica, Maria Cotelli, Maria Concetta Pellicciari, Paolo Maria Rossini |
Human Brain Networks in Physiological and Pathological Aging: Reproducibility of Electroencephalogram Graph Theoretical Analysis in Cortical Connectivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Brain Connect. ![In: Brain Connect. 12(1), pp. 41-51, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
34 | Aravind Nagulu, Ahmed Mekkawy, Mykhailo Tymchenko, Dimitrios L. Sounas, Andrea Alù, Harish Krishnaswamy |
Ultra-Wideband Switched-Capacitor Delays and Circulators - Theory and Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 56(5), pp. 1412-1424, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
34 | Mirko Barbuto, Andrea Alù, Filiberto Bilotti, Alessandro Toscano |
Dual-Circularly Polarized Topological Patch Antenna With Pattern Diversity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 48769-48776, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
34 | Fabrizio Vecchio, Francesca Miraglia, Chiara Pappalettera, Alessandro Orticoni, Francesca Alù, Elda Judica, Maria Cotelli, Paolo Maria Rossini |
Entropy as Measure of Brain Networks' Complexity in Eyes Open and Closed Conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Symmetry ![In: Symmetry 13(11), pp. 2178, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
34 | Mykhailo Tymchenko, Aravind Nagulu, Harish Krishnaswamy, Andrea Alù |
Universal Frequency-Domain Analysis of N-Path Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 68(2), pp. 569-580, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
34 | Fabrizio Vecchio, Chiara Pappalettera, Francesca Miraglia, Francesca Alù, Alessandro Orticoni, Elda Judica, Maria Cotelli, Francesca Pistoia, Paolo Maria Rossini |
Graph Theory on Brain Cortical Sources in Parkinson's Disease: The Analysis of 'Small World' Organization from EEG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 21(21), pp. 7266, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
34 | Andrea Alù |
Opportunities for Millemeter-Wave Wireless Technologies Using Metasurfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BCICTS ![In: IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2021, Monterey, CA, USA, December 5-8, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3990-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
34 | Francesca Miraglia, Fabrizio Vecchio, Camillo Marra, Davide Quaranta, Francesca Alù, Benedetta Peroni, Giuseppe Granata, Elda Judica, Maria Cotelli, Paolo Maria Rossini |
Small World Index in Default Mode Network Predicts Progression from Mild Cognitive Impairment to Dementia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Neural Syst. ![In: Int. J. Neural Syst. 30(2), pp. 2050004:1-2050004:17, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Ying-Tao Luo, Peng-Qi Li, Dong-Ting Li, Yu-Gui Peng, Zhi-Guo Geng, Shu-Huan Xie, Yong Li, Andrea Alù, Jie Zhu, Xue Feng Zhu |
Probability-Density-Based Deep Learning Paradigm for the Fuzzy Design of Functional Metastructures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2011.05516, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
34 | Mario Miscuglio, Yaliang Gui, Xiaoxuan Ma, Shuai Sun, Tarek A. El-Ghazawi, Tatsuo Itoh, Andrea Alù, Volker J. Sorger |
Analog Computing with Metatronic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2007.05380, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
34 | Francesca Alù, Francesca Miraglia, Alessandro Orticoni, Elda Judica, Maria Cotelli, Paolo Maria Rossini, Fabrizio Vecchio |
Approximate Entropy of Brain Network in the Study of Hemispheric Differences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Entropy ![In: Entropy 22(11), pp. 1220, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Alex Krasnok, Andrea Alù |
Active Nanophotonics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 108(5), pp. 628-654, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Andrea Alù |
Magnet-Free Nonreciprocity [Scanning the Section]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 108(10), pp. 1682-1683, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Andrea Alù, Hilmi Volkan Demir, Chennupati Jagadish |
Active Nanophotonics [Scanning the Issue]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 108(5), pp. 625-627, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Ahmed Kord, Dimitrios L. Sounas, Andrea Alù |
Microwave Nonreciprocity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 108(10), pp. 1728-1758, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Stéphane D'Alu, Oana Iova, Olivier Simonin 0001, Hervé Rivano |
Demo: In-flight Localisation of Micro-UAVs using Ultra-Wide Band. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWSN ![In: Proceedings of the 2020 International Conference on Embedded Wireless Systems and Networks, EWSN 2020, Lyon, France, February 17-18, 2020, pp. 186-188, 2020, ACM, 978-0-9949886-4-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
34 | Andrea Alù |
Magnet-Free Routes to Nonreciprocal Photonics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECOC ![In: European Conference on Optical Communications, ECOC 2020, Virtual Event, Belgium, December 6-10, 2020, pp. 1-2, 2020, IEEE, 978-1-7281-7361-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Lina Han, Jiquan Zhang, Yichen Zhang, Qing Ma, Alu Si, Qiuling Lang |
Hazard Assessment of Earthquake Disaster Chains Based on a Bayesian Network Model and ArcGIS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPRS Int. J. Geo Inf. ![In: ISPRS Int. J. Geo Inf. 8(5), pp. 210, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Alu Si, Jiquan Zhang, Siqin Tong, Quan Lai, Rui Wang, Na Li, Yongbin Bao |
Regional Landslide Identification Based on Susceptibility Analysis and Change Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPRS Int. J. Geo Inf. ![In: ISPRS Int. J. Geo Inf. 7(10), pp. 394, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
34 | Li Na, Jiquan Zhang, Yulong Bao, Yongbin Bao, Risu Na, Siqin Tong, Alu Si |
Himawari-8 Satellite Based Dynamic Monitoring of Grassland Fire in China-Mongolia Border Regions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 18(1), pp. 276, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
34 | Patrice Raveneau, Stephane D'Alu, Hervé Rivano |
Localisation based on Wi-Fi fingerprints: A crowdsensing approach with a device-to-device aim. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PerCom Workshops ![In: 2017 IEEE International Conference on Pervasive Computing and Communications Workshops, PerCom Workshops 2017, Kona, Big Island, HI, USA, March 13-17, 2017, pp. 321-325, 2017, IEEE, 978-1-5090-4338-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
34 | Laëtitia Matignon, Stephane D'Alu, Olivier Simonin 0001 |
Multi-robot human scene observation based on hybrid metric-topological mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECMR ![In: 2017 European Conference on Mobile Robots, ECMR 2017, Paris, France, September 6-8, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-1096-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
34 | Francesco Monticone, Andrea Alù |
Leaky-Wave Theory, Techniques, and Applications: From Microwaves to Visible Frequencies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 103(5), pp. 793-821, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
34 | Pai-Yen Chen, Andrea Alù |
THz beamforming using graphene-based devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RWS ![In: 2013 IEEE Radio and Wireless Symposium, Austin, TX, USA, January 20-23, 2013, pp. 55-57, 2013, IEEE, 978-1-4673-2929-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
34 | Yang Zhao, Andrea Alù |
Optical nanoantennas and their applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RWS ![In: 2013 IEEE Radio and Wireless Symposium, Austin, TX, USA, January 20-23, 2013, pp. 58-60, 2013, IEEE, 978-1-4673-2929-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
34 | Andrea Alù, Nader Engheta |
Optical Metamaterials Based on Optical Nanocircuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 99(10), pp. 1669-1681, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Andrea Alù, Carmine Sapia, Alessandro Toscano, Lucio Vegni |
Radio frequency animal identification: electromagnetic analysis and experimental evaluation of the transponder-gate system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Radio Freq. Identif. Technol. Appl. ![In: Int. J. Radio Freq. Identif. Technol. Appl. 1(1), pp. 90-106, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Mauro Manzini, Andrea Alù, Filiberto Bilotti, Lucio Vegni |
Polygonal patch antennas for wireless communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Veh. Technol. ![In: IEEE Trans. Veh. Technol. 53(5), pp. 1434-1440, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Peter Adebayo Idowu, A. O. Alu, E. R. Adagunodo |
The Effect of Information Technology on the Growth of the Banking Industry in Nigeria. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. J. Inf. Syst. Dev. Ctries. ![In: Electron. J. Inf. Syst. Dev. Ctries. 10(1), pp. 1-8, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Ioannis Voyiatzis |
An ALU-Based BIST Scheme for Word-Organized RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(5), pp. 577-590, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Memory control and access, Reliability, Test generation, Built-In Tests, Testing and Fault-Tolerance, Semiconductor Memories |
33 | Pak-Keung Leung, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun |
A low power asynchronous GF(2173) ALU for elliptic curve crypto-processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 337-340, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang 0001, Whay Sing Lee |
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998, pp. 306-317, 1998, IEEE Computer Society, 0-8186-8491-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Sunwoo Kim, Won Woo Ro |
FPGA implementation of highly parallelized decoder logic for network coding (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 284, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
fpga, network coding, fpga implementation, galois field arithmetic |
24 | Fatemeh Eslami, Amirali Baniasadi, Mostafa Farahani |
Application Specific Transistor Sizing for Low Power Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 195-198, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala |
A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 433-436, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
performance, design |
24 | Xiaohong Qiu, Jaliya Ekanayake, Scott Beason, Thilina Gunarathne, Geoffrey C. Fox, Roger S. Barga, Dennis Gannon |
Cloud technologies for bioinformatics applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC-MTAGS ![In: Proceedings of the 2nd Workshop on Many-Task Computing on Grids and Supercomputers, MTAGS 2009, November 16, 2009, Portland, Oregon, USA, 2009, ACM, 978-1-60558-714-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Dryad, MPI, bioinformatics, multicore, cloud, Hadoop |
24 | Yuzhong Jiao, Xin'an Wang, Xuewen Ni |
A Fully Data-Driven Reconfigurable Architecture with Very Coarse-Grained Execution Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Infoscale ![In: Scalable Information Systems, 4th International ICST Conference, Infoscale 2009, Hong Kong, June 10-11, 2009, Revised Selected Papers, pp. 1-13, 2009, Springer, 978-3-642-10484-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Processing element (PE), Execution unit (EU), Very-coarse-grained, Fully-data-driven, Reconfigurable architecture |
24 | Swaroop Ghosh, Kaushik Roy 0001 |
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 635-640, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Toshinori Sato, Shingo Watanabe |
Instruction Scheduling for Variation-Originated Variable Latencies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 361-364, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
variable latency adder, long latency adder, instruction criticality, microprocessors, parameter variations |
24 | Sean O'Rourke, Noah Zaitlen, Nebojsa Jojic, Eleazar Eskin |
Reconstructing the Phylogeny of Mobile Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RECOMB ![In: Research in Computational Molecular Biology, 11th Annual International Conference, RECOMB 2007, Oakland, CA, USA, April 21-25, 2007, Proceedings, pp. 196-210, 2007, Springer, 3-540-71680-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Krishnan Sundaresan, Nihar R. Mahapatra |
An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 515-520, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | A. J. KleinOsowski, Kevin KleinOsowski, Vijay Rangarajan, Priyadarshini Ranganath, David J. Lilja |
The Recursive NanoBox Processor Grid: A Reliable System Architecture for Unreliable Nanotechnology Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June - 1 July 2004, Florence, Italy, Proceedings, pp. 167-176, 2004, IEEE Computer Society, 0-7695-2052-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
architecture, VLSI, fault-injection, nanotechnology, fault-masking |
24 | Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer |
False-Noise Analysis for Domino Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 784-789, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Ahmet Bindal, Silvio Brugada, T. Ha, Willie Sana, Mandeep Singh, Vinilkant Tejaswi, David Wyland |
A Simple Micro-Threaded Data-Driven Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 70-77, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Timothy Daryl Stanley |
Bringing bits, bytes, devices and computers to life with designs in multimedia logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGITE Conference ![In: Proceedings of the 5th Conference on Information Technology Education, SIGITE 2004, 2004, Salt Lake City, UT, USA, October 28-30, 2004, pp. 267, 2004, ACM, 1-58113-936-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
binary visualization, multimedia logic, logic simulation, computer design |
24 | Vasily G. Moshnyaga |
Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(1-2), pp. 75-82, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
bit-truncation, low-power design, video processing, switching activity |
24 | Edwin A. Hakkennes, Stamatis Vassiliadis |
Multimedia Execution Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 28(3), pp. 221-234, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
multimedia architectures, multimedia instruction set, multimedia processors, compound instructions, multimedia, hardware accelerators, subword parallelism, SIMD processors, vector architectures |
24 | Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler |
A design space evaluation of grid processor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 40-51, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Narasimhan Ramasubramanian, Ram Subramanian, Santosh Pande |
Automatic Analysis of Loops to Exploit Operator Parallelism on Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 11th International Workshop, LCPC'98, Chapel Hill, NC, USA, August 7-9, 1998, Proceedings, pp. 305-322, 1998, Springer, 3-540-66426-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Hyunman Chang, Changhee Lee, Myung Hoon Sunwoo |
SliM-II: A Linear Array SIMD Processor for Real-time Image Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 11-13 December 1997, Seoul, Korea, Proceedings, pp. 132-137, 1997, IEEE Computer Society, 0-8186-8227-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
24 | David M. Dahle, Jeffrey D. Hirschberg, Kevin Karplus, Hansjörg Keller, Eric Rice, Don Speck, Douglas H. Williams, Richard Hughey |
Kestrel: Design of an 8-bit SIMD Parallel Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 17th Conference on Advanced Research in VLSI (ARVLSI '97), September 15-16, 1997, Ann Arbor, MI, USA, pp. 145-, 1997, IEEE Computer Society, 0-8186-7913-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
24 | Hyunman Chang, Soohwan Ong, Myung Hoon Sunwoo |
A Linear Array Parallel Image Processor: SliM-II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 34-41, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
24 | Suntae Hwang, Rochit Rajsuman, Yashwant K. Malaiya |
On the testing of microprogrammed processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 260-266, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
24 | Diederik Verkest, Luc J. M. Claesen, Hugo De Man |
Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 62-66, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
24 | T. R. N. Rao, Harry J. Reinheimer |
Fault-tolerant modularized arithmetic logic units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1977 National Computer Conference, June 13-16, 1977, Dallas, Texas, USA, pp. 703-710, 1977, AFIPS Press, 978-1-4503-7914-4. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
|
24 | William B. Langdon, Wolfgang Banzhaf |
Repeated patterns in genetic programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Nat. Comput. ![In: Nat. Comput. 7(4), pp. 589-613, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Genetic alogorithms, ALU, Macky-Glass, Poly-10, Nuclear protein localisation, Tiny GP, GPquick, Evolution of program shape, Sensitivity analysis, Frequent subgraphs, SINE, Frequent subtrees |
23 | Alan Marshall, Tony Stansfield, Igor Kostarnov, Jean Vuillemin, Brad L. Hutchings |
A Reconfigurable Arithmetic Array for Multimedia Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, FPGA 1999, Monterey, CA, USA, February 21-23, 1999, pp. 135-143, 1999, ACM, 1-58113-088-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
4-bit ALU, FPGA, multimedia, reconfigurable computing |
23 | Kazumi Hatayama, Kazunori Hikone, Takeshi Miyazaki, Hiromichi Yamada |
A practical approach to instruction-based test generation for functional modules of VLSI processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 17-23, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
VLSI processors, instruction-based test generation, functional test pattern generation, gate level faults, constrained test generation, ALU oriented test pattern generation system, VLSI, functional modules, ALPS |
23 | Waldo C. Kabat, Anthony S. Wojcik |
On the Design of 4-Valued Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(9), pp. 666-671, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
T-gate, 4-valued ALU, Post algebra, multivalued logic, Boolean algebra, digital system design |
21 | S. Senthilmurugan, K. Gunaseelan |
Performance Analysis of Multicore Processor Using FOFO-Based Approximate Compatible ALU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 33(4), pp. 2450062:1-2450062:19, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
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