Search results for "ATPG"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
92	Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja	Combinational automatic test pattern generation for acyclic sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
91	Suresh Kumar Devanathan, Michael L. Bushnell	Sequential Spectral ATPG Using the Wavelet Transform and Compaction.	VLSI Design	2006	DBLP DOI BibTeX RDF
87	Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri	SAT-based ATPG using multilevel compatible don't-cares.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Boolean satisfiabilty (SAT), testing, Automatic test pattern generation (ATPG), don't cares
87	Robert H. Klenke, James H. Aylor, Joseph M. Wolf	An analysis of fault partitioning algorithms for fault partitioned ATPG.	VTS	1996	DBLP DOI BibTeX RDF	fault partitioning algorithm, VLSI device, detected fault broadcasting, preprocessing time, parallel processing, parallel processing, VLSI, fault diagnosis, integrated circuit testing, ATPG, automatic testing, dynamic load balancing, NP complete problem, digital system, test vector generation
78	Kameshwar Chandrasekar, Michael S. Hsiao	Forward image computation with backtracing ATPG and incremental state-set construction.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	model checking, ATPG, image computation, ZBDDs
78	Mukul R. Prasad, Philip Chong, Kurt Keutzer	Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	combinational ATPG, SAT, backtracking, complexity analysis, VLSI circuits
74	Xinghao Chen 0003, Michael L. Bushnell	Sequential circuit test generation using dynamic justification equivalence.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	search decision spaces, test generation efficiency, automatic test pattern generation, stuck-at faults, justification
72	Liang Zhang 0012, Indradeep Ghosh, Michael S. Hsiao	A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
72	Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang	Efficient Boolean characteristic function for fast timed ATPG.	ICCAD	2006	DBLP DOI BibTeX RDF
72	Liang Zhang 0012, Indradeep Ghosh, Michael S. Hsiao	Efficient Sequential ATPG for Functional RTL Circuits.	ITC	2003	DBLP DOI BibTeX RDF
68	Stephan Eggersglüß, Rolf Drechsler	On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults.	ISMVL	2008	DBLP DOI BibTeX RDF	Boolean Encodings, ATPG, SAT, Path Delay Faults
68	Franco Fummi, Cristina Marconcini, Graziano Pravadelli	An EFSM-based approach for functional ATPG.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	ATPG, fault models, EFSM
64	Indradeep Ghosh	High Level Test Generation for Custom Hardware: An Industrial Perspective.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
63	Daniel Tille, Rolf Drechsler	A fast untestability proof for SAT-based ATPG.	DDECS	2009	DBLP DOI BibTeX RDF
63	Daniel Tille, Rolf Drechsler	Incremental SAT Instance Generation for SAT-based ATPG.	DDECS	2008	DBLP DOI BibTeX RDF
63	Chung-Yang Huang, Kwang-Ting Cheng	Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
63	Chung-Yang Huang, Kwang-Ting Cheng	Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques.	DAC	2000	DBLP DOI BibTeX RDF
63	Paul Tafertshofer, Andreas Ganz	SAT based ATPG using fast justification and propagation in the implication graph.	ICCAD	1999	DBLP DOI BibTeX RDF
60	Lech Józwiak	On the use of term trees for effective and efficient test pattern generation.	EUROMICRO	1997	DBLP DOI BibTeX RDF	term trees, structural automatic test pattern generation, fault discovery, structural fault model, term tree based ATPG algorithm, nonredundant faults, minimal test set, circuit redundancy, logic design, fault model, data representation, automatic test software
59	Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu	VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	combinational broadcaster, combinational compactor, fault diagnosis, ATPG, test compression, low-power testing, scan testing
59	M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor	Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume.	ITC	2002	DBLP DOI BibTeX RDF	compact test sets, ATPG, fault coverage, stuck-at faults, test length, Test point insertion, gate-delay faults
59	Peter Wohl, John A. Waicukauski	Using ATPG for clock rules checking in complex scan design.	VTS	1997	DBLP DOI BibTeX RDF	clock rules checking, complex scan designs, structured DFT, automated design-rules-checking, robust set of rules, clock-rule-violation detection, fast clock verification, large microprocessor design, topological circuit analysis, zero delay, user controlled verification, capture ability, port contention, cone tracing, equivalent sources, ATPG, race conditions, computer testing, timing verification
55	Paul Tafertshofer, Andreas Ganz, Kurt Antreich	IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
54	Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.	DFT	2008	DBLP DOI BibTeX RDF
54	Kai Yang, Kwang-Ting Cheng, Li-C. Wang	TranGen: a SAT-based ATPG for path-oriented transition faults.	ASP-DAC	2004	DBLP DOI BibTeX RDF
54	Debashis Nayak, Srikanth Venkataraman, Paul J. Thadikaran	Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application.	VTS	2004	DBLP DOI BibTeX RDF
54	Kameshwar Chandrasekar, Michael S. Hsiao	Decision Selection and Learning for an All-Solutions ATPG Engine.	ITC	2004	DBLP DOI BibTeX RDF
54	Vivekananda M. Vedula, Whitney J. Townsend, Jacob A. Abraham	Program Slicing for ATPG-Based Property Checking.	VLSI Design	2004	DBLP DOI BibTeX RDF
54	Rubin A. Parekhji	Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions.	VLSI Design	2003	DBLP DOI BibTeX RDF
54	Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng 0012, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir	Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.	ITC	2002	DBLP DOI BibTeX RDF
54	Tsuyoshi Shinogi, Tomokazu Kanbayashi, Tomohiro Yoshikawa, Shinji Tsuruoka, Terumine Hayashi	Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
54	Maria K. Michael, Spyros Tragoudas	ATPG for Path Delay Faults without Path Enumeration.	ISQED	2001	DBLP DOI BibTeX RDF
54	Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante	SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
54	Eugeni Isern 0001, Miquel Roca 0001, Jaume Segura 0001	Analyzing the Need for ATPG Targeting GOS Defects.	VTS	1999	DBLP DOI BibTeX RDF
54	Li-C. Wang, M. Ray Mercer, Thomas W. Williams	A Better ATPG Algorithm and Its Design Principles.	ICCD	1996	DBLP DOI BibTeX RDF
51	Hyoung B. Min, William A. Rogers	A test methodology for finite state machines using partial scan design.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	loop-free circuits, test generation, ATPG, fault, partial scan
50	Shuo Sheng, Koichiro Takayama, Michael S. Hsiao	Effective safety property checking using simulation-based sequential ATPG.	DAC	2002	DBLP DOI BibTeX RDF	sequential ATPG, simulation-based, verification
50	Jalal A. Wehbeh, Daniel G. Saab	Initialization of Sequential Circuits and its Application to ATPG.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	verification, CAD, ATPG, initialization
47	Wu-Tung Cheng	Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
46	Tiziana Gravagnoli, Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto	Automatic Test Pattern Generation with BOA.	PPSN	2006	DBLP DOI BibTeX RDF
45	Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille	On Acceleration of SAT-Based ATPG for Industrial Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
45	Franco Fummi, Graziano Pravadelli	Too Few or Too Many Properties? Measure it by ATPG!	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Property coverage, Property optimization, Model checking, Functional verification, Functional fault model
45	Görschwin Fey, Tim Warode, Rolf Drechsler	Reusing Learned Information in SAT-based ATPG.	VLSI Design	2007	DBLP DOI BibTeX RDF
45	Görschwin Fey, Junhao Shi, Rolf Drechsler	Efficiency of Multi-Valued Encoding in SAT-based ATPG.	ISMVL	2006	DBLP DOI BibTeX RDF
45	Qiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham	Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core.	ICCD	2005	DBLP DOI BibTeX RDF
45	Arkan Abdulrahman, Spyros Tragoudas	Compact ATPG for Concurrent SOC Testing.	MTV	2004	DBLP DOI BibTeX RDF
45	Shuo Sheng, Michael S. Hsiao	Efficient Preimage Computation Using A Novel Success-Driven ATPG.	DATE	2003	DBLP DOI BibTeX RDF
45	Liang Zhang 0012, Michael S. Hsiao, Indradeep Ghosh	Automatic Design Validation Framework for HDL Descriptions via RTL ATPG.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
45	Puneet Gupta, Michael S. Hsiao	High Quality ATPG for Delay Defects.	ITC	2003	DBLP DOI BibTeX RDF
45	Xiaoliang Bai, Sujit Dey, Angela Krstic	HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk.	ITC	2003	DBLP DOI BibTeX RDF
45	Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael R. Grimaila, M. Ray Mercer	A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults.	DATE	2002	DBLP DOI BibTeX RDF
45	Chih-Wei Jim Chang, Malgorzata Marek-Sadowska	ATPG-based logic synthesis: an overview.	ICCAD	2002	DBLP DOI BibTeX RDF
45	Mani Soma, Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg	Hierarchical ATPG for Analog Circuits and Systems.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
45	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero	High-Level Observability for Effective High-Level ATPG.	VTS	2000	DBLP DOI BibTeX RDF
45	Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunderlich	Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
45	Seongmoon Wang, Sandeep K. Gupta 0001	ATPG for Heat Dissipation Minimization During Scan Testing.	DAC	1997	DBLP DOI BibTeX RDF
45	Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell	On More Efficient Combinational ATPG Using Functional Learning.	VLSI Design	1996	DBLP DOI BibTeX RDF
45	Kwang-Ting Cheng, Hi-Keung Tony Ma	On the over-specification problem in sequential ATPG algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
42	Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor	Test-Pattern Grading and Pattern Selection for Small-Delay Defects.	VTS	2008	DBLP DOI BibTeX RDF	Small-delay defects, pattern grading, pattern selection, ATPG
42	Soumitra Bose	Modeling Custom Digital Circuits for Test.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	ATPG, fault simulation, logic simulation, switch-level modeling
42	Fei Li 0003, Lei He 0001, Kewal K. Saluja	Estimation of Maximum Power-Up Current.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	current estimation, ATPG algorithm, leakage reduction
42	Aarti Gupta, Pranav Ashar	Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking.	VLSI Design	1998	DBLP DOI BibTeX RDF	ATPG techniques, circuit similarity, formal verification, combinational circuits, Boolean satisfiability (SAT), combinational equivalence checking, Binary Decision Diagrams (BDDs)
42	Peter A. Krauss, Andreas Ganz, Kurt Antreich	Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	fault parallelism, search space parallelism, sequential circuits, ATPG
42	Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai	Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	CMOS bridging faults detection, ATPG system, built-in intermediate voltage sensing, BIFEST system, PODEM-like process, PPSFP-based process, logic monitoring, gate threshold ranges, Byzantine General's Command Problem, feedback bridging faults, parallel pattern single fault propagation, fault modelling, fault simulation, fault coverage, greedy algorithm, CMOS logic circuits
42	Xinli Gu	RT level testability-driven partitioning.	VTS	1995	DBLP DOI BibTeX RDF	testability-driven partitioning, RT level designs, hard-to-test points, testability analysis algorithm, normal mode, design function, test mode, acyclic partition, BIST technique, fault diagnosis, logic testing, built-in self test, integrated circuit testing, design for testability, ATPG, automatic testing, logic CAD, fault coverage, logic partitioning, test application time, data path, testability measurements, DFT techniques
41	Manoj Kumar Goparaju, Spyros Tragoudas	A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates.	VTS	2008	DBLP DOI BibTeX RDF	Weght defects, ATPG, Threshold logic, Parametric faults
41	Jeffrey E. Nelson, Jason G. Brown, Rao Desineni, R. D. (Shawn) Blanton	Multiple-detect ATPG based on physical neighborhoods.	DAC	2006	DBLP DOI BibTeX RDF	N-detect, multiple-detect, ATPG, defects, neighborhoods
41	Ronald P. Lajaunie, Michael S. Hsiao	An effective and efficient ATPG-based combinational equivalence checker.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	verification, ATPG, equivalence checking
41	Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas	Low power ATPG for path delay faults.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	low power, ATPG, path delay faults, PODEM
41	Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Genetic Algorithm, ATPG
41	Paul Tafertshofer, Andreas Ganz, Manfred Henftling	A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists.	ICCAD	1997	DBLP DOI BibTeX RDF	SAT-based implication engine, circuit clause description, efficient ATPG, implication evaluation, indirect implications, netlist optimization, structure based methods, graph algorithms, automatic testing, logic circuits, graph model, equivalence checking, implication graph
41	Salvador Mir, Marcelo Lubaszewski, Bernard Courtois	Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	analog ATPG, fault diagnosis, fault-based testing, analog BIST
41	Jalal A. Wehbeh, Daniel G. Saab	Initialization of sequential circuits and its application to ATPG.	VTS	1996	DBLP DOI BibTeX RDF	initialization sequence, X-value simulation, functional initializability, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, ATPG, automatic testing, integrated logic circuits, structural decomposition
41	Anne-Lise Courbis, Jean François Santucci	Pseudo-random behavioral ATPG.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	pseudo-random behavioral ATPG, fault diagnosis, logic testing, VHDL, automatic testing, hardware description languages
41	Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva	A portable ATPG tool for parallel and distributed systems.	VTS	1995	DBLP DOI BibTeX RDF	portable ATPG tool, memory critical problems, electronic CAD, code portability, PVM library, DEC Alpha AXP, genetic algorithms, genetic algorithm, distributed systems, parallel architectures, parallel architectures, logic testing, message passing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, logic CAD, parallel systems, software portability, message-passing libraries, CM-5
41	Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus	Improving topological ATPG with symbolic techniques.	VTS	1995	DBLP DOI BibTeX RDF	topological ATPG, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, network topology, automatic testing, fault coverage, binary decision diagrams, CPU time, critical areas, symbolic techniques
41	Don Sterba, Andy Halliday, Don McClean	ATPG and diagnostics for boards implementing boundary scan.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	1149.1, ATPG, diagnostics, boundary scan, JTAG
37	Loganathan Lingappan, Srivaths Ravi 0001, Niraj K. Jha	Satisfiability-based test generation for nonseparable RTL controller-datapath circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
37	Shweta Chary, Michael L. Bushnell	Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
37	Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram	Timing-based delay test for screening small delay defects.	DAC	2006	DBLP DOI BibTeX RDF	test generation, delay testing
37	Zhigang Jiang, Sandeep K. Gupta 0001	A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
37	Loganathan Lingappan, Srivaths Ravi 0001, Niraj K. Jha	Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach.	ICCD	2003	DBLP DOI BibTeX RDF
37	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays
37	Silvia Chiusano, Fulvio Corno, Paolo Prinetto	A Test Pattern Generation Algorithm Exploiting Behavioral Information.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
37	Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly	Behavior and testability preservation under the retiming transformation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
37	J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor	Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
37	Vivek Chickermane, Jaushin Lee, Janak H. Patel	Addressing design for testability at the architectural level.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
36	K.-W. Yeh, M.-F. Wu, J.-L. Huang	A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method.	ICA3PP	2009	DBLP DOI BibTeX RDF
36	Boxue Yin, Dong Xiang, Zhen Chen	New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets.	VLSI Design	2009	DBLP DOI BibTeX RDF
36	Franco Fummi, Cristina Marconcini, Graziano Pravadelli, Ian G. Harris	A CLP-Based Functional ATPG for Extended FSMs.	MTV	2007	DBLP DOI BibTeX RDF
36	Margrit R. Krug, Marcelo Lubaszewski, Marcelo de Souza Moraes	Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
36	Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli	FATE: a Functional ATPG to Traverse Unstabilized EFSMs.	ETS	2006	DBLP DOI BibTeX RDF
36	Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli	Improving Gate-Level ATPG by Traversing Concurrent EFSMs.	VTS	2006	DBLP DOI BibTeX RDF
36	Qiang Qiang, Daniel G. Saab, Jacob A. Abraham	Checking Nested Properties Using Bounded Model Checking and Sequential ATPG.	VLSI Design	2006	DBLP DOI BibTeX RDF
36	Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli	A Pseudo-Deterministic Functional ATPG based on EFSM Traversing.	MTV	2005	DBLP DOI BibTeX RDF
36	Ahmad A. Al-Yamani, Edward J. McCluskey	BIST-Guided ATPG.	ISQED	2005	DBLP DOI BibTeX RDF
36	B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal	A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
36	Shuo Sheng, Michael S. Hsiao	Success-Driven Learning in ATPG for Preimage Computation.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
36	M. Enamul Amyeen, Srikanth Venkataraman, Ajay Ojha, Sangbong Lee	Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor.	ITC	2004	DBLP DOI BibTeX RDF
36	Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain	Can SAT be used to Improve Sequential ATPG Methods?	VLSI Design	2004	DBLP DOI BibTeX RDF