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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 18148 publication records. Showing 18148 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
62 | Georgios Theodoropoulos 0001, J. V. Woods |
Simulating Asynchronous Architectures on Transputer Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 274-281, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
asynchronous architecture simulation, asynchronous design techniques, clock related timing problems, CSP based parallel language, asynchronous architectural simulation models, parallel architectures, logic design, asynchronous circuits, circuit analysis computing, parallel languages, Occam, Occam, asynchronous logic, transputer systems, transputer networks |
53 | Alexandre Yakovlev, A. I. Petrov, Leonid Ya. Rosenblum |
Synthesis of Asynchronous Control Circuits from Symbolic Signal Transition Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 71-85, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
53 | Meng-Lin Yu, P. A. Subrahmanyam |
Hazard-Free Asynchronous Circuit Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 87-105, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
53 | Al Davis, Bill Coates 0001, Ken Stevens |
Automatic Synthesis of Fast Compact Asynchronous Control Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 193-207, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
53 | Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
Automated Synthesis of Asynchronous Interface Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 107-121, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
53 | Jim D. Garside |
A CMOS VLSI Implementation of an Asynchronous ALU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 181-192, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
53 | Kees van Berkel 0001, Ronan Burgess, Joep L. W. Kessels, Marly Roncken, Frits D. Schalij |
Characterization and Evaluation of a Compiled Asynchronous IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 209-221, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
53 | Jaco Haans, Kees van Berkel 0001, Ad M. G. Peeters, Frits D. Schalij |
Asynchronous Multipliers as Combinational Handshake Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 149-163, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
49 | Martin Simlastík, Viera Stopjaková |
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 348-358, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Asynchronous Digital Circuits, Self-time Digital Circuits, Synchronous-to-asynchronous Conversion, DLAP, De-synchronization, Phased Logic, LEDR, Low Power, Null Convention Logic, SADT |
49 | Octavian Petre, Hans G. Kerkhoff |
Scan Test Strategy for Asynchronous-Synchronous Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(6), pp. 639-645, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
globally asynchronous locally synchronous (GALS), asynchronous synchronous interface, synchronizers, scan test |
48 | Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Son Jhang, Jeong-A Lee, Dong-Soo Har |
Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 46(2-3), pp. 133-151, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multiple outstanding transactions, in-order/out-of-order transaction completion, asynchronous on-chip bus, GALS |
48 | Rik van de Wiel |
High-level test evaluation of asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 63-71, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high-level test evaluation, production fault tests, high-level circuit description, asynchronous 22 k transistor DCC error corrector IC, VLSI, logic testing, fault model, asynchronous circuits, asynchronous circuits, error detection codes |
48 | Joep L. W. Kessels |
VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 44-52, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
digital audio tape, VLSI programming, low-power asynchronous Reed-Solomon decoder, DCC player, Tangram, minimal power dissipation, low-power cost-effective design, VLSI, logic programming, power consumption, power consumption, asynchronous circuits, asynchronous circuit, decoding, Reed-Solomon codes |
48 | Jelio Todorov Yantchev, C. G. Huang, Mark B. Josephs, Ivailo M. Nedelchev |
Low-latency asynchronous FIFO buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 24-31, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
buffer circuits, low-latency asynchronous FIFO buffers, parallel asynchronous implementation, interface circuitry, inter-chip communication wires, acknowledge signal, high-throughput multiple-burst signalling scheme, packet switching, asynchronous circuits, pipeline processing, propagation delay |
46 | Venkatesh Akella, Ganesh Gopalakrishnan |
Specification and Validation of Control-Intensive IC's in hopCP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 20(6), pp. 405-423, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
control-intensive integrated circuits, hopCP, asynchronous operations, multiple concurrent threads, Intel 8251, Universal Synchronous/Asynchronous Receiver/Transmitter, USART, synchronous message passing, distributed shared variables, asynchronous ports, compiled-code concurrent functional simulator, CFSIM, formal specification, formal methods, formal verification, specification, validation, message passing, specification languages, interrupt, digital simulation, hardware description language, microprocessor chips, hardware design, polling, computational requirements, synchronous operations |
46 | Stephen B. Furber, Martyn Edwards (eds.) |
Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993 ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![North-Holland, 0-444-81599-6 The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
46 | Ilana David, Ran Ginosar, Michael Yoeli |
Self-Timed Architecture of a Reduced Instruction Set Computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 29-43, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
46 | Marly Roncken, Ronald Saeijs |
Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 13-27, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
46 | O. Salomon, Heinrich Klar |
Self-Timed Fully Pipelined Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 45-55, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
46 | Jo C. Ebergen, P. F. Bertrand, S. Gingras |
Solving a Mutual Exclusion Problem with the RGD Arbiter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 137-147, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
46 | Mark B. Josephs, Jan Tijmen Udding |
Implementing a Stack as a Delay-insensitive Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 123-135, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
46 | Jens Sparsø, Christian D. Nielsen, Lars Skovby Nielsen, Jørgen Staunstrup |
Design of Self-timed Multipliers: A Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 165-179, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
46 | Rix Groenboom, Mark B. Josephs, Paul G. Lucassen, Jan Tijmen Udding |
Normal Form in a Delay-Insensitive Algebra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 57-70, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
46 | Kees van Berkel 0001 |
VLSI Programming of a Modulo-N Counter with Constant Response Time and Constant Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 1-11, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
44 | Pierre Ganty, Rupak Majumdar, Andrey Rybalchenko |
Verifying liveness for asynchronous programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Proceedings of the 36th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2009, Savannah, GA, USA, January 21-23, 2009, pp. 102-113, 2009, ACM, 978-1-60558-379-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
asynchronous (event-driven) programming, fair termination, petri nets, liveness |
44 | Lilian Janin, Doug Edwards |
Software Visualisation Techniques Adapted and Extended for Asynchronous Hardware Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IV ![In: 9th International Conference on Information Visualisation, IV 2005, 6-8 July 2005, London, UK, pp. 347-356, 2005, IEEE Computer Society, 0-7695-2397-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
program comprehension, asynchronous circuits, Software visualisation, coordinated views |
44 | Daranee Hormdee, Jim D. Garside, Stephen B. Furber |
An Asynchronous Victim Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 4-11, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
copy-back cache architecture, asynchronous design, victim cache |
44 | Rida A. Bazzi |
Access cost for asynchronous Byzantine quorum systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 14(1), pp. 41-48, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Access cost, Fault tolerance, Distributed systems, Asynchronous, Quorum, Byzantine failures |
44 | Rida A. Bazzi |
Non-blocking Asynchronous Byzantine Quorum Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DISC ![In: Distributed Computing, 13th International Symposium, Bratislava, Slovak Republic, September 27-29, 1999, Proceedings, pp. 109-122, 1999, Springer, 3-540-66531-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
access cost, distributed, asynchronous, failures, quorum, tolerance, Byzantine |
44 | Craig Farnsworth, David A. Edwards, Jianwei Liu, Shiv S. Sikand |
A hybrid asynchronous system design environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 91-98, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
hybrid asynchronous system design environment, hybrid design scheme, asynchronous circuit synthesis, Tangram silicon complier, synchronous design techniques, concurrency, high level synthesis, asynchronous circuits, power reduction, performance gains, micropipelines |
44 | Chantal Ykman-Couvreur, Bill Lin 0001 |
Optimised state assignment for asynchronous circuit synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 118-127, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimised state assignment, asynchronous circuit synthesis, complete state coding, state graph level, asynchronous benchmarks, circuit area, logic design, encoding, asynchronous circuits, computation time, state assignment |
44 | David A. Kearney, Neil W. Bergmann |
Performance evaluation of asynchronous logic pipelines with data dependent processing delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 4-13, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous logic pipelines, data dependent processing delays, logic stages, data dependent delay, two valued random variable, performance evaluation, performance evaluation, asynchronous circuits, pipeline processing, latches |
43 | Mathew A. Sacker, Andrew D. Brown, Peter R. Wilson, Andrew J. Rushton |
A General Purpose Behavioural Asynchronous Synthesis System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 125-134, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Behavioural synthesis, asynchronous synthesis, cryptography |
43 | Joep L. W. Kessels, Paul Marston |
Designing Asynchronous Standby Circuits for a Low-Power Pager. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 268-278, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
pager, loadable counter, synchronous/asynchronous, low-power, co-design |
43 | Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, Paul Day, N. C. Paver |
AMULET2e: An Asynchronous Embedded Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 290-, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Low power, Microprocessors, Asynchronous design, Embedded control |
42 | Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri |
CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 62-72, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits |
42 | Thierry Chich, Pierre Fraigniaud |
An extended comparison of slotted and unslotted deflection routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the International Conference On Computer Communications and Networks (ICCCN 1997), September 22-25, 1997 Las Vegas, NV, USA, pp. 92-97, 1997, IEEE Computer Society, 0-8186-8186-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
slotted deflection routing, unslotted deflection routing, synchronized all-optical deflection networks, asynchronous all-optical deflection networks, synchronous mode, partially synchronous mode, asynchronous mode, fixed packet sizes, bound packet sizes, performances, design, cost, telecommunication network routing, bursty traffic |
41 | Chantal Ykman-Couvreur, Bill Lin 0001 |
Efficient state assignment framework for asynchronous state graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 692-697, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
state assignment framework, asynchronous state graphs, state graph level, complete state coding problem, circuit area, logic design, encoding, asynchronous circuits, asynchronous circuits, computation time, state assignment |
41 | Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach |
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 149-158, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous |
41 | Alain Girault, Clément Ménier |
Automatic Production of Globally Asynchronous Locally Synchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Embedded Software, Second International Conference, EMSOFT 2002, Grenoble, France, October 7-9, 2002, Proceedings, pp. 266-281, 2002, Springer, 3-540-44307-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Globally synchronous-locally asynchronous (GALS), asynchronous communications, hardware/software codesign, distributed architectures, synchronous circuits, automatic distribution |
40 | José Manuel Colmenar, Noelia Morón, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo |
Modelling Asynchronous Systems using Probability Distribution Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 16th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2008), 13-15 February 2008, Toulouse, France, pp. 3-11, 2008, IEEE Computer Society, 978-0-7695-3089-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
modelling, asynchronous, microarchitecture |
40 | Gaurav Gulati, Erik Brunvand |
Design of a cell library for asynchronous microengines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 385-389, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CMOS cell library, microprogramed control, asynchronous control, self-timed systems |
40 | John Teifel, Rajit Manohar |
An Asynchronous Dataflow FPGA Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(11), pp. 1376-1392, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Asynchronous/synchronous operation, reconfigurable hardware, gate arrays, dataflow architectures |
40 | Lu Jun, Xianliang Lu, Han Hong, Qingsong Wei |
A cooperative asynchronous write mechanism for NAS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGOPS Oper. Syst. Rev. ![In: ACM SIGOPS Oper. Syst. Rev. 36(3), pp. 25-32, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
performance, cache, cooperation, asynchronous, write, NAS |
40 | Hans M. Jacobson, Ganesh Gopalakrishnan |
Asynchronous Microengines for Efficient High-level Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 17th Conference on Advanced Research in VLSI (ARVLSI '97), September 15-16, 1997, Ann Arbor, MI, USA, pp. 201-218, 1997, IEEE Computer Society, 0-8186-7913-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
asynchronous circuits, microprogramming, self-timing |
40 | Jing Wang |
Asynchronous Computing and Communication Architecture Toward Energy Efficient Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PerCom ![In: Seventh Annual IEEE International Conference on Pervasive Computing and Communications, PerCom 2009, 9-13 March 2009, Galveston, TX, USA, pp. 1-2, 2009, IEEE Computer Society, 978-1-4244-3304-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
40 | Morteza Damavandpeyma, Siamak Mohammadi |
Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 857-864, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
40 | C. J. Elston, D. B. Christianson, Paul A. Findlay, Gordon B. Steven |
Hades-towards the design of an asynchronous superscalar processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 200-209, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous superscalar processor, Hades, generic processor architecture, asynchronous processor design, decoupled operand forwarding, register writeback, computer architecture, logic design |
40 | Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu |
ARAS: asynchronous RISC architecture simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 210-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous RISC architecture simulator, ARAS, pipeline instruction simulator, benchmark programs, pipeline configuration, asynchronous pipeline architectures, performance evaluation, parallel architectures, virtual machines, performance measurements, pipeline processing |
39 | Joep L. W. Kessels, Gerrit den Besten, Ad M. G. Peeters, Torsten Kramer, Volker Timm |
Applying Asynchronous Circuits in Contactless Smart Cards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 36-44, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power asynchronous circuits, contactless devices, DES cryptography, smart cards |
39 | Romain Beauxis, Catuscia Palamidessi, Frank D. Valencia |
On the Asynchronous Nature of the Asynchronous pi-Calculus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurrency, Graphs and Models ![In: Concurrency, Graphs and Models, Essays Dedicated to Ugo Montanari on the Occasion of His 65th Birthday, pp. 473-492, 2008, Springer, 978-3-540-68676-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Mikio Aoyama, Akira Mori |
A Unified Design Method of Asynchronous Service-Oriented Architecture Based on the Models and Patterns of Asynchronous Message Exchanges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICWS ![In: 2008 IEEE International Conference on Web Services (ICWS 2008), September 23-26, 2008, Beijing, China, pp. 537-544, 2008, IEEE Computer Society, 978-0-7695-3310-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet |
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 295-306, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Ionel Muscalagiu, Hong Jiang, Horia Emil Popa |
Implementation and Evaluation Model for the Asynchronous Search Techniques: From a Synchronously Distributed System to an Asynchronous Distributed System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SYNASC ![In: 8th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing (SYNASC 2006), 26-29 September 2006, Timisoara, Romania, pp. 209-216, 2006, IEEE Computer Society, 0-7695-2740-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Dietrich Kuske |
Asynchronous Cellular Automata and Asynchronous Automata for Pomsets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONCUR ![In: CONCUR '98: Concurrency Theory, 9th International Conference, Nice, France, September 8-11, 1998, Proceedings, pp. 517-532, 1998, Springer, 3-540-64896-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
38 | Seokjin Kim, Ramalingam Sridhar |
A local clocking approach for self-timed datapath designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 152-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits |
37 | Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt |
A new method for asynchronous pipeline control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA, pp. 100-104, 1997, IEEE Computer Society, 0-8186-7904-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
asynchronous pipeline control, static logic control, dynamic logic control, flow controlled asynchronous method, asynchronous circuits, VLSI architecture |
37 | R. S. Hogg, W. I. Hughes, David W. Lloyd |
A Novel Asynchronous ALU for Massively Parallel Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 282-289, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit |
37 | Karl M. Fant, Scott A. Brandt |
NULL Convention LogicTM: A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 261-273, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
consistent logic, asynchronous digital circuit synthesis, symbolically complete logic, asynchronous digital circuits, asynchronous circuits, multivalued logic, three value logic, Boolean logic, NULL Convention Logic, four value logic |
37 | Robert M. Fuhrer, Bill Lin 0001, Steven M. Nowick |
Algorithms for the optimal state assignment of asynchronous state machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 59-75, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimal state assignment, asynchronous state machines, state codes, race-free state assignment, hazard-free state assignment, input encoding problem, sum-of-products implementations, finite state machines, asynchronous circuits, state assignment, minimisation of switching nets, hazards and race conditions, asynchronous sequential logic |
37 | O. A. Petlin, Stephen B. Furber |
Scan testing of asynchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 224-229, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits |
37 | Jerry Zhigang Li, Sharon Elizabeth Bratt |
Activity Theory as Tool for Analyzing Asynchronous Learning Networks (ALN). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICWL ![In: Advances in Web-Based Learning - ICWL 2004, Third International Conference, Beijing, China, August 8-11, 2004, Proceedings, pp. 19-26, 2004, Springer, 3-540-22542-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
online conference, E-learning, computer-mediated communication, Asynchronous communication, activity theory, instructional design, web-based learning, online discussion, Asynchronous Learning Networks |
37 | Atanu Chattopadhyay, Zeljko Zilic |
A globally asynchronous locally dynamic system for ASICs and SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 176-181, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
all-digital clock generation, dynamic clock manager, globally asynchronous locally synchronous system, asynchronous design |
37 | François Verdier, Alain Mérigot, Bertrand Y. Zavidovique |
Fast Stable Matching Algorithm using Asynchronous Parallel Programming Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 131-135, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fast stable matching algorithm, asynchronous parallel programming model, stable marriage algorithm, massively parallel asynchronous model, asynchronously communicating processors, image processing problem, image processing, 3D reconstruction, image matching, database search |
37 | Michael J. Liebelt, Cheng-Chew Lim |
A method for determining whether asynchronous circuits are self-checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 472-477, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise |
37 | Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy |
Fsimac: a fault simulator for asynchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 114-119, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits |
37 | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama |
Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 18-20 December 2000, Los Angeles, CA, USA, pp. 27-36, 2000, IEEE Computer Society, 0-7695-0975-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits |
37 | Sridhar Narayanan, Melvin A. Breuer |
Asynchronous multiple scan chain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 270-276, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous multiple scan chains, scan flip-flops, control complexity, I/O pin count, DFT method, logic IC, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, flip-flops, integrated logic circuits, scan designs, boundary scan testing, test application time |
36 | Zuzana Beerliová-Trubíniová, Martin Hirt, Jesper Buus Nielsen |
On the theoretical gap between synchronous and asynchronous MPC protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the 29th Annual ACM Symposium on Principles of Distributed Computing, PODC 2010, Zurich, Switzerland, July 25-28, 2010, pp. 211-218, 2010, ACM, 978-1-60558-888-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
cryptography, multi-party computation, asynchronous network, mpc |
36 | Chun Sing Louis Tsui, John Q. Gan |
Asynchronous BCI Control of a Robot Simulator with Supervised Online Training. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDEAL ![In: Intelligent Data Engineering and Automated Learning - IDEAL 2007, 8th International Conference, Birmingham, UK, December 16-19, 2007, Proceedings, pp. 125-134, 2007, Springer, 978-3-540-77225-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
asynchronous BCI, automated learning, Adaptation, brain-computer interface, online training |
36 | Prakash Chandrasekaran, Christopher L. Conway, Joseph M. Joy, Sriram K. Rajamani |
Programming asynchronous layers with CLARITY. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESEC/SIGSOFT FSE ![In: Proceedings of the 6th joint meeting of the European Software Engineering Conference and the ACM SIGSOFT International Symposium on Foundations of Software Engineering, 2007, Dubrovnik, Croatia, September 3-7, 2007, pp. 65-74, 2007, ACM, 978-1-59593-811-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
asynchronous components, design for analyzability, concurrency, static analysis, event-driven programming |
36 | Yoshihiro Nakaminami, Toshimitsu Masuzawa, Ted Herman |
A Method for Evaluating Efficiency of Protocols on the Asynchronous Shared-State Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Self-Stabilizing Systems ![In: Self-Stabilizing Systems, 6th International Symposium, SSS 2003, San Francisco, CA, USA, June 24-25, 2003, Proceedings, pp. 141-153, 2003, Springer, 3-540-40453-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
asynchronous model, synchronous execution, linear state-transition protocol, Distributed system, distributed algorithm, time complexity |
36 | Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor |
Security Evaluation of Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2003, 5th International Workshop, Cologne, Germany, September 8-10, 2003, Proceedings, pp. 137-151, 2003, Springer, 3-540-40833-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Dual-Rail encoding, EMA, Design-time security evaluation, Asynchronous circuits, Power Analysis, Fault Analysis |
36 | Yosi Ben-Asher, Esti Stein |
Basic Algorithms for the Asynchronous Reconfigurable Mes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
APRAM, Asynchronous, Reconfigurable mesh |
36 | Michel Hurfin, Michel Raynal |
A Simple and Fast Asynchronous Consensus Protocol Based on a Weak Failure Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 12(4), pp. 209-223, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Fault-tolerance, Asynchronous distributed systems, Crash failures, Unreliable failure detectors, Consensus problem |
36 | Mohsen Raji, Behnam Ghavami, Hossein Pedram |
Statistical static performance analysis of asynchronous circuits considering process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 291-296, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Kenneth Y. Yun |
Recent Advances in Asynchronous Design Methodologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 253-, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Jun Gu, Ruchir Puri |
Asynchronous circuit synthesis with Boolean satisfiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8), pp. 961-973, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
36 | Marc Renaudin, Pascal Vivet, Frédéric Robin |
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 22-31, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design |
36 | Eckhard Grass, Simon Jones |
Asynchronous circuits based on multiple localised current-sensing completion detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 170-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
dual rail coding, Current-Sensing Completion Detection, Current-Sensing Circuits, logic design, power consumption, asynchronous circuits, asynchronous circuits, granularity, parallel multiplier, BiCMOS |
36 | Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt |
ECSTAC: a fast asynchronous microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 180-189, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous microprocessor, ECSTAC, two-phase communication, processor pipeline, register tagging, branch techniques, block simulation, caches, logic design, asynchronous circuits, microprocessor chips |
36 | Alexandre Yakovlev, Victor Varshavsky, Vyacheslav Marakhovsky, Alexei L. Semenov |
Designing an asynchronous pipeline token ring interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 32-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous pipeline token ring interface, speed-independent interface, reliable communication medium, on-board multicomputer, asynchronous buses, point-to-point interconnections, syntax-driven implementation, channel protocol controller, protocols, fairness, multiprocessor interconnection networks, local area networks, pipeline processing, deadlock-freedom, token networks |
35 | Amy Streich, Alex Kondratyev, Lief Sorensen |
Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 171-180, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
ATPG, asynchronous circuits, stuck-at faults, partial scan |
35 | José A. Tierno, Sergey V. Rylov, Alexander V. Rylyakov, Montek Singh, Steven M. Nowick |
An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 84-95, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
PRML read channel, magnetic recording, asynchronous pipeline, digital arithmetic, FIR filter, dynamic logic, high-throughput, low-latency, distributed arithmetic, mixed timing |
35 | Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken |
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 73-, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing |
35 | Kåre Tais Christensen, Peter Jensen, Peter Korger, Jens Sparsø |
The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 108-, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Asynchronous circuits and systems, low-power, microprocessor design |
35 | W. J. Bainbridge, Stephen B. Furber |
Asynchronous Macrocell Interconnect using MARBLE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 122-132, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Macrocell Bus, VLSI, Interconnect, Asynchronous |
35 | Ross Smith, Karl Fant, Dave Parker, Rick Stephani, Ching-Yi Wang |
An Asynchronous 2-D Discrete Cosine Transform Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 224-, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
DCT, asynchronous, threshold logic, bit-serial |
35 | D. J. Kinniment, Alexandre Yakovlev, Fei Xia, B. Gao |
Towards Asynchronous A-D Conversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 206-215, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
analogue to digital conversion, synchronisers, asynchronous circuits, arbitration, signal transition graphs, metastability |
35 | Cheoljoo Jeong, Steven M. Nowick |
Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 128-137, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Hans M. Jacobson, Erik Brunvand, Ganesh Gopalakrishnan, Prabhakar Kudva |
High-Level Asynchronous System Design Using the ACK Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 93-103, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Garth Baulch, David Hemmendinger, Cherrice Traver |
Analyzing and verifying locally clocked circuits with the concurrency workbench. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 144-147, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
locally clocked circuits, concurrency workbench, synchronous computational elements, concurrent system modelling, CCS process algebra, formal verification, timing, logic design, process algebra, logic CAD, asynchronous circuits, asynchronous circuits, circuit analysis computing, asynchronous communication |
33 | Anthony J. McAuley |
Four State Asynchronous Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(2), pp. 129-142, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
four state asynchronous architectures, asynchronous wavefront array, one-dimensional multipliers, two-dimensional sorter, reliability, throughput, sequential circuits, many-valued logics, design complexity, asynchronous sequential logic |
33 | Weiguo Wang |
An Asynchronous Two-Dimensional Self-Correcting Cellular Automaton ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 32nd Annual Symposium on Foundations of Computer Science, San Juan, Puerto Rico, 1-4 October 1991, pp. 278-285, 1991, IEEE Computer Society, 0-8186-2445-0. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
fault-free global synchronization clock, asynchronous two-dimensional self-correcting cellular automaton, arbitrary size, homogeneous asynchronous array, asynchronous environment, reliability, probability, reliable computation |
33 | Leonard R. Marino |
The Effect of Asynchronous Inputs on Sequential Network Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 26(11), pp. 1082-1090, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
Asynchronous arbiter, asynchronous sequential networks, flip-flop oscillations, inertial delay, input synchronization, metastable state, Schmitt trigger, synchronous sequential networks, reliability, asynchronous interactions |
33 | Achour Mostéfaoui, Sergio Rajsbaum, Michel Raynal |
Synchronous condition-based consensus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 18(5), pp. 325-343, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Early deciding, Consensus, Input vector, Synchronous distributed system, Process crash failure |
33 | Sufian Sudeng, Arthit Thongtak |
Template Based: A Novel STG Based Logic Synthesis for Asynchronous Control Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
World Congress on Engineering (Selected Papers) ![In: Advances in Electrical Engineering and Computational Science, [revised and extended papers from the World Congress on Engineering, WCE 2008, London, UK, July 2-4, 2008], pp. 59-74, 2008, Springer, 978-90-481-2310-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
asynchronous control circuits, asynchronous DMA controller, template based technique, logic synthesis, Signal Transition Graph (STG) |
33 | Christof Fetzer |
Perfect Failure Detection in Timed Asynchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(2), pp. 99-112, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Perfect failure detection, timed asynchronous system model, asynchronous distributed systems, crash failures |
33 | Victor Varshavsky, Vyacheslav Marakhovsky |
GALA Approach in Design of Asynchronous Control for Counterflow Pipeline Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 73-80, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
GALA - Globally Asynchronous Locally Arbitrary, Counterflow Pipeline Processor, Synchronous Prototype, Arbitration, Asynchronous Design |
33 | Donna Dufner, Ojoung Kwon, William Rogers |
Enriching Asynchronous Learning Networks through the Provision of Virtual Collaborative Learning Spaces: A Research Pilot. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 34th Annual Hawaii International Conference on System Sciences (HICSS-34), January 3-6, 2001, Maui, Hawaii, USA, 2001, IEEE Computer Society, 0-7695-0981-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Virtual Workgroup Environment, Web-enabled GDSS, Cooperative Document Production, Asynchronous Mode of Communication, Collaborative Learning, Distance Learning, Online Learning, Cooperative Learning, Collaboratories, Asynchronous Learning Networks |
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