Search results for "Chip-multiprocessors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
85	Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan	Compiler directed network-on-chip reliability enhancement for chip multiprocessors.	LCTES	2010	DBLP DOI BibTeX RDF	reliability, compiler, noc, chip multiprocessors
71	Noel Eisley, Li-Shiuan Peh, Li Shang	Leveraging on-chip networks for data cache migration in chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	network-driven computing, interconnection network, CMP, chip-multiprocessor, migration
70	Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin	Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	data compression, chip multiprocessors, optimizing compiler
67	Chris R. Jesshope	muTC - An Intermediate Language for Programming Chip Multiprocessors.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Self-adaptive computing, data-driven com-putation, programming chip multiprocessors, concurrent languages
56	Hemayet Hossain, Sandhya Dwarkadas, Michael C. Huang 0001	Improving support for locality and fine-grain sharing in chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	ARMCO, L1-to-L1 direct access, fine-grain sharing, chip multiprocessors, cache coherence
53	Hyunhee Kim, Jung Ho Ahn, Jihong Kim 0001	Replication-aware leakage management in chip multiprocessors with private L2 cache.	ISLPED	2010	DBLP DOI BibTeX RDF	leakage power management, chip multiprocessors, L2 caches
53	Jinglei Wang, Dongsheng Wang 0002, Yibo Xue, Haixia Wang 0001	An Efficient Lightweight Shared Cache Design for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	Directory-based Cache Coherence Protocol, Lightweight Shared Cache, Chip Multiprocessors (CMP)
53	Seung Woo Son 0001, Mahmut T. Kandemir, Mustafa Karaköy, Dhruva R. Chakrabarti	A compiler-directed data prefetching scheme for chip multiprocessors.	PPoPP	2009	DBLP DOI BibTeX RDF	compiler, chip multiprocessors, prefetching, helper thread
53	Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni	Design Exploration of Optical Interconnection Networks for Chip Multiprocessors.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Networks-on-Chip, Interconnection, Chip Multiprocessors, Optics
50	Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Ozcan Ozturk 0001	An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors.	ISCIS	2006	DBLP DOI BibTeX RDF	Reliability, DVS, energy minimization, duplication, heterogeneous chip multiprocessors
50	Rakesh Kumar 0002, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan	Heterogeneous Chip Multiprocessors.	Computer	2005	DBLP DOI BibTeX RDF	Multicore microprocessors, Multiprocessors, Chip multiprocessors, CMP, Heterogeneity, System architectures, Power-aware computing
50	Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir	Optimizing Bus Energy Consumption of On-Chip Multiprocessors Using Frequent Values.	PDP	2004	DBLP DOI BibTeX RDF	On-chip Multiprocessors, Power Optimization, Value Locality
50	Vasileios Liaskovitis, Shimin Chen, Phillip B. Gibbons, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Michael Kozuch, Todd C. Mowry, Chris Wilkerson	Parallel depth first vs. work stealing schedulers on CMP architectures.	SPAA	2006	DBLP DOI BibTeX RDF	scheduling, caches, chip multiprocessors
50	Naraig Manjikian, Huang Jin, James Reed, Nathan Cordeiro	Architecture and Implementation of Chip Multiprocessors: Custom Logic Components and Software for Rapid Prototyping.	ICPP	2004	DBLP DOI BibTeX RDF
49	Shirish Bahirat, Sudeep Pasricha	Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	photonic interconnect, network-on-chip, chip multiprocessor
49	Assaf Shacham, Keren Bergman, Luca P. Carloni	Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
47	Ayse K. Coskun, Richard D. Strong, Dean M. Tullsen, Tajana Simunic Rosing	Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors.	SIGMETRICS/Performance	2009	DBLP DOI BibTeX RDF	reliability, chip multiprocessors, thermal management, simulation methodology
47	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Utilizing shared data in chip multiprocessors with the nahalal architecture.	SPAA	2008	DBLP DOI BibTeX RDF	chip multiprocessors, cache memories
47	Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-Hsin S. Lee	Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	MESI protocol, internal and external snoops, self-modifying code, chip multiprocessors
47	Rakesh Kumar 0002, Dean M. Tullsen, Norman P. Jouppi	Core architecture optimization for heterogeneous chip multiprocessors.	PACT	2006	DBLP DOI BibTeX RDF	computer architecture, multi-core architectures, heterogeneous chip multiprocessors
47	Yu Zhang, Alex K. Jones	Non-uniform fat-meshes for chip multiprocessors.	IPDPS	2009	DBLP DOI BibTeX RDF
47	Feng Liu, Vipin Chaudhary	Extending OpenMP for Heterogeneous Chip Multiprocessors.	ICPP	2003	DBLP DOI BibTeX RDF
46	Ozcan Ozturk 0001, Mahmut T. Kandemir, G. Chen, Mary Jane Irwin, Mustafa Karaköy	Customized on-chip memories for embedded chip multiprocessors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
46	Evan Speight, Hazim Shafi, Lixin Zhang 0002, Ramakrishnan Rajamony	Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors.	ISCA	2005	DBLP DOI BibTeX RDF
44	Mahmut T. Kandemir, Ozcan Ozturk 0001, Mustafa Karaköy	Dynamic on-chip memory management for chip multiprocessors.	CASES	2004	DBLP DOI BibTeX RDF	chip multiprocessors, optimizing compiler, memory bank
44	Wan-Yu Lee, Iris Hui-Ru Jiang	VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	chip-multiprocessor, process variation, monte carlo analysis
44	Ozcan Ozturk 0001, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy	An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors.	ISVLSI	2006	DBLP DOI BibTeX RDF
44	Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Martonosi, Douglas W. Clark	Coordinated, distributed, formal energy management of chip multiprocessors.	ISLPED	2005	DBLP DOI BibTeX RDF	power, dynamic voltage scaling
43	Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun	Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors.	ICPADS (1)	2006	DBLP DOI BibTeX RDF
43	Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Mustafa Karaköy, Mary Jane Irwin	Integrated code and data placement in two-dimensional mesh based chip multiprocessors.	ICCAD	2008	DBLP DOI BibTeX RDF
43	Alaa R. Alameldeen, David A. Wood 0001	Interactions Between Compression and Prefetching in Chip Multiprocessors.	HPCA	2007	DBLP DOI BibTeX RDF
42	Jeffery A. Brown, Rakesh Kumar 0002, Dean M. Tullsen	Proximity-aware directory-based coherence for multi-core processor architectures.	SPAA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, coherence
42	Ozcan Ozturk 0001, Guilin Chen, Mahmut T. Kandemir	Optimizing code parallelization through a constraint network based approach.	DAC	2006	DBLP DOI BibTeX RDF	compiler, constraint network, chip multiprocessing
40	Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
40	Yefu Wang, Kai Ma, Xiaorui Wang	Temperature-constrained power control for chip multiprocessors with online model estimation.	ISCA	2009	DBLP DOI BibTeX RDF	power management, chip multiprocessor, feedback control
38	Sungjune Youn, Hyunhee Kim, Jihong Kim 0001	A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches.	ISLPED	2007	DBLP DOI BibTeX RDF	chip multiprocessors (CMPS), performance, embedded systems, architecture, low-power, L2 cache
38	Anne Benoit, Paul Renaud-Goud, Yves Robert, Rami G. Melhem	Energy-Aware Mappings of Series-Parallel Workflows onto Chip Multiprocessors.	ICPP	2011	DBLP DOI BibTeX RDF	power consumption minimization, chip multiprocessors, scheduling algorithms, series-parallel graphs
38	Dai N. Bui, Hiren D. Patel, Edward A. Lee	Deploying Hard Real-Time Control Software on Chip-Multiprocessors.	RTCSA	2010	DBLP DOI BibTeX RDF	Chip-multiprocessors, Real-time software, Discrete-Event
38	Enric Herrero, José González 0002, Ramon Canal	Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors.	ISCA	2010	DBLP DOI BibTeX RDF	elastic cooperative caching, tiled microarchitectures, chip multiprocessors, memory hierarchy
38	Muhammad Yasir Qadri, Klaus D. McDonald-Maier	A Fuzzy Logic Reconfiguration Engine for Symmetric Chip Multiprocessors.	CISIS	2010	DBLP DOI BibTeX RDF	Symmetric Chip multiprocessors, Performance, Fuzzy Logic, Energy, Reconfigurable Hardware
38	Noriko Takagi, Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura	Cooperative shared resource access control for low-power chip multiprocessors.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, chip multiprocessors, cache partitioning, dvfs, resource conflict
38	Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis	Comparative evaluation of memory models for chip multiprocessors.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	streaming memory, parallel programming, Chip multiprocessors, cache coherence, locality optimizations
38	Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio	Reducing the Interconnection Network Cost of Chip Multiprocessors.	NOCS	2008	DBLP DOI BibTeX RDF	Chip Multiprocessors, Deadlock, Router Design
38	Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis	Comparing memory systems for chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	streaming memory, parallel programming, chip multiprocessors, locality optimizations, coherent caches
38	Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez	Core fusion: accommodating software diversity in chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, reconfigurable architectures, software diversity
38	Guilin Chen, Mahmut T. Kandemir	Optimizing inter-processor data locality on embedded chip multiprocessors.	EMSOFT	2005	DBLP DOI BibTeX RDF	chip multiprocessors, data locality, stencil computation
38	Martin Schoeberl, Wolfgang Puffitsch, Benedikt Huber	Towards Time-Predictable Data Caches for Chip-Multiprocessors.	SEUS	2009	DBLP DOI BibTeX RDF
37	Guilin Chen, Mahmut T. Kandemir	An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF
37	Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie 0001, Narayanan Vijaykrishnan, Mahmut T. Kandemir	Design and Management of 3D Chip Multiprocessors Using Network-in-Memory.	ISCA	2006	DBLP DOI BibTeX RDF
35	Javier Lira, Carlos Molina, Antonio González 0001	The auction: optimizing banks usage in Non-Uniform Cache Architectures.	ICS	2010	DBLP DOI BibTeX RDF	bank replacement policy, non-uniform cache architecture (NUCA), chip multiprocessors (CMP)
35	Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng 0001, Mishali Naik, Lixia Zhang 0001, Jason Cong	A scalable micro wireless interconnect structure for CMPs.	MobiCom	2009	DBLP DOI BibTeX RDF	on-chip wireless interconnection network, chip multiprocessors
35	Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith 0001	Configurable isolation: building high availability systems with commodity multi-core processors.	ISCA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, high availability, fault isolation
35	Shimin Chen, Phillip B. Gibbons, Michael Kozuch, Vasileios Liaskovitis, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Todd C. Mowry, Chris Wilkerson	Scheduling threads for constructive cache sharing on CMPs.	SPAA	2007	DBLP DOI BibTeX RDF	constructive cache sharing, parallel depth first, thread granularity, working set profiling, chip multiprocessors, scheduling algorithms, work stealing
35	Shimin Chen, Babak Falsafi, Phillip B. Gibbons, Michael Kozuch, Todd C. Mowry, Radu Teodorescu, Anastassia Ailamaki, Limor Fix, Gregory R. Ganger, Bin Lin 0002, Steven W. Schlosser	Log-based architectures for general-purpose monitoring of deployed code.	ASID	2006	DBLP DOI BibTeX RDF	general-purpose task monitoring, log-based architectures, chip multiprocessors
35	Anders P. Ravn, Martin Schoeberl	Cyclic executive for safety-critical Java on chip-multiprocessors.	JTRES	2010	DBLP DOI BibTeX RDF
35	Sevin Fide, Stephen F. Jenks	Architecture optimizations for synchronization and communication on chip multiprocessors.	IPDPS	2008	DBLP DOI BibTeX RDF
35	Liping Xue, Mahmut T. Kandemir, Guilin Chen, Feihui Li, Ozcan Ozturk 0001, Rajaraman Ramanarayanan, Balaji Vaidyanathan	Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors.	VLSI Design	2007	DBLP DOI BibTeX RDF
35	Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Brian D. Carlstrom, Lance Hammond, Christos Kozyrakis, Kunle Olukotun	Characterization of TCC on Chip-Multiprocessors.	IEEE PACT	2005	DBLP DOI BibTeX RDF
34	Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson	Energy-efficient redundant execution for chip multiprocessors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	redundant execution, microarchitecture, transient faults, permanent faults
34	Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk 0001	Optimizing shared cache behavior of chip multiprocessors.	MICRO	2009	DBLP DOI BibTeX RDF
34	Abhishek Bhattacharjee, Margaret Martonosi	Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors.	ISCA	2009	DBLP DOI BibTeX RDF	intel tbb, thread criticality prediction, parallel processing, caches, dvfs
34	Abu Saad Papa, Madhu Mutyam	Power management of variation aware chip multiprocessors.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	chipmulti-processor, process variation, power-aware, adaptive voltage scaling
34	Martin Karlsson, Erik Hagersten	Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution.	IPDPS	2007	DBLP DOI BibTeX RDF
34	Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa	Efficient Synchronization for Embedded On-Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
34	Juan Chen 0001, Yong Dong, Xuejun Yang, Dan Wu	A Compiler-Directed Energy Saving Strategy for Parallelizing Applications in On-Chip Multiprocessors.	ISPDC	2005	DBLP DOI BibTeX RDF
34	Michael Zhang, Krste Asanovic	Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors.	ISCA	2005	DBLP DOI BibTeX RDF
34	Lin Li 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif	CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors.	DSD	2003	DBLP DOI BibTeX RDF
32	Eddy Z. Zhang, Yunlian Jiang, Xipeng Shen	Does cache sharing on modern CMP matter to the performance of contemporary multithreaded programs?	PPoPP	2010	DBLP DOI BibTeX RDF	parallel program optimizations, chip multiprocessors, shared cache, thread scheduling
32	Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith 0001	Isolation in Commodity Multicore Processors.	Computer	2007	DBLP DOI BibTeX RDF	chip multiprocessors, multicore processors, fault isolation
32	Niti Madan, Rajeev Balasubramonian	Power Efficient Approaches to Redundant Multithreading.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	redundant multi-threading (RMT), dynamic frequency scaling, Reliability, power, soft errors, transient faults, heterogeneous chip multiprocessors
32	Manohar K. Prabhu, Kunle Olukotun	Exposing speculative thread parallelism in SPEC2000.	PPoPP	2005	DBLP DOI BibTeX RDF	SPEC CPU2000, feedback-driven optimization, manual parallel programming, chip multiprocessors, multithreading, thread-level speculation
31	Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar	Optimizing Replication, Communication, and Capacity Allocation in CMPs.	ISCA	2005	DBLP DOI BibTeX RDF
31	Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang	SHARP control: controlled shared cache management in chip multiprocessors.	MICRO	2009	DBLP DOI BibTeX RDF
31	Guanjun Jiang, Degui Feng, Liangliang Tong, Lingxiang Xiang, Chao Wang 0058, Tianzhou Chen	L1 Collective Cache: Managing Shared Data for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	CMP, cache design, L1 cache
31	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	Dynamic cache clustering for chip multiprocessors.	ICS	2009	DBLP DOI BibTeX RDF	non-uniform cache architecture (nuca), chip multiprocessor (cmp)
31	Omer Khan, Sandip Kundu	Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines.	HiPEAC	2009	DBLP DOI BibTeX RDF	Dynamic Thermal Management (DTM), Virtual Thermal Manager (VTM), Dynamic Voltage and Frequency Scaling (DVFS)
31	Yunlian Jiang, Xipeng Shen, Jie Chen 0010, Rahul Tripathi	Analysis and approximation of optimal co-scheduling on chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	CMP scheduling, cache contention, perfect matching, co-scheduling
31	Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin	Adaptive set pinning: managing shared caches in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	inter-processor, intra-processor, set pinning, CMP, shared cache
31	Haakon Dybdahl, Per Stenström	An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors.	HPCA	2007	DBLP DOI BibTeX RDF
31	Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque	Adaptive L2 Cache for Chip Multiprocessors.	Euro-Par Workshops	2007	DBLP DOI BibTeX RDF
31	Sebastian Herbert, Diana Marculescu	Analysis of dynamic voltage/frequency scaling in chip-multiprocessors.	ISLPED	2007	DBLP DOI BibTeX RDF	chip-multiprocessor, dynamic voltage/frequency scaling
31	Haakon Dybdahl, Per Stenström, Lasse Natvig	A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors.	HiPC	2006	DBLP DOI BibTeX RDF
31	Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope	Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors.	ARCS	2006	DBLP DOI BibTeX RDF
31	Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Taylan Yemliha	SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors.	ICPADS (1)	2006	DBLP DOI BibTeX RDF	SPM (Scratch-Pad Memory), dynamic loop scheduling, parallelization, compiler, CMP (chip multiprocessor), data locality
31	Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen, Ozcan Ozturk 0001, Mustafa Karaköy, Ugur Sezer	Optimizing Array-Intensive Applications for On-Chip Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	On-chip multiprocessor, adaptive loop parallelization, embedded systems, energy consumption, integer linear programming, constrained optimization
31	Mahmut T. Kandemir, Guangyu Chen, Feihui Li, I. Demirkiran	Using data replication to reduce communication energy on chip multiprocessors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
31	Kyriakos Stavrou, Pedro Trancoso	TSIC: Thermal Scheduling Simulator for Chip Multiprocessors.	Panhellenic Conference on Informatics	2005	DBLP DOI BibTeX RDF
31	Mohamed A. Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz	Transient-Fault Recovery for Chip Multiprocessors.	IEEE Micro	2003	DBLP DOI BibTeX RDF
31	Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar	Transient-Fault Recovery for Chip Multiprocessors.	ISCA	2003	DBLP DOI BibTeX RDF
31	Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer	An integer linear programming based approach for parallelizing applications in On-chip multiprocessors.	DAC	2002	DBLP DOI BibTeX RDF	constraint-based compilation, embedded systems, loop-Level parallelism
30	Vassos Soteriou, Hangsheng Wang, Li-Shiuan Peh	A Statistical Traffic Model for On-Chip Interconnection Networks.	MASCOTS	2006	DBLP DOI BibTeX RDF
30	Mitsuhisa Sato	OpenMP: Parallel Programming API for Shared Memory Multiprocessors and On-Chip Multiprocessors.	ISSS	2002	DBLP DOI BibTeX RDF	deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading
29	Cor Meenderinck, Arnaldo Azevedo, Ben H. H. Juurlink, Mauricio Alvarez 0001, Alex Ramírez	Parallel Scalability of Video Decoders.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Scalability, Parallel processing, Chip multiprocessors, H.264, Video codecs
29	Fredrik Warg, Per Stenström	Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Computer architecture, Chip multiprocessors, Thread-level speculation, Thread-level parallelism, Simultaneous multithreading
29	Jose Renau, Karin Strauss, Luis Ceze, Wei Liu 0014, Smruti R. Sarangi, James Tuck 0001, Josep Torrellas	Energy-Efficient Thread-Level Speculation.	IEEE Micro	2006	DBLP DOI BibTeX RDF	out-of-order task spawning, chip multiprocessors, Thread-level speculation
29	Weiwu Hu, Rui Hou, Jun-Hua Xiao, Long-Bin Zhang	High Performance General-Purpose Microprocessors: Past and Future.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	high performance general-purpose microprocessor, Godson processor, chip multiprocessors, instruction level parallelism, thread level parallelism, data level parallelism
29	Qiang Wu, Philo Juang, Margaret Martonosi, Li-Shiuan Peh, Douglas W. Clark	Formal Control Techniques for Power-Performance Management.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Power performance management, dynamic voltage, frequency sealing, chip multiprocessors, multiple-clock-domain
29	Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlke	Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications.	HPCA	2007	DBLP DOI BibTeX RDF
29	Andrew A. Chien	Pervasive parallel computing: an historic opportunity for innovation in programming and architecture.	PPoPP	2007	DBLP DOI BibTeX RDF
29	Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen	Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading.	ACM Trans. Comput. Syst.	1997	DBLP DOI BibTeX RDF	multiprocessors, multithreading, instruction-level parallelism, thread-level parallelism, simultaneous multithreading, cache interference