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Searching for phrase Chip-multiprocessors (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1994-2001 (20) 2002-2003 (22) 2004 (22) 2005 (59) 2006 (80) 2007 (93) 2008 (92) 2009 (82) 2010 (86) 2011 (56) 2012 (30) 2013 (28) 2014 (33) 2015 (21) 2016 (19) 2017 (21) 2018-2019 (21) 2020-2023 (13)
Publication types (Num. hits)
article(195) incollection(2) inproceedings(585) phdthesis(16)
Venues (Conferences, Journals, ...)
ISCA(32) PACT(31) HPCA(26) IPDPS(24) MICRO(24) IEEE Trans. Parallel Distribut...(19) ICS(17) DATE(16) ICCD(16) DAC(15) IEEE Trans. Computers(14) Int. J. Parallel Program.(13) SIGARCH Comput. Archit. News(13) IEEE Micro(12) ICPP(11) ISLPED(11) More (+10 of total 215)
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Found 798 publication records. Showing 798 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
85Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan Compiler directed network-on-chip reliability enhancement for chip multiprocessors. Search on Bibsonomy LCTES The full citation details ... 2010 DBLP  DOI  BibTeX  RDF reliability, compiler, noc, chip multiprocessors
71Noel Eisley, Li-Shiuan Peh, Li Shang Leveraging on-chip networks for data cache migration in chip multiprocessors. Search on Bibsonomy PACT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF network-driven computing, interconnection network, CMP, chip-multiprocessor, migration
70Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF data compression, chip multiprocessors, optimizing compiler
67Chris R. Jesshope muTC - An Intermediate Language for Programming Chip Multiprocessors. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Self-adaptive computing, data-driven com-putation, programming chip multiprocessors, concurrent languages
56Hemayet Hossain, Sandhya Dwarkadas, Michael C. Huang 0001 Improving support for locality and fine-grain sharing in chip multiprocessors. Search on Bibsonomy PACT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF ARMCO, L1-to-L1 direct access, fine-grain sharing, chip multiprocessors, cache coherence
53Hyunhee Kim, Jung Ho Ahn, Jihong Kim 0001 Replication-aware leakage management in chip multiprocessors with private L2 cache. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF leakage power management, chip multiprocessors, L2 caches
53Jinglei Wang, Dongsheng Wang 0002, Yibo Xue, Haixia Wang 0001 An Efficient Lightweight Shared Cache Design for Chip Multiprocessors. Search on Bibsonomy APPT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Directory-based Cache Coherence Protocol, Lightweight Shared Cache, Chip Multiprocessors (CMP)
53Seung Woo Son 0001, Mahmut T. Kandemir, Mustafa Karaköy, Dhruva R. Chakrabarti A compiler-directed data prefetching scheme for chip multiprocessors. Search on Bibsonomy PPoPP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF compiler, chip multiprocessors, prefetching, helper thread
53Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni Design Exploration of Optical Interconnection Networks for Chip Multiprocessors. Search on Bibsonomy Hot Interconnects The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Networks-on-Chip, Interconnection, Chip Multiprocessors, Optics
50Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Ozcan Ozturk 0001 An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors. Search on Bibsonomy ISCIS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Reliability, DVS, energy minimization, duplication, heterogeneous chip multiprocessors
50Rakesh Kumar 0002, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan Heterogeneous Chip Multiprocessors. Search on Bibsonomy Computer The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Multicore microprocessors, Multiprocessors, Chip multiprocessors, CMP, Heterogeneity, System architectures, Power-aware computing
50Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir Optimizing Bus Energy Consumption of On-Chip Multiprocessors Using Frequent Values. Search on Bibsonomy PDP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF On-chip Multiprocessors, Power Optimization, Value Locality
50Vasileios Liaskovitis, Shimin Chen, Phillip B. Gibbons, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Michael Kozuch, Todd C. Mowry, Chris Wilkerson Parallel depth first vs. work stealing schedulers on CMP architectures. Search on Bibsonomy SPAA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF scheduling, caches, chip multiprocessors
50Naraig Manjikian, Huang Jin, James Reed, Nathan Cordeiro Architecture and Implementation of Chip Multiprocessors: Custom Logic Components and Software for Rapid Prototyping. Search on Bibsonomy ICPP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
49Shirish Bahirat, Sudeep Pasricha Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. Search on Bibsonomy CODES+ISSS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF photonic interconnect, network-on-chip, chip multiprocessor
49Assaf Shacham, Keren Bergman, Luca P. Carloni Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
47Ayse K. Coskun, Richard D. Strong, Dean M. Tullsen, Tajana Simunic Rosing Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors. Search on Bibsonomy SIGMETRICS/Performance The full citation details ... 2009 DBLP  DOI  BibTeX  RDF reliability, chip multiprocessors, thermal management, simulation methodology
47Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser Utilizing shared data in chip multiprocessors with the nahalal architecture. Search on Bibsonomy SPAA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF chip multiprocessors, cache memories
47Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-Hsin S. Lee Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors. Search on Bibsonomy ASPLOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF MESI protocol, internal and external snoops, self-modifying code, chip multiprocessors
47Rakesh Kumar 0002, Dean M. Tullsen, Norman P. Jouppi Core architecture optimization for heterogeneous chip multiprocessors. Search on Bibsonomy PACT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF computer architecture, multi-core architectures, heterogeneous chip multiprocessors
47Yu Zhang, Alex K. Jones Non-uniform fat-meshes for chip multiprocessors. Search on Bibsonomy IPDPS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
47Feng Liu, Vipin Chaudhary Extending OpenMP for Heterogeneous Chip Multiprocessors. Search on Bibsonomy ICPP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
46Ozcan Ozturk 0001, Mahmut T. Kandemir, G. Chen, Mary Jane Irwin, Mustafa Karaköy Customized on-chip memories for embedded chip multiprocessors. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
46Evan Speight, Hazim Shafi, Lixin Zhang 0002, Ramakrishnan Rajamony Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors. Search on Bibsonomy ISCA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
44Mahmut T. Kandemir, Ozcan Ozturk 0001, Mustafa Karaköy Dynamic on-chip memory management for chip multiprocessors. Search on Bibsonomy CASES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF chip multiprocessors, optimizing compiler, memory bank
44Wan-Yu Lee, Iris Hui-Ru Jiang VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF chip-multiprocessor, process variation, monte carlo analysis
44Ozcan Ozturk 0001, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors. Search on Bibsonomy ISVLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
44Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Martonosi, Douglas W. Clark Coordinated, distributed, formal energy management of chip multiprocessors. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF power, dynamic voltage scaling
43Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors. Search on Bibsonomy ICPADS (1) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Mustafa Karaköy, Mary Jane Irwin Integrated code and data placement in two-dimensional mesh based chip multiprocessors. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Alaa R. Alameldeen, David A. Wood 0001 Interactions Between Compression and Prefetching in Chip Multiprocessors. Search on Bibsonomy HPCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
42Jeffery A. Brown, Rakesh Kumar 0002, Dean M. Tullsen Proximity-aware directory-based coherence for multi-core processor architectures. Search on Bibsonomy SPAA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF chip multiprocessors, coherence
42Ozcan Ozturk 0001, Guilin Chen, Mahmut T. Kandemir Optimizing code parallelization through a constraint network based approach. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF compiler, constraint network, chip multiprocessing
40Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
40Yefu Wang, Kai Ma, Xiaorui Wang Temperature-constrained power control for chip multiprocessors with online model estimation. Search on Bibsonomy ISCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF power management, chip multiprocessor, feedback control
38Sungjune Youn, Hyunhee Kim, Jihong Kim 0001 A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF chip multiprocessors (CMPS), performance, embedded systems, architecture, low-power, L2 cache
38Anne Benoit, Paul Renaud-Goud, Yves Robert, Rami G. Melhem Energy-Aware Mappings of Series-Parallel Workflows onto Chip Multiprocessors. Search on Bibsonomy ICPP The full citation details ... 2011 DBLP  DOI  BibTeX  RDF power consumption minimization, chip multiprocessors, scheduling algorithms, series-parallel graphs
38Dai N. Bui, Hiren D. Patel, Edward A. Lee Deploying Hard Real-Time Control Software on Chip-Multiprocessors. Search on Bibsonomy RTCSA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Chip-multiprocessors, Real-time software, Discrete-Event
38Enric Herrero, José González 0002, Ramon Canal Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors. Search on Bibsonomy ISCA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF elastic cooperative caching, tiled microarchitectures, chip multiprocessors, memory hierarchy
38Muhammad Yasir Qadri, Klaus D. McDonald-Maier A Fuzzy Logic Reconfiguration Engine for Symmetric Chip Multiprocessors. Search on Bibsonomy CISIS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Symmetric Chip multiprocessors, Performance, Fuzzy Logic, Energy, Reconfigurable Hardware
38Noriko Takagi, Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura Cooperative shared resource access control for low-power chip multiprocessors. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF low power, chip multiprocessors, cache partitioning, dvfs, resource conflict
38Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis Comparative evaluation of memory models for chip multiprocessors. Search on Bibsonomy ACM Trans. Archit. Code Optim. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF streaming memory, parallel programming, Chip multiprocessors, cache coherence, locality optimizations
38Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio Reducing the Interconnection Network Cost of Chip Multiprocessors. Search on Bibsonomy NOCS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Chip Multiprocessors, Deadlock, Router Design
38Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis Comparing memory systems for chip multiprocessors. Search on Bibsonomy ISCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF streaming memory, parallel programming, chip multiprocessors, locality optimizations, coherent caches
38Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez Core fusion: accommodating software diversity in chip multiprocessors. Search on Bibsonomy ISCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF chip multiprocessors, reconfigurable architectures, software diversity
38Guilin Chen, Mahmut T. Kandemir Optimizing inter-processor data locality on embedded chip multiprocessors. Search on Bibsonomy EMSOFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF chip multiprocessors, data locality, stencil computation
38Martin Schoeberl, Wolfgang Puffitsch, Benedikt Huber Towards Time-Predictable Data Caches for Chip-Multiprocessors. Search on Bibsonomy SEUS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
37Guilin Chen, Mahmut T. Kandemir An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors. Search on Bibsonomy Trans. High Perform. Embed. Archit. Compil. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie 0001, Narayanan Vijaykrishnan, Mahmut T. Kandemir Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. Search on Bibsonomy ISCA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Javier Lira, Carlos Molina, Antonio González 0001 The auction: optimizing banks usage in Non-Uniform Cache Architectures. Search on Bibsonomy ICS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF bank replacement policy, non-uniform cache architecture (NUCA), chip multiprocessors (CMP)
35Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng 0001, Mishali Naik, Lixia Zhang 0001, Jason Cong A scalable micro wireless interconnect structure for CMPs. Search on Bibsonomy MobiCom The full citation details ... 2009 DBLP  DOI  BibTeX  RDF on-chip wireless interconnection network, chip multiprocessors
35Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith 0001 Configurable isolation: building high availability systems with commodity multi-core processors. Search on Bibsonomy ISCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF chip multiprocessors, high availability, fault isolation
35Shimin Chen, Phillip B. Gibbons, Michael Kozuch, Vasileios Liaskovitis, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Todd C. Mowry, Chris Wilkerson Scheduling threads for constructive cache sharing on CMPs. Search on Bibsonomy SPAA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF constructive cache sharing, parallel depth first, thread granularity, working set profiling, chip multiprocessors, scheduling algorithms, work stealing
35Shimin Chen, Babak Falsafi, Phillip B. Gibbons, Michael Kozuch, Todd C. Mowry, Radu Teodorescu, Anastassia Ailamaki, Limor Fix, Gregory R. Ganger, Bin Lin 0002, Steven W. Schlosser Log-based architectures for general-purpose monitoring of deployed code. Search on Bibsonomy ASID The full citation details ... 2006 DBLP  DOI  BibTeX  RDF general-purpose task monitoring, log-based architectures, chip multiprocessors
35Anders P. Ravn, Martin Schoeberl Cyclic executive for safety-critical Java on chip-multiprocessors. Search on Bibsonomy JTRES The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
35Sevin Fide, Stephen F. Jenks Architecture optimizations for synchronization and communication on chip multiprocessors. Search on Bibsonomy IPDPS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Liping Xue, Mahmut T. Kandemir, Guilin Chen, Feihui Li, Ozcan Ozturk 0001, Rajaraman Ramanarayanan, Balaji Vaidyanathan Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Brian D. Carlstrom, Lance Hammond, Christos Kozyrakis, Kunle Olukotun Characterization of TCC on Chip-Multiprocessors. Search on Bibsonomy IEEE PACT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson Energy-efficient redundant execution for chip multiprocessors. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF redundant execution, microarchitecture, transient faults, permanent faults
34Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk 0001 Optimizing shared cache behavior of chip multiprocessors. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
34Abhishek Bhattacharjee, Margaret Martonosi Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors. Search on Bibsonomy ISCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF intel tbb, thread criticality prediction, parallel processing, caches, dvfs
34Abu Saad Papa, Madhu Mutyam Power management of variation aware chip multiprocessors. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF chipmulti-processor, process variation, power-aware, adaptive voltage scaling
34Martin Karlsson, Erik Hagersten Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution. Search on Bibsonomy IPDPS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa Efficient Synchronization for Embedded On-Chip Multiprocessors. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Juan Chen 0001, Yong Dong, Xuejun Yang, Dan Wu A Compiler-Directed Energy Saving Strategy for Parallelizing Applications in On-Chip Multiprocessors. Search on Bibsonomy ISPDC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Michael Zhang, Krste Asanovic Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. Search on Bibsonomy ISCA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Lin Li 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors. Search on Bibsonomy DSD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
32Eddy Z. Zhang, Yunlian Jiang, Xipeng Shen Does cache sharing on modern CMP matter to the performance of contemporary multithreaded programs? Search on Bibsonomy PPoPP The full citation details ... 2010 DBLP  DOI  BibTeX  RDF parallel program optimizations, chip multiprocessors, shared cache, thread scheduling
32Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith 0001 Isolation in Commodity Multicore Processors. Search on Bibsonomy Computer The full citation details ... 2007 DBLP  DOI  BibTeX  RDF chip multiprocessors, multicore processors, fault isolation
32Niti Madan, Rajeev Balasubramonian Power Efficient Approaches to Redundant Multithreading. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF redundant multi-threading (RMT), dynamic frequency scaling, Reliability, power, soft errors, transient faults, heterogeneous chip multiprocessors
32Manohar K. Prabhu, Kunle Olukotun Exposing speculative thread parallelism in SPEC2000. Search on Bibsonomy PPoPP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF SPEC CPU2000, feedback-driven optimization, manual parallel programming, chip multiprocessors, multithreading, thread-level speculation
31Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar Optimizing Replication, Communication, and Capacity Allocation in CMPs. Search on Bibsonomy ISCA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang SHARP control: controlled shared cache management in chip multiprocessors. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
31Guanjun Jiang, Degui Feng, Liangliang Tong, Lingxiang Xiang, Chao Wang 0058, Tianzhou Chen L1 Collective Cache: Managing Shared Data for Chip Multiprocessors. Search on Bibsonomy APPT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF CMP, cache design, L1 cache
31Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem Dynamic cache clustering for chip multiprocessors. Search on Bibsonomy ICS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF non-uniform cache architecture (nuca), chip multiprocessor (cmp)
31Omer Khan, Sandip Kundu Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines. Search on Bibsonomy HiPEAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Dynamic Thermal Management (DTM), Virtual Thermal Manager (VTM), Dynamic Voltage and Frequency Scaling (DVFS)
31Yunlian Jiang, Xipeng Shen, Jie Chen 0010, Rahul Tripathi Analysis and approximation of optimal co-scheduling on chip multiprocessors. Search on Bibsonomy PACT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF CMP scheduling, cache contention, perfect matching, co-scheduling
31Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin Adaptive set pinning: managing shared caches in chip multiprocessors. Search on Bibsonomy ASPLOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF inter-processor, intra-processor, set pinning, CMP, shared cache
31Haakon Dybdahl, Per Stenström An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors. Search on Bibsonomy HPCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
31Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque Adaptive L2 Cache for Chip Multiprocessors. Search on Bibsonomy Euro-Par Workshops The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
31Sebastian Herbert, Diana Marculescu Analysis of dynamic voltage/frequency scaling in chip-multiprocessors. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF chip-multiprocessor, dynamic voltage/frequency scaling
31Haakon Dybdahl, Per Stenström, Lasse Natvig A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors. Search on Bibsonomy HiPC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
31Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors. Search on Bibsonomy ARCS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
31Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Taylan Yemliha SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors. Search on Bibsonomy ICPADS (1) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF SPM (Scratch-Pad Memory), dynamic loop scheduling, parallelization, compiler, CMP (chip multiprocessor), data locality
31Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen, Ozcan Ozturk 0001, Mustafa Karaköy, Ugur Sezer Optimizing Array-Intensive Applications for On-Chip Multiprocessors. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF On-chip multiprocessor, adaptive loop parallelization, embedded systems, energy consumption, integer linear programming, constrained optimization
31Mahmut T. Kandemir, Guangyu Chen, Feihui Li, I. Demirkiran Using data replication to reduce communication energy on chip multiprocessors. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Kyriakos Stavrou, Pedro Trancoso TSIC: Thermal Scheduling Simulator for Chip Multiprocessors. Search on Bibsonomy Panhellenic Conference on Informatics The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Mohamed A. Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz Transient-Fault Recovery for Chip Multiprocessors. Search on Bibsonomy IEEE Micro The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
31Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar Transient-Fault Recovery for Chip Multiprocessors. Search on Bibsonomy ISCA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
31Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer An integer linear programming based approach for parallelizing applications in On-chip multiprocessors. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF constraint-based compilation, embedded systems, loop-Level parallelism
30Vassos Soteriou, Hangsheng Wang, Li-Shiuan Peh A Statistical Traffic Model for On-Chip Interconnection Networks. Search on Bibsonomy MASCOTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30Mitsuhisa Sato OpenMP: Parallel Programming API for Shared Memory Multiprocessors and On-Chip Multiprocessors. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading
29Cor Meenderinck, Arnaldo Azevedo, Ben H. H. Juurlink, Mauricio Alvarez 0001, Alex Ramírez Parallel Scalability of Video Decoders. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Scalability, Parallel processing, Chip multiprocessors, H.264, Video codecs
29Fredrik Warg, Per Stenström Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor. Search on Bibsonomy Int. J. Parallel Program. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Computer architecture, Chip multiprocessors, Thread-level speculation, Thread-level parallelism, Simultaneous multithreading
29Jose Renau, Karin Strauss, Luis Ceze, Wei Liu 0014, Smruti R. Sarangi, James Tuck 0001, Josep Torrellas Energy-Efficient Thread-Level Speculation. Search on Bibsonomy IEEE Micro The full citation details ... 2006 DBLP  DOI  BibTeX  RDF out-of-order task spawning, chip multiprocessors, Thread-level speculation
29Weiwu Hu, Rui Hou, Jun-Hua Xiao, Long-Bin Zhang High Performance General-Purpose Microprocessors: Past and Future. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF high performance general-purpose microprocessor, Godson processor, chip multiprocessors, instruction level parallelism, thread level parallelism, data level parallelism
29Qiang Wu, Philo Juang, Margaret Martonosi, Li-Shiuan Peh, Douglas W. Clark Formal Control Techniques for Power-Performance Management. Search on Bibsonomy IEEE Micro The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Power performance management, dynamic voltage, frequency sealing, chip multiprocessors, multiple-clock-domain
29Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlke Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications. Search on Bibsonomy HPCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Andrew A. Chien Pervasive parallel computing: an historic opportunity for innovation in programming and architecture. Search on Bibsonomy PPoPP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading. Search on Bibsonomy ACM Trans. Comput. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF multiprocessors, multithreading, instruction-level parallelism, thread-level parallelism, simultaneous multithreading, cache interference
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