Search results for "DSP-applications"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
60	Catherine H. Gebotys, Robert J. Gebotys	Designing for Low Power in Complex Embedded DSP Systems.	HICSS	1999	DBLP DOI BibTeX RDF
55	Hyun-Gyu Kim, Hyeong-Cheol Oh	A DSP-Enhanced 32-Bit Embedded Microprocessor.	EUC	2005	DBLP DOI BibTeX RDF	DSP-enhanced microprocessor, hardware address generator, register extension, embedded microprocessor, SIMD
55	Sanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley	A Multi-Level Memory System Architecture for High-Performance DSP Applications.	ICCD	2000	DBLP DOI BibTeX RDF
54	Prithviraj Banerjee, Vikram Saxena, Juan Ramon Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, Robert Anderson	Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
54	Chia-Jui Hsu, Shuvra S. Bhattacharyya	Porting DSP Applications across Design Tools Using the Dataflow Interchange Format.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
53	Catherine H. Gebotys, Robert J. Gebotys	Complexities in DSP Software Compilation: Performance, Code Size Power, Retargetability.	HICSS (3)	1998	DBLP DOI BibTeX RDF
47	Xi-min Wang, Zhe Wang	Design and Implementation of Memory Pools for Embedded DSP.	CSSE (2)	2008	DBLP DOI BibTeX RDF
47	Wei-Kai Cheng, Youn-Long Lin	Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF	code generation, DSP
43	S. Ramanathan, S. K. Nandy 0001, V. Visvanathan	Reconfigurable Filter Coprocessor Architecture for DSP Applications.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF	reconfigurable coprocessors, filter coprocessor architecture, systolic architectures and digital signal processing, pipelined architectures, low-power architectures
42	Hyun-Gyu Kim, Hyeong-Cheol Oh	A Low-Power DSP-Enhanced 32-Bit EISC Processor.	HiPEAC	2005	DBLP DOI BibTeX RDF
41	Ivan P. Radivojevic, Jayantha A. Herath	Executing DSP Applications in a Fine-Grained Dataflow Environment.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	fine-grained dataflow architecture, numerically intensive digital signal processing, pipelined data-parallel algorithms, high-level language programming blocks, logical fine-grained decomposition, serial fraction, fine-grained general-purpose dataflow computing, parallel algorithms, parallel architectures, pipeline processing, precedence relations, computerised signal processing, DSP applications
41	Yung-Chia Lin, Yuan-Shin Hwang, Jenq Kuen Lee	Compiler Optimizations with DSP-Specific Semantic Descriptions.	LCPC	2002	DBLP DOI BibTeX RDF
40	Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez 0001, Antonio García 0001	Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices.	FPL	2004	DBLP DOI BibTeX RDF
40	Uwe Meyer-Bäse, Antonio García 0001, Fred J. Taylor	Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer
37	Chung-Ching Shen, William Plishker, Shuvra S. Bhattacharyya, Neil Goldsman	An Energy-Driven Design Methodology for Distributing DSP Applications across Wireless Sensor Networks.	RTSS	2007	DBLP DOI BibTeX RDF
37	Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee	Synthesis of Embedded Software from Synchronous Dataflow Specifications.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
36	Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis	Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications.	IPDPS	2006	DBLP DOI BibTeX RDF
36	Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis	A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications.	ISCAS	2006	DBLP DOI BibTeX RDF
36	Guilin Chen, Mahmut T. Kandemir	Optimizing Address Code Generation for Array-Intensive DSP Applications.	CGO	2005	DBLP DOI BibTeX RDF
35	Anuja Jayraj Thakkar, Abdel Ejnioui	Pipelining of double precision floating point division and square root operations.	ACM Southeast Regional Conference	2006	DBLP DOI BibTeX RDF	FPGA, pipelining, floating point, division, square root
34	Weijia Li, Youtao Zhang	An efficient code update scheme for DSP applications in mobile embedded systems.	LCTES	2010	DBLP DOI BibTeX RDF	context-aware script, context-unaware script, incremental coalescing general offset assignment (icgoa), incremental coalescing simple offset assignment (icsoa)
34	Inki Hong, Miodrag Potkonjak, Ramesh Karri	Power optimization using divide-and-conquer techniques for minimization of the number of operations.	ICCAD	1997	DBLP DOI BibTeX RDF	DSP computations, architectural techniques, divide-and-conquer compilation, portable wireless DSP applications, compilation, power consumption, data flow graphs
34	Partha Biswas, Nikil D. Dutt	Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction
34	Chia-Jui Hsu, Shuvra S. Bhattacharyya	Software Synthesis from the Dataflow Interchange Format.	SCOPES	2005	DBLP DOI BibTeX RDF	DIF, dataflow interchange format, software synthesis
34	Catherine H. Gebotys, Robert J. Gebotys	An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors.	ISLPED	1998	DBLP DOI BibTeX RDF
28	Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee	An Overview of a Compiler for Mapping Software Binaries to Hardware.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
28	Nikolas Kroupis, Stylianos Mamagkakis, Dimitrios Soudris	An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems.	ESTIMedia	2006	DBLP DOI BibTeX RDF
28	Emre Özer 0001, Andy Nisbet, David Gregg	Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
28	Björn Franke, Michael F. P. O'Boyle	Array recovery and high-level transformations for DSP applications.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	Pointer conversion, high-level transformations, embedded processors, dataflow graphs
28	Björn Franke, Michael F. P. O'Boyle	Compiler Transformation of Pointers to Explicit Array Accesses in DSP Applications.	CC	2001	DBLP DOI BibTeX RDF
28	Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya	Memory-constrained Block Processing for DSP Software Optimization.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	block processing, block diagram compiler, activation overhead, embedded systems, memory management, vectorization, dataflow, context switch
28	Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya	Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	block diagram compiler, hierarchical graph decomposition, procedural implementation, embedded systems, design methodology, memory optimization, Synchronous dataflow
28	Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya	Memory-constrained Block Processing Optimization for Synthesis of DSP Software.	ICSAMOS	2006	DBLP DOI BibTeX RDF
28	Kwangsup So, Jin-Sang Kim, Won-Kyung Cho, Young Soo Kim, Doug Young Suh	Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array.	ARC	2006	DBLP DOI BibTeX RDF
28	Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya	Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition.	SCOPES	2004	DBLP DOI BibTeX RDF
28	Russell Tessier, Wayne P. Burleson	Reconfigurable Computing for Digital Signal Processing: A Survey.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	FPGA, survey, reconfigurable computing, signal processing
28	Awni Itradat, M. Omair Ahmad, Ali M. Shatnawi	Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional Units.	ISCAS	2007	DBLP DOI BibTeX RDF
28	Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis	Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path.	FCCM	2004	DBLP DOI BibTeX RDF
28	Javier Ramírez 0001, Antonio García 0001, Pedro G. Fernández, Luis Parrilla 0001, Antonio Lloris-Ruíz	Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform.	FPL	2000	DBLP DOI BibTeX RDF
28	Joseph T. Buck	A dynamic dataflow model suitable for efficient mixed hardware and software implementations of DSP applications.	CODES	1994	DBLP DOI BibTeX RDF
27	Greet Bilsen, Rudy Lauwereins, J. A. Peperstraete	Compile-time scheduling with resource-constraints.	HICSS (2)	1995	DBLP DOI BibTeX RDF	multiple execution, CPU-usage, run-time performance, nonCPU resource requirements, performance evaluation, resource allocation, signal processing, digital signal processing, program compilers, processor scheduling, resource-constraints, static schedule, compile-time scheduling, scheduling method, DSP-applications
27	Partha Biswas, Nikil D. Dutt	Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions.	CASES	2003	DBLP DOI BibTeX RDF	dependence conflict graph, heterogeneous-connectivity-based DSP, restricted data dependence graph, instruction set extensions, instruction set architecture, static single assignment
27	Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob	Transparent data-memory organizations for digital signal processors.	CASES	2001	DBLP DOI BibTeX RDF
27	Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair	Performance Considerations in Embedded DSP based System-On-a-Chip Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
23	Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal	Multi-core architectures and streaming applications.	SLIP	2008	DBLP DOI BibTeX RDF	NoC design, multi-core SoC design, system design, streaming applications
23	Jacob Fainguelernt, Graham Reith, Richard Sikora	An integrated environment for developing real-time DSP applications.	ICASSP	2008	DBLP DOI BibTeX RDF
23	Michalis D. Galanis, Gregory Dimitroulakos, Constantinos E. Goutis	An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
22	Carles Rodoreda Sala, Natalino G. Busá	A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor.	ISSS	2002	DBLP DOI BibTeX RDF	VLIW processors, reconfigurable logic, architectural synthesis
22	Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis	Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware.	IPDPS	2006	DBLP DOI BibTeX RDF
22	Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis	Mapping DSP applications on processor/coarse-grain reconfigurable array architectures.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Florian Marteil, Nathalie Julien, Eric Senn, Eric Martin 0001	A Complete Methodology for Memory Optimization in DSP Applications.	DSD	2004	DBLP DOI BibTeX RDF
22	Michael A. Soderstrand	CSD multipliers for FPGA DSP applications.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
22	Katarzyna Leijten-Nowak, Jef L. van Meerbergen	Embedded Reconfigurable Logic Core for DSP Applications.	FPL	2002	DBLP DOI BibTeX RDF
21	Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas	Architecture and Evaluation of an Asynchronous Array of Simple Processors.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	programmable DSP, digital signal processing, DSP, multi-core, array processor, GALS, many-core, chip multi-processor, globally asynchronous locally synchronous
21	Sanghamitra Roy, Prith Banerjee	An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	field programmable gate arrays, Automation, quantization, floating-point arithmetic, fixed-point arithmetic
21	Jani Paakkulainen, Seppo Virtanen, Jouni Isoaho	Tuning a Protocol Processor Architecture Towards DSP Operations.	SAMOS	2005	DBLP DOI BibTeX RDF
21	William R. Dieter, Srabosti Datta, Wong Key Kai	Power reduction by varying sampling rate.	ISLPED	2005	DBLP DOI BibTeX RDF	real-time audio, digital signal processing, voltage scaling, power-aware, frequency scaling
21	Mauro Olivieri, Mirko Scarana, Simone Smorfa	Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
21	Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin 0001	Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Prototyping, Refinement, High-level synthesis, Design space exploration, System level design
21	Jer-Min Jou, Yun-Lung Lee, Chen-Yen Lin, Chien-Ming Sun	A Novel Reconfigurable Computation Unit for DSP Applications.	ISVLSI	2007	DBLP DOI BibTeX RDF
21	Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin 0001	Design Space Exploration of DSP Applications Based on Behavioral Description Models.	SiPS	2006	DBLP DOI BibTeX RDF
21	Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis	A reusable IP FFT core for DSP applications.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
21	Oleg Maslennikow, Juri Shevtshenko, Anatoli Sergyienko	Configurable Microprocessor Array for DSP Applications.	PPAM	2003	DBLP DOI BibTeX RDF
21	Youtao Zhang, Jun Yang 0002	Procedural Level Address Offset Assignment of DSP Applications with Loops.	ICPP	2003	DBLP DOI BibTeX RDF
21	A. K. Rath, Pramod Kumar Meher	Reconfigurable execution core for high performance DSP applications.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
21	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah	A Low Power Approach to Floating Point Adder Design for DSP Applications.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	digital-CMOS, power-consumption-model, VLSI, low-power-design, computer-arithmetic, floating-point, switching-activity
21	Nam Ling	A special purpose formal verifier for systolic designs in DSP applications.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
20	Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee	Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study.	ETS	2006	DBLP DOI BibTeX RDF
20	Elana D. Granston, Eric Stotzer, Joe Zbiciak	Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture.	LCTES/OM	2001	DBLP DOI BibTeX RDF	WHILE loops, software pipelining, digital signal processors, VLIW architectures
20	Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss	A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines.	DSD	2001	DBLP DOI BibTeX RDF
20	M. Agarwala, Poras T. Balsara	An architecture for a DSP field-programmable gate array.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
20	Catherine H. Gebotys	Throughput optimized architectural synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
20	Ching-Long Su, Yin-Tsung Hwang	Distributed arithmetic-based architectures for high speed IIR filter design.	ICPADS	1996	DBLP DOI BibTeX RDF	high speed IIR filter, pipelining techniques, SPDM technology, parallel processing, parallel architectures, digital arithmetic, recursion, recursive filters, Distributed Arithmetic, IIR filters, DSP applications
20	S. Samel, Bert Gyselinckx, Ivo Bolsens, Hugo De Man	Designing Systems On Silicon: A Digital Spread Spectrum Pager.	VLSI Design	1996	DBLP DOI BibTeX RDF	System Design Methodologies, HW/SW Co-design, DSP Applications
16	Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee	An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design.	FPGA	2004	DBLP DOI BibTeX RDF
16	Sanghamitra Roy, Prithviraj Banerjee	An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design.	DAC	2004	DBLP DOI BibTeX RDF	quantization, quantizer, floating point, fixed point
15	Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki	Astra: An Advanced Space-Time Reconfigurable Architecture.	FPL	2006	DBLP DOI BibTeX RDF
15	Alireza Shoa, Shahram Shirani	Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	FPGA, DSP, Run-Time Reconfiguration (RTR)
15	Vadim Gutnik, Anantha P. Chandrakasan	Embedded power supply for low-power DSP.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
15	Corinne Ancourt, Denis Barthou, Christophe Guettier, François Irigoin, Bertrand Jeannet, Jean Jourdan, Juliette Mattioli	Automatic data mapping of signal processing applications.	ASAP	1997	DBLP DOI BibTeX RDF	automatic data mapping, signal processing applications, architectural resources constraints, fine-grain scheduling, concurrent constraints logic programming languages, concurrent resolution technique, panoramic analysis, mapping, parallel machine, data partitioning, distributed memory, real time constraints, logic programming languages
15	Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Chaitali Chakrabarti, Scott A. Mahlke, Trevor N. Mudge	Diet SODA: a power-efficient processor for digital cameras.	ISLPED	2010	DBLP DOI BibTeX RDF	digital still cameras, near-threshold, dynamic voltage scaling, SIMD
15	Sunil Shukla, Neil W. Bergmann, Jürgen Becker 0001	QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks.	IPDPS	2007	DBLP DOI BibTeX RDF
15	Wei Wang 0015, Dongming Peng, Honggang Wang 0001, Hamid Sharif	Study of an energy efficient multi rate scheme for wireless sensor network MAC protocol.	Q2SWinet	2006	DBLP DOI BibTeX RDF	wireless sensor network, energy efficiency, MAC, multi rate
15	Nikhil Bansal 0003, Sumit Gupta, Nikil D. Dutt, Alexandru Nicolau, Rajesh Gupta 0001	Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures.	DATE	2004	DBLP DOI BibTeX RDF
15	Pedro C. Diniz, Joonseok Park	Data reorganization engines for the next generation of system-on-a-chip FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF	field-programmable-gate-arrays (FPGAs), high-level synthesis, data reorganization
15	Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne P. Burleson	A dynamically reconfigurable adaptive viterbi decoder.	FPGA	2002	DBLP DOI BibTeX RDF	field-programmable-gate-arrays (FPGAs), high-level synthesis, data reorganization
15	Bin Xiao 0001, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge	Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops.	ISSS	2002	DBLP DOI BibTeX RDF	rotation scheduling, software pipelining, retiming, unfolding
15	Martyn Edwards, Peter Green 0001	The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware.	FPL	2000	DBLP DOI BibTeX RDF
15	Amr M. Fahim, Mohamed I. Elmasry	A Low-Voltage High-Performance Differential Static Logic (LVDSL) family.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
15	Sissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Nelson L. Passos	Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
15	Chih-Tung Chen, Kayhan Küçükçakar	High-level scheduling model and control synthesis for a broad range of design applications.	ICCAD	1997	DBLP DOI BibTeX RDF	multi-phase clocking, relative scheduling, architectural power optimization, high-level synthesis, pipelining, multi-threading, behavioral synthesis, control synthesis, architectural synthesis, scheduling model
15	Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee	Optimized software synthesis for synchronous dataflow.	ASAP	1997	DBLP DOI BibTeX RDF	optimized software synthesis, programmable digital signal processors, off-chip memory, real-time systems, digital signal processing, synchronous dataflow, graphical programs
15	Ching-Yi Wang, Keshab K. Parhi	Resource-constrained loop list scheduler for DSP algorithms.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
14	Nima Honarmand, M. Reza Javaheri, Naser Sedaghati-Mokhtari, Ali Afzali-Kusha	Power efficient sequential multiplication using pre-computation.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Nima Honarmand, Ali Afzali-Kusha	Low Power Combinational Multipliers using Data-driven Signal Gating.	APCCAS	2006	DBLP DOI BibTeX RDF
14	Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Mei Kang Qiu, Edwin Hsing-Mean Sha	Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs.	EUC	2005	DBLP DOI BibTeX RDF	Loop Distribution, Embedded DSP, Scheduling, Code Size, Loop Fusion
14	Hiren D. Patel, Sandeep K. Shukla	Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	simulation efficiency, synchronous data flow, heterogeneous, SystemC, models of computation, embedded system design
14	Reza Hashemian, Bipin Sreedharan	A Hybrid Number System And Its Application In FPGA-DSP Technology.	ITCC (2)	2004	DBLP DOI BibTeX RDF
14	Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen	An Efficient VLIW DSP Architecture for Baseband Processing.	ICCD	2003	DBLP DOI BibTeX RDF
14	Ramaswamy Govindarajan, Guang R. Gao, Palash Desai	Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	buffer minimization, Digital Signal Processing (DSP) computation, Multi-Rate Software Pipelining, Regular Stream Flow Graphs, software pipelining, dataflow graphs