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Searching for phrase Delay-Insensitive (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1986-1991 (19) 1992-1994 (20) 1995-1996 (16) 1997-1998 (24) 1999-2001 (22) 2002-2003 (28) 2004-2005 (36) 2006 (17) 2007 (19) 2008-2009 (24) 2010-2011 (18) 2012-2014 (23) 2015-2017 (20) 2018-2021 (17) 2022-2023 (8)
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article(89) inproceedings(221) phdthesis(1)
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Found 311 publication records. Showing 311 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
115Priyadarsan Patra, Donald S. Fussell Power-efficient delay-insensitive codes for data transmission. Search on Bibsonomy HICSS (1) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF telecommunication switching, power-efficient delay-insensitive codes, dynamic delay-insensitive codes, switching energy optimization, data pins, protocols, delays, power consumption, codes, asynchronous systems, data communication, data communication, data transmission, energy reduction, delay-insensitive circuits
105Jia Di, Parag K. Lala Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. Search on Bibsonomy J. Electron. Test. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Reed-Muller expression, nanoscale circuit, layout, stuck-at fault, cellular arrays, delay-insensitive circuit
99H. Bekker, E. J. Dijkstra Delay-Insensitive Synchronization on a Message-Passing Architecture with an Open Collector Bus. Search on Bibsonomy PDP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF delay-insensitive synchronization, open collector bus, high latency, constraint algorithm, SHAKE, Constraint Molecular Dynamics simulation, ring architecture, delay insensitive algorithm, performance evaluation, performance, parallel algorithms, parallel algorithms, parallel architectures, message passing, multiprocessor interconnection networks, multiprocessor interconnection networks, synchronisation, digital simulation, physics computing, system buses, communication time, message passing architecture
74Sandeep Pagey Fast functional testing of delay-insensitive circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF four-phase handshake signalling, Martin's method, distributed circuit, OR/C blocks, generation of test sequences, program flow graph, logic testing, delays, design for testability, logic CAD, asynchronous circuits, functional testing, testing time, self-timed circuits, delay-insensitive circuits, OR gates
70Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Delay-insensitive codes, self-timed design, delay-insensitive communication, block codes
59Pedro A. Molina, Peter Y. K. Cheung A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Tri-state Buffers, Asynchronous, Composability, Bus, Data Path, Delay-Insensitive, Handshake Circuits
57Hiroshi Saito, Alex Kondratyev, Takashi Nanya Design of Asynchronous Controllers with Delay Insensitive Interface. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF delay insensitive interface, gate-level transformation, behavioral transformation, asynchronous circuits, hazards
57Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. Search on Bibsonomy ASYNC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF pulse-driven logic, Josephson junction device, RSFQ device, pipeline, asynchronous circuit, delay-insensitive circuit
54Jia Lee, Ferdinand Peper, Susumu Adachi, Kenichi Morita Universal Delay-Insensitive Circuits with Bidirectional and Buffering Lines. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF bidirectional buffering lines, module, Asynchronous systems, universality, delay-insensitive circuits
54Willem C. Mallon, Jan Tijmen Udding Using Metrics for Proof Rules for Recursively Defined Delay-insensitive Specifications. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF delay-insensitive specifications, recursive definition, linear proofs, intuitive induction rule, algebraic specification, algebraic specifications, theorem provers, correctness proofs, proof rules, proof rule
48Gregg N. Hoyer, Gin Yee, Carl Sechen Locally clocked pipelines and dynamic logic. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
48Yoshio Kameda Pulse-Driven Delay-Insensitive Circuits using Single-Flux-Quantum Devices. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
45David K. Probst, Hon Fung Li Partial-Order Model Checking: A Guide for the Perplexed. Search on Bibsonomy CAV The full citation details ... 1991 DBLP  DOI  BibTeX  RDF delay-insensitive system, partial-order representation, recurrence structure, model checking, state explosion, state encoding
45Daniel H. Linder, James C. Harden Phased Logic Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Asynchronous circuitry, delay-insensitive circuitry, dual-rail encoding, LEDR, phased logic, synchronous circuitry, data flow, marked graphs
43Jia Di, Dilip P. Vasudevan Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays. Search on Bibsonomy DELTA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Christopher LaFrieda, Rajit Manohar Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits. Search on Bibsonomy DSN The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
42Lei Wang 0014, Carl McCrosky Performance Comparison of Control Schemes for ABR Service in ATM LANs. Search on Bibsonomy MASCOTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF ABR service, ATM Forum, available bit rate service, constrained cell loss, network resource utilization, CBR/VBR services, burst level traffic control, rate based feedback control, loss sensitive applications, delay insensitive applications, burst transfer delay, simulation, asynchronous transfer mode, bandwidth, performance comparison, ATM LAN, delay variation
41Masashi Imai, Metehan Γ–zcan, Takashi Nanya Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. Search on Bibsonomy ASYNC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
41A. Neslin Ismailoglu, Murat Askar Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Ethiopia Nigussie, Juha Plosila, Jouni Isoaho Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling. Search on Bibsonomy ISVLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
41Jia Di, Parag K. Lala, Dilip P. Vasudevan On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. Search on Bibsonomy DFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
38Igor Lemberski, Mark B. Josephs Optimal Two-Level Delay - Insensitive Implementation of Logic Functions. Search on Bibsonomy PATMOS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Mark B. Josephs, Dennis P. Furey Delay-Insensitive Interface Specification and Synthesis. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
38Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
38Priyadarsan Patra, Donald S. Fussell Efficient Delay-Insensitive RSFQ Circuits. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
38David M. Goldschlag Mechanically Verifying Safety and Liveness Properties of Delay Insensitive Circuits. Search on Bibsonomy CAV The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
38Anders Gammelgaard Implementation Conditions for Delay Insensitive Circuits. Search on Bibsonomy PARLE (1) The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
36Dario Pompili, Tommaso Melodia, Ian F. Akyildiz Routing algorithms for delay-insensitive and delay-sensitive applications in underwater sensor networks. Search on Bibsonomy MobiCom The full citation details ... 2006 DBLP  DOI  BibTeX  RDF routing algorithms, underwater sensor networks
35Raffaele Mascella, Luca G. Tallini Efficient m-Ary Balanced Codes which Are Invariant under Symbol Permutation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Coding and information theory, m{hbox{-}}rm ary communication, line codes, DC-free communication, delay-insensitive communication, error control codes, digital communication, constant weight codes, balanced codes
35Yannick Monnet, Marc Renaudin, RΓ©gis Leveugle Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF quasi-delay insensitive, hardening techniques, Asynchronous circuits, data encryption standard, fault attacks
35Yannick Monnet, Marc Renaudin, RΓ©gis Leveugle Asynchronous circuits transient faults sensitivity evaluation. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF quasi delay insensitive, simulation, fault model, asynchronous circuits, transient fault
35Hemangee K. Kapoor, Mark B. Josephs Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF asynchronous logic synthesis, delay-insensitive decomposition
35Marc Renaudin, Pascal Vivet, FrΓ©dΓ©ric Robin ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. Search on Bibsonomy ASYNC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design
35R. S. Hogg, W. I. Hughes, David W. Lloyd A Novel Asynchronous ALU for Massively Parallel Architectures. Search on Bibsonomy PDP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit
35Priyadarsan Patra, Donald S. Fussell Fully asynchronous, robust, high-throughput arithmetic structures. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers
35David K. Probst, Hon Fung Li Using Partial-Order Semantics to Avoid the State Explosion Problem in Asynchronous Systems. Search on Bibsonomy CAV The full citation details ... 1990 DBLP  DOI  BibTeX  RDF delay-insensitive system, branching point, recurrence structure, behavior machine, behavior state, model checking, state explosion, partial-order semantics
31Masashi Imai, Takashi Nanya A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. Search on Bibsonomy ASYNC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
31Ethiopia Nigussie, Juha Plosila, Jouni Isoaho Area efficient delay-insensitive and differential current sensing on-chip interconnect. Search on Bibsonomy SoCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Furey Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments. Search on Bibsonomy ACSD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
29Amitava Mitra, William F. McLaughlin, Steven M. Nowick Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. Search on Bibsonomy ASYNC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Yannick Monnet, Marc Renaudin, RΓ©gis Leveugle Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. Search on Bibsonomy IOLTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Giuseppe Campobello, Marco Castano, Carmine Ciofi, Daniele Mangano GALS networks on chip: a new solution for asynchronous delay-insensitive links. Search on Bibsonomy DATE Designers' Forum The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. Search on Bibsonomy CHES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF QDI Asynchronous circuits, Path Swapping (PS), Power analysis
29G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. Search on Bibsonomy VLSI-SoC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Bertrand Folco, Vivian BrΓ©gier, Laurent Fesquet, Marc Renaudin Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. Search on Bibsonomy VLSI-SoC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Konrad J. Kulikowski, Ming Su, Alexander B. Smirnov, Alexander Taubin, Mark G. Karpovsky, Daniel MacDonald Delay Insensitive Encoding and Power Analysis: A Balancing Act. Search on Bibsonomy ASYNC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Hemangee K. Kapoor, Mark B. Josephs Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation. Search on Bibsonomy ACSD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Myeong-Hoon Oh, Dong-Soo Har A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic. Search on Bibsonomy PATMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
29Alexander Taubin, Karl Fant, John McCardle Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing. Search on Bibsonomy ICCD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
29Robert Berks, Radu Negulescu Partial-Order Correctness-Preserving Properties of Delay-Insensitive Circuits. Search on Bibsonomy ASYNC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
29W. J. Bainbridge, Stephen B. Furber Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding. Search on Bibsonomy ASYNC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
29Nattha Sretasereekul, Takashi Nanya Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
29Willem C. Mallon On Directed Transformations of Delay-Insensitive Specifications, Alternations and Dynamic Nondeterminism. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF {Communicating Processes}, {Computer Aided Design}, Meta-stability, Formal Methods, Handshake Protocol, Delay-Insensitivity
29Fu-Chiung Cheng, Chuin-Ren Wang Specification and Design of a Quasi-Delay-Insensitive Java Card. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
29Tom Verhoeff Analyzing Specifications for Delay-Insensitive Circuits. Search on Bibsonomy ASYNC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
29Priyadarsan Patra, Stanislav Polonsky, Donald S. Fussell Delay Insensitive Logic for RSFQ Superconductor Technology. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
29Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho Delay-Insensitive Carry-Lookahead Adders. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
29S. C. Leung, Hon Fung Li On the realizability and synthesis of delay-insensitive behaviors. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
29S. C. Leung, Hon Fung Li A syntax-directed translation for the synthesis of delay-insensitive circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
29Takashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura TITAC: Design of A Quasi-Delay-Insensitive Microprocessor. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
29Mark B. Josephs, Jan Tijmen Udding Delay-Insensitive Circuits: An Algebraic Approach to their Design. Search on Bibsonomy CONCUR The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
29Alain J. Martin The Design of a Delay-Insensitive Microprocessor: An Example of Circuit Synthesis by Program Transformation. Search on Bibsonomy Hardware Specification, Verification and Synthesis The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
26David W. Lloyd, Jim D. Garside A Practical Comparison of Asynchronous Design Styles. Search on Bibsonomy ASYNC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
26Scott C. Smith Design of a logic element for implementing an asynchronous FPGA. Search on Bibsonomy FPGA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF NULL convention logic (NCL), asynchronous logic design, field programmable gate array (FPGA), reconfigurable logic, delay-insensitive circuits
26Mehrdad Najibi, Kamran Saleh, Hossein Pedram Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF quasi-delay insensitive, standard-cell layout, asynchronous circuits
26Signe J. Silver, Janusz A. Brzozowski True Concurrency in Models of Asynchronous Circuit Behavior. Search on Bibsonomy Formal Methods Syst. Des. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF multiple-winner, single-winner, semi-modular, asynchronous, circuit, interleaving, true concurrency, delay-insensitive
26Luca G. Tallini, Bella Bose Transmission Time Analysis for the Parallel Asynchronous Communication Scheme. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF delay-insensitive codes, proximity detecting codes, low weight codes, Asynchronous communication, constant weight codes, unordered codes
26Scott C. Smith Speedup of Self-Timed Digital Systems Using Early Completion. Search on Bibsonomy ISVLSI The full citation details ... 2002 DBLP  DOI  BibTeX  RDF asynchronous, NCL, NULL Convention Logic, delay-insensitive
26Luca G. Tallini, Bella Bose Some Transmission Time Analysis for the Parallel Asynchronous Communication Scheme. Search on Bibsonomy FTCS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF delay-insensitive codes, proximity detecting codes, low weight codes, Asynchronous communication, constant weight codes, unordered codes
26Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian A Tabular Method for Guard Strengthening, Symmetrization, and Operator Reduction for Martin's Asynchronous Design Methodology. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1997 DBLP  DOI  BibTeX  RDF formal program transformation, self-timed logic, signal transition graphs (STG), speed independent circuits, guarded commands, delay insensitive circuits, Asynchronous sequential circuits
24Dario Pompili, Tommaso Melodia Three-dimensional routing in underwater acoustic sensor networks. Search on Bibsonomy PE-WASUN The full citation details ... 2005 DBLP  DOI  BibTeX  RDF routing algorithms, mathematical programming/optimization, underwater acoustic sensor networks
24Myeong-Hoon Oh, Dong-Soo Har Low Delay-Power Product Current-Mode Multiple Valued Logic for Delay-Insensitive Data Transfer Mechanism. Search on Bibsonomy IEICE Trans. Fundam. Electron. Commun. Comput. Sci. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22P. Balasubramanian 0001, David A. Edwards, Charlie Brej Self-timed full adder designs based on hybrid input encoding. Search on Bibsonomy DDECS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
19Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger Early evaluation for performance enhancement in phased logic. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
19Susumu Adachi, Ferdinand Peper, Jia Lee Universality of Hexagonal Asynchronous Totalistic Cellular Automata. Search on Bibsonomy ACRI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
19Mark B. Josephs Formal Derivation of a Loadable Asynchronous Counter. Search on Bibsonomy MPC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
19Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits. Search on Bibsonomy ISMVL The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
19Yong Zhang, Xin Zhang 0001 QoS Based Proportional Fair Scheduling Algorithm for CDMA Forward Link. Search on Bibsonomy VTC Spring The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
19Zaheer Tabassam, Andreas Steininger Towards Resilient Quasi Delay Insensitive Conditional Control Elements. Search on Bibsonomy DSD The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
19Zaheer Tabassam, Andreas Steininger SET Effects on Quasi Delay Insensitive and Synchronous Circuits. Search on Bibsonomy ETS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
19Zaheer Tabassam, Andreas Steininger, Robert Najvirt, Florian Huemer ΞΆ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. Search on Bibsonomy ASYNC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
19Duarte Lopes de Oliveira, Marcus H. Victor, Luiz C. Moreira, Felipe F. Nascimento Design of Quasi Delay Insensitive Combinational Circuits Based on Optimized DIMS. Search on Bibsonomy LASCAS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
19Dalta Imam Maulana, Wanyeong Jung An Energy-Efficient Delay Insensitive Asynchronous Interface for Globally Asynchronous Locally Synchronous (GALS) System. Search on Bibsonomy ISCAS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
19Zeguo Liu, Jingyi Yuan, Feng Wu, Lin Cheng 0001 A 12V/24V-to-1V PWM-Controlled DSD Converter With Delay-Insensitive and Dual-Phase Charging Techniques for Fast Transient Responses. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
19Yue Feng, Yuanli Yue, Qiang Wu 0005, Chao Wang 0074 Delay-Insensitive Time Stretch Interrogation of Fiber Bragg Grating Sensors. Search on Bibsonomy CSNDSP The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
19Orlando Verducci Jr., Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices. Search on Bibsonomy LASCAS The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
19Raghda El Shehaby, Andreas Steininger Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. Search on Bibsonomy DDECS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
19Duarte Lopes de Oliveira, Gabriel C. Duarte, Gracieth Cavalcanti Batista A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication. Search on Bibsonomy LASCAS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
19Taciano A. Rodolfo, Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison. Search on Bibsonomy ISCAS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
19Orlando Verducci Jr., Duarte Lopes de Oliveira, Robson L. Moreno Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices. Search on Bibsonomy LATS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
19Linh Duc Tran, Thanh Chi Pham, Omid Kavehei, Peter C. M. Burton, Glenn Ian Matthews Extended Boolean algebra for asynchronous quasi-delay-insensitive logic. Search on Bibsonomy IET Circuits Devices Syst. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
19Padmanabhan Balasubramanian, Nikos E. Mastorakis Quasi-Delay-Insensitive Implementation of Approximate Addition. Search on Bibsonomy Symmetry The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
19P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications. Search on Bibsonomy CoRR The full citation details ... 2020 DBLP  BibTeX  RDF
19Yuri Stepchenkov, Yuri Rogdestvenski, Anton N. Kamenskih, Yuri Diachenko, Denis Diachenko Improvement of the Quasi Delay-Insensitive Pipeline Noise Immunity. Search on Bibsonomy DESSERT The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
19P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
19P. Balasubramanian 0001 Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
19Quang Tran Minh 0001, Van An Le, Tran Khanh Dang, Nam Thoai, Takeshi Kitahara Flow aggregation for SDN-based delay-insensitive traffic control in mobile core networks. Search on Bibsonomy IET Commun. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
19Yi-Fan Evan Chang, Ruei-Yang Huang, Jie-Hong R. Jiang Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
19P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications. Search on Bibsonomy EECS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
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