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Found 784 publication records. Showing 784 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
153Tung-Chieh Chen, Yao-Wen Chang Modern floorplanning based on fast simulated annealing. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF simulated annealing, floorplanning
117Tung-Chieh Chen, Yao-Wen Chang Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
94Jianzhong Shi, Akash Randhar, Dinesh Bhatia Macro Block Based FPGA Floorplanning. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design
93Chaomin Luo, Miguel F. Anjos, Anthony Vannelli A nonlinear optimization methodology for VLSI fixed-outline floorplanning. Search on Bibsonomy J. Comb. Optim. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Circuit layout design, VLSI floorplanning, Facility layout, Combinatorial optimization, Global optimization, Convex programming
88Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances
83Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He 0001 Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF piecewise-linear, performance, pipeline, interconnect, floorplanning
77Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
77Saurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov Unification of partitioning, placement and floorplanning. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
72Bo-Shiun Wu, Tsung-Yi Ho Bus-pin-aware bus-driven floorplanning. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF bus planning, floorplanning
72Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng Integrating dynamic thermal via planning with 3D floorplanning algorithm. Search on Bibsonomy ISPD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF 3D floorplanning, thermal optimization, thermal via
72Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang Constrained "Modern" Floorplanning. Search on Bibsonomy ISPD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF floorplanning, network flow, rectilinear polygons
72Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang Multilevel floorplanning/placement for large-scale modules using B*-trees. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF multilevel framework, floorplanning, lagrangian relaxation
72Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. Search on Bibsonomy ISPD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF floorplanning, routability, interconnect estimation
72Maggie Zhiwei Kang, Wayne Wei-Ming Dai, Tom Dillinger, David P. LaPotin Delay bounded buffered tree construction for timing driven floorplanning. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Total Wire Length, DBB-tree, SPT, Floorplanning, Buffer Insertion, Delay Bounds, Elmore Delay, MST
70Jarrod A. Roy, Saurabh N. Adya, David A. Papa, Igor L. Markov Min-cut floorplacement. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
67Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He 0001 Microarchitecture Configurations and Floorplanning Co-Optimization. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
67Jason Cong, Jie Wei, Yan Zhang A thermal-driven floorplanning algorithm for 3D ICs. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
67Abhishek Ranjan, Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh Fast floorplanning for effective prediction and construction. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
66Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu Architecting voltage islands in core-based system-on-a-chip designs. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF multiple VDD, low-power, floorplanning, system-on-a-chip, voltage island
62Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs. Search on Bibsonomy ISPD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF multiple-supply voltage designs, physical design, floorplanning, vlsi
62Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF floorplanning, thermal, 3D IC
62Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF floorplanning, microarchitecture, transient analysis
62Rong Liu, Sheqin Dong, Xianlong Hong Fixed-outline floorplanning based on common subsequence. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF common subsequence, floorplanning, fixed-outline
62Meng-Chiou Wu, Rung-Bin Lin Reticle floorplanning of flexible chips for multi-project wafers. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF mask cost, multi-project wafer, reticle floorplanning, dicing
62Jason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl An area-optimality study of floorplanning. Search on Bibsonomy ISPD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF area partitioning, block packing, optimality, benchmarking, placement, floorplanning, aspect ratios
62Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen 0001, Yici Cai, Chung-Kuan Cheng, Jun Gu An integrated floorplanning with an efficient buffer planning algorithm. Search on Bibsonomy ISPD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF floorplanning, buffer insertion, routability
62Xiaoping Tang, D. F. Wong 0001 Floorplanning with alignment and performance constraints. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF floorplanning, longest common subsequence, sequence pair
60Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao Simultaneous floor plan and buffer-block optimization. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
57Bei Yu 0001, Sheqin Dong, Satoshi Goto, Song Chen 0001 Voltage-island driven floorplanning considering level-shifter positions. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF convex network flow, level shifter assignment, voltage assignment, white space redistribution, voltage-island
57Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou 0001, Xianlong Hong, Qiang Zhou 0001 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
57Hua Xiang 0001, Liang Deng, Li-Da Huang, Martin D. F. Wong OPC-Friendly Bus Driven Floorplanning. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
57Minsik Cho, Hongjoong Shin, David Z. Pan Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
57Yan Feng, Dinesh P. Mehta Heterogeneous Floorplanning for FPGAs. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
57Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu LFF algorithm for heterogeneous FPGA floorplanning. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
57Maolin Tang, Alvin Sebastian A Genetic Algorithm for VLSI Floorplanning Using O-Tree Representation. Search on Bibsonomy EvoWorkshops The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
57Meng-Chiou Wu, Rung-Bin Lin Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
57Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang Constrained floorplanning using network flows. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
57Thomas Lengauer, Rolf Müller Robust and accurate hierarchical floorplanning with integrated global wiring. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
52Song Chen 0001, Takeshi Yoshimura A stable fixed-outline floorplanning method. Search on Bibsonomy ISPD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF floorplanning, sequence pair, fixed-outline
52Mario R. Casu, Luca Macchiarulo Floorplanning for throughput. Search on Bibsonomy ISPD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF systems-on-chip, throughput, floorplanning, wire pipelining
52Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Interconnect-Driven Floorplanning, Performance Optimization
52Israel Koren, Zahava Koren Incorporating Yield Enhancement into the Floorplanning Process. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF memory ICs, routing complexity, redundancy, microprocessor, Floorplanning, yield
52Pradeep Prabhakaran, Prithviraj Banerjee Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF timing driven synthesis, High-level synthesis, floorplanning
48Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh 3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 1999 DBLP  DOI  BibTeX  RDF 3-D floorplanning, Reconfigurable computing, floorplanning
47Minsik Cho, David Z. Pan Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
47Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
47Dae Hyun Kim 0004, Sung Kyu Lim Bus-aware microarchitectural floorplanning. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
47Maolin Tang, Xin Yao 0001 A Memetic Algorithm for VLSI Floorplanning. Search on Bibsonomy IEEE Trans. Syst. Man Cybern. Part B The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Hushrav Mogal, Kia Bazargan Microarchitecture floorplanning for sub-threshold leakage reduction. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Chunta Chu, Xinyi Zhang, Lei He 0001, Tong Jing Temperature aware microprocessor floorplanning considering application dependent power load. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Peter G. Sassone, Sung Kyu Lim Traffic: a novel geometric algorithm for fast wire-optimized floorplanning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Jason Cong, Michail Romesis, Joseph R. Shinnerl Fast floorplanning by look-ahead enabled recursive bipartitioning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Vijay Sundaresan, Ranga Vemuri A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning. Search on Bibsonomy ISVLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Yong Zhan, Yan Feng, Sachin S. Sapatnekar A fixed-die floorplanning algorithm using an analytical approach. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Zhaojun Wo, Israel Koren, Maciej J. Ciesielski Yield-aware Floorplanning. Search on Bibsonomy DSD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Jason Cong, Michail Romesis, Joseph R. Shinnerl Fast floorplanning by look-ahead enabled recursive bipartitioning. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Lei Cheng 0001, Liang Deng, Martin D. F. Wong Floorplanning for 3-D VLSI design. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani Fixed-outline floorplanning with constraints through instance augmentation. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003, Hsin-Hsien Ho Modem floorplanning with abutment and fixed-outline constraints. Search on Bibsonomy ISCAS (6) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Wei-Lun Hung, Yuan Xie 0001, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin Thermal-Aware Floorplanning Using Genetic Algorithms. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Shinn-Ying Ho, Shinn-Jang Ho, Yi-Kuang Lin, W. C.-C. Chu An orthogonal simulated annealing algorithm for large floorplanning problems. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
47Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Xu Xu 0001, Alexander Zelikovsky Multi-project reticle floorplanning and wafer dicing. Search on Bibsonomy ISPD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF multi-project wafers, reticle design, wafer dicing
47Martin D. F. Wong Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers. Search on Bibsonomy ICCD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
47Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani Integrated floorplanning with buffer/channel insertion for bus-based designs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
47Matthew Moe, Herman Schmit Floorplanning of pipelined array modules using sequence pairs. Search on Bibsonomy ISPD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF pipelined array, floorplan, sequence pair
47Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
47Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani Consistent floorplanning with hierarchical superconstraints. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
47Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
47I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong 0001 Integrated power supply planning and floorplanning. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
47John Marty Emmert, Akash Randhar, Dinesh Bhatia Fast Floorplanning for FPGAs. Search on Bibsonomy FPL The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
47Chang-Sheng Ying, Joshua Sook-Leung Wong An analytical approach to floorplanning for hierarchical building blocks layout [VLSI]. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
46Jackey Z. Yan, Natarajan Viswanathan, Chris Chu Handling complexities in modern large-scale mixed-size placement. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF incremental placement, mixed-size design, floorplanning
46Natarajan Viswanathan, Min Pan, Chris C. N. Chu FastPlace: an analytical placer for mixed-mode designs. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF mixed-mode placement, floorplanning, analytical placement
46Su-Wei Wu, Yao-Wen Chang Efficient power/ground network analysis for power integrity-driven design methodology. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF footnotesize floorplanning, power/ground network
42De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF wire bonding, floorplanning, system-in-package
42David Cuesta, José Luis Ayala, José Ignacio Hidalgo, Massimo Poncino, Andrea Acquaviva, Enrico Macii Thermal-aware floorplanning exploration for 3D multi-core architectures. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF 3D, floorplanning, MPSoC, temperature
42Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang T-trees: A tree-based representation for temporal and three-dimensional floorplanning. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF temporal floorplanning, Reconfigurable computing, partially dynamical reconfiguration
42Jyh-Perng Fang, Yang-Lang Chang, Chih-Chia Chen, Wen-Yew Liang, Tung-Ju Hsieh, Muhammad T. Satria, Chin-Chuan Han A Parallel Simulated Annealing Approach for Floorplanning in VLSI. Search on Bibsonomy ICA3PP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF FFA, Parallel Computing, Simulated Annealing, OpenMP, Floorplanning
42Jinzhu Chen, Guolong Chen, Wenzhong Guo A Discrete PSO for Multi-objective Optimization in VLSI Floorplanning. Search on Bibsonomy ISICA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF discrete PSO, MOP, floorplanning
42Yu-Ning Chang, Yih-Lang Li, Wei-Tin Lin, Wen-Nai Cheng Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction. Search on Bibsonomy ISPD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF crosstalk reduction, full-chip routing, gridless routing, implicit connection graph-based router, non-slicing floorplanning, detailed routing
42Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang Temporal floorplanning using the three-dimensional transitive closure subGraph. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF temporal floorplanning, Reconfigurable computing, partially dynamical reconfiguration
42Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani How does partitioning matter for 3D floorplanning? Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF partitioning, floorplanning, 3D IC, wire length
42Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu Optimal cell flipping in placement and floorplanning. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF flipping, placement, floorplanning, orientation, wirelength
42Jill H. Y. Law, Evangeline F. Y. Young Multi-bend bus driven floorplanning. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF bus planning, floorplanning, VLSI CAD
42Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar Microarchitecture-aware floorplanning using a statistical design of experiments approach. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF floorplanning, microarchitecture, wire pipelining
42Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim Profile-guided microarchitectural floorplanning for deep submicron processor design. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF microarchitectural planning, computer architecture, floorplanning
42Jingcao Hu, Yangdong Deng, Radu Marculescu System-Level Point-to-Point Communication Synthesis using Floorplanning Information. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF System-leve design, low-power, floorplanning, Communication synthesis, point-to-point communication
42Swanwa Liao, Mario Alberto López, Dinesh P. Mehta Constrained polygon transformations for incremental floorplanning. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF floorplanning, incremental design, rectilinear polygons
42Takayuki Yamanouchi, Kazuo Tamakashi, Takashi Kambe Hybrid floorplanning based on partial clustering and module restructuring. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF slicing structure, clustering, placement, floorplanning
42Susmita Sur-Kolay, Bhargab B. Bhattacharya Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning. Search on Bibsonomy FSTTCS The full citation details ... 1988 DBLP  DOI  BibTeX  RDF plane triangulated graphs, rectangular duals, slicing structures, algorithms, floorplanning, VLSI layout
40Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
40Lei Cheng 0001, Martin D. F. Wong Floorplan Design for Multimillion Gate FPGAs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Lei Cheng 0001, Martin D. F. Wong Floorplan design for multi-million gate FPGAs. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
40Kia Bazargan, Samjung Kim, Majid Sarrafzadeh Nostradamus: a floorplanner of uncertain designs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
40Kia Bazargan, Samjung Kim, Majid Sarrafzadeh Nostradamus: a floorplanner of uncertain design. Search on Bibsonomy ISPD The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
37Song Chen 0001, Zheng Xu, Takeshi Yoshimura A generalized V-shaped multilevel method for large scale floorplanning. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
37Tilen Ma, Evangeline F. Y. Young TCG-based multi-bend bus driven floorplanning. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
37Pradeep Fernando, Srinivas Katkoori An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
37Love Singhal, Elaheh Bozorgzadeh Novel Multi-Layer floorplanning for Heterogeneous FPGAs. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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