Search results for "LUT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
99	Murat Mese, Palghat P. Vaidyanathan	Tree-structured method for LUT inverse halftoning and for image halftoning.	IEEE Trans. Image Process.	2002	DBLP DOI BibTeX RDF
83	Chih-Hung Lin, Jiunn-Tsair Chen	Signal-Statistics-Based Look-Up-Table Spacing for Power Amplifier Linearization.	VTC Spring	2007	DBLP DOI BibTeX RDF
80	Takayuki Suyama, Hiroshi Sawada, Akira Nagoya	LUT-based FPGA Technology Mapping using Permissible Functions.	VLSI Design	1996	DBLP DOI BibTeX RDF	Permissible Functions, Techonology Mapping, FPGA, LUT
78	Umair F. Siddiqi, Sadiq M. Sait	Algorithm for parallel inverse halftoning using partitioning of Look-Up Table (LUT).	ISCAS	2008	DBLP DOI BibTeX RDF
78	In-Gook Chun	Look Up Table(LUT) Method for Halftone Image Watermarking.	IWDW	2005	DBLP DOI BibTeX RDF
78	Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi	SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	SPFD, collaboration of logic and physical design, global rewiring (GR), one-to-many rewiring (OMR), logic optimization
78	Murat Mese, Palghat P. Vaidyanathan	Look-up table (LUT) method for inverse halftoning.	IEEE Trans. Image Process.	2001	DBLP DOI BibTeX RDF
78	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	SRAM-based FPGA's: testing the LUT/RAM modules.	ITC	1998	DBLP DOI BibTeX RDF
73	Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose	Logic synthesis for a single large look-up table.	ICCD	1995	DBLP DOI BibTeX RDF	single large look-up table, LUT-based field-programmable gate array architectures, simulation time minimisation, compile-code, software simulation, field programmable gate arrays, Boolean function, logic design, logic synthesis, hardware accelerator, programmable logic arrays, table lookup, logic simulation, FPGA architectures, logic functions, on-chip memory, memory constraint
72	Xiao-Ping (Steven) Zhang, Kan Li, Xiaofeng Wang 0008	A Novel Look-Up Table Design Method for Data Hiding With Reduced Distortion.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
72	Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia	Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield.	IOLTS	2007	DBLP DOI BibTeX RDF
72	Daesun Oh, Keshab K. Parhi	Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check Codes.	SiPS	2006	DBLP DOI BibTeX RDF
72	Jason Cong, Yuzheng Ding	FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
68	Haixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong	Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations.	ISQED	2005	DBLP DOI BibTeX RDF
68	Elias Ahmed, Jonathan Rose	The effect of LUT and cluster size on deep-submicron FPGA performance and density.	FPGA	2000	DBLP DOI BibTeX RDF
63	Somsubhra Mondal, Seda Ogrenci Memik	Fine-grain leakage optimization in SRAM based FPGAs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	hierarchical LUT, FPGA, low power, leakage power
62	Xiaofeng Wang 0008, Xiao-Ping (Steven) Zhang	Minimum Distortion Look-Up Table Based Data Hiding.	ICME	2006	DBLP DOI BibTeX RDF
59	Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler	Numerical Function Generators Using LUT Cascades.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	LUT cascades, numerical function generators (NFGs), nonuniform segmentation, FPGA implementation, automatic synthesis
58	Jong-Bae Jeon, Sang-Hyeon Jin, Dong-Ju Kim, Kwang-Seok Hong	Facial Gender Classification Using LUT-Based Sub-images and DIE.	HCI (11)	2009	DBLP DOI BibTeX RDF	Difference Image Entropy, Gender Classification
58	Kai Zhu 0001	Post-route LUT output polarity selection for timing optimization.	FPGA	2007	DBLP DOI BibTeX RDF	optimization, timing, polarity, FPGA lookup table
58	Somsubhra Mondal, Seda Ogrenci Memik, Debasish Das	Hierarchical LUT structures for leakage power reduction (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
58	Maxim Teslenko, Elena Dubrova	Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth.	ICCAD	2004	DBLP DOI BibTeX RDF
58	Hiroshi Tsutsui, K. Hiwada, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura	A design of LUT-array-based PLD and a synthesis approach based on sum of generalized complex terms expression.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
58	Jason Cong, Yuzheng Ding	Combinational logic synthesis for LUT based field programmable gate arrays.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	FPGA, routing, synthesis, system design, decomposition, technology mapping, simplification, programmable logic, power minimization, logic optimization, delay modeling, delay minimization, computer-aided design of VLSI, area minimization
58	Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen	Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture.	ICCAD	1995	DBLP DOI BibTeX RDF
52	Matthew Collin Jordan, Ramachandran Vaidyanathan	Configurable decoders with application in fast partial reconfiguration of FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, decoder, look-up table, configurable logic
52	Sin Man Cheang, Kin-Hong Lee, Kwong-Sak Leung	Applying Genetic Parallel Programming to Synthesize Combinational Logic Circuits.	IEEE Trans. Evol. Comput.	2007	DBLP DOI BibTeX RDF
52	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura	A fast logic simulator using a look up table cascade emulator.	ASP-DAC	2006	DBLP DOI BibTeX RDF
52	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	Defect Analysis for Delay-Fault BIST in FPGAs.	IOLTS	2003	DBLP DOI BibTeX RDF
52	Artur Chojnacki, Lech Józwiak	High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures.	ISQED	2001	DBLP DOI BibTeX RDF
50	Wenyi Feng, Sinan Kaptanoglu	Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	cluster, FPGAs, entropy, interconnect, counting, PLDs, LUT
50	Wenyi Feng, Sinan Kaptanoglu	Designing efficient input interconnect blocks for LUT clusters using counting and entropy.	FPGA	2007	DBLP DOI BibTeX RDF	cluster, FPGAs, entropy, interconnect, counting, PLDs, LUT
49	Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen	An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.	ICCAD	1996	DBLP DOI BibTeX RDF	LUT-Based FPGA Technology Mapping, Area/Performance Trade-Off and Timing Driven FPGA Synthesis
49	Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya	A new method to express functional permissibilities for LUT based FPGAs and its applications.	ICCAD	1996	DBLP DOI BibTeX RDF	look-up table (LUT), functional permissibility, optimization, FPGA, routing
49	Aiguo Lu, Erik L. Dagless, Jonathan M. Saul	DART: delay and routability driven technology mapping for LUT based FPGAs.	ICCD	1995	DBLP DOI BibTeX RDF	DART, delay driven technology mapping, LUT based FPGAs, two-phased approach, routability directed delay-optimal mapping, stochastic routability analysis, delay-optimal mapping, field programmable gate arrays, delays, logic design, programmable logic arrays, table lookup, minimisation of switching nets
47	Jason Cong, Kirill Minkovich	LUT-based FPGA technology mapping for reliability (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	logic synthesis, error analysis, windowing, technology mapping, don't cares, fpga lookup table
47	Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko	WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	area flow, cut enumeration, edge flow, FPGA, technology mapping
47	Yu Hu 0002, Satyaki Das, Steven Trimberger, Lei He 0001	Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
47	Khalil Dayo, Abdul Qadeer Khan Rajput, Bhawani Shankar Chowdhry, Narinder P. Chowdhry	Impact of Cluster Size on Efficient LUT-FPGA Architecture for Best Area and Delay Trade-Off.	IMTIC	2008	DBLP DOI BibTeX RDF	CLBs, BLE, FPGA, Lookup table
47	David B. Thomas, Wayne Luk	High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	Uniform Random Numbers, Simulation, FPGA
47	Kan Li, Xiao-Ping Zhang 0002	A New LUT Watermarking Scheme with Near Minimum Distortion Based on the Statistical Modeling in the Wavelet Domain.	ICIC (2)	2005	DBLP DOI BibTeX RDF
47	Rohit Pandey, Santanu Chattopadhyay	Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach".	VLSI Design	2003	DBLP DOI BibTeX RDF
47	Jason Cong, Yean-Yow Hwang	Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
47	Andrzej Krasniewski	Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing.	DSD	2001	DBLP DOI BibTeX RDF
47	Shyue-Kung Lu, Cheng-Wen Wu	A novel approach to testing LUT-based FPGAs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
47	Chitrasena Bhat, Niranjan N. Chiplunkar	Heuristic Technology Mapper For Lut Based Fpgas.	VLSI Design	1999	DBLP DOI BibTeX RDF
47	Jason Cong, Yean-Yow Hwang	Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation.	FPGA	1998	DBLP DOI BibTeX RDF
47	Jason Cong, Yuzheng Ding	On Nominal Delay Minimization in LUT-based FPGA Technology Mapping.	FPGA	1995	DBLP DOI BibTeX RDF
43	Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer	Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
41	Yu-Chen Chen, Hou-Yu Pang, Kuen-Wen Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su	Via configurable three-input lookup-tables for structured ASICs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	via-configurable, layout, look-up-table, vlsi, structured ASIC
41	Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang	Scalable don't-care-based logic optimization and resynthesis.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, interpolation, windowing, technology mapping, boolean satisfiability, logic optimization
41	David M. Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Christopher Lane, Andy Lee, Philip Pan	Architectural enhancements in Stratix-IIITM and Stratix-IVTM.	FPGA	2009	DBLP DOI BibTeX RDF	power management, memory, fpga architecture, static power
41	Scott Melvin, Mohan Baro, Majed Jandali, Jacek Ilow	Improved Compensation of HPA Nonlinearities Using Digital Predistorters with Dynamic and Multi-dimensional LUTs.	CNSR	2008	DBLP DOI BibTeX RDF
41	Charan Litchfield, Peter Lee 0002, Richard J. Langley, John C. Batchelor	Logarithmic Codecs for Adaptive Beamforming in WCDMA Downlink Channels.	ISCAS	2007	DBLP DOI BibTeX RDF
41	Catherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu	How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs.	DAC	2007	DBLP DOI BibTeX RDF
41	Kuo-Liang Chung, Shih-Tung Wu	Inverse Halftoning Algorithm Using Edge-Based Lookup Table Approach.	IEEE Trans. Image Process.	2005	DBLP DOI BibTeX RDF
41	Dong-Woo Kang, Yang-Ho Cho, Myong-Young Lee, Tae-Yong Park, Yeong-Ho Ha	Color signal decomposition method using 3-D Gamut boundary of multi-primary display.	ICIP (1)	2005	DBLP DOI BibTeX RDF
41	Francisco-Javier Veredas, Jordi Carrabina	Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures.	PATMOS	2005	DBLP DOI BibTeX RDF
41	Canh Quang Tran, Hiroshi Kawaguchi 0001, Takayasu Sakurai	More than two orders of magnitude leakage current reduction in look-up table for FPGAs.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
41	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	High Quality TPG for Delay Faults in Look-Up Tables of FPGAs.	DELTA	2004	DBLP DOI BibTeX RDF
41	Shizhong Liu, Alan C. Bovik	Look-up-table based DCT domain inverse motion compensation.	ICIP (2)	2001	DBLP DOI BibTeX RDF
41	Amir H. Farrahi, Majid Sarrafzadeh	Complexity of the lookup-table minimization problem for FPGA technology mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
38	Shashidhar Thakur, D. F. Wong 0001	Simultaneous area and delay minimum K-LUT mapping for K-exact networks.	ICCD	1995	DBLP DOI BibTeX RDF	area/delay minimum K-LUT mapping, K-exact networks, technology mapping problem, lookup table FPGAs, area minimization problem, K-bounded networks, delay minimization problem, flow-map algorithm, field programmable gate arrays, computational complexity, complexity, NP-complete, logic design, polynomial time algorithm, programmable logic arrays, table lookup, minimisation of switching nets
37	Taiga Takata, Yusuke Matsunaga	A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, technology mapping
37	Jason Cong, Kirill Minkovich	LUT-based FPGA technology mapping for reliability.	DAC	2010	DBLP DOI BibTeX RDF	logic synthesis, error analysis, windowing, technology mapping, don't cares, FPGA lookup table
37	Hosung Kim, John Lillis	A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
37	Michael T. Frederick, Arun K. Somani	Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	carry chain, depth optimal mapping, logic chain
37	Taiga Takata, Yusuke Matsunaga	Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
37	Ricardo Chaves, Blagomir Donchev, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	BRAM-LUT Tradeoff on a Polymorphic DES Design.	HiPEAC	2008	DBLP DOI BibTeX RDF
37	Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton	Improvements to Technology Mapping for LUT-Based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
37	Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki	On LUT Cascade Realizations of FIR Filters.	DSD	2005	DBLP DOI BibTeX RDF
37	Tsutomu Sasao	Radix Converters: Complexity and Implementation by LUT Cascades.	ISMVL	2005	DBLP DOI BibTeX RDF
37	Krishna Prasad Raghuraman, Haibo Wang 0005, Spyros Tragoudas	A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs.	VLSI Design	2005	DBLP DOI BibTeX RDF
37	Varun Jindal, Alpana Agarwal	Carry Circuitry for LUT-Based FPGA.	VLSI Design	2004	DBLP DOI BibTeX RDF
37	Bo Wu 0001, Haizhou Ai, Chang Huang	LUT-Based Adaboost for Gender Classification.	AVBPA	2003	DBLP DOI BibTeX RDF	Adaboost, gender classification
37	Andrzej Krasniewski	On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
37	Frank Wolz, Reiner Kolla	Bubble Partitioning for LUT-Based Sequential Circuits.	FPL	2001	DBLP DOI BibTeX RDF
37	Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen	ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
37	Joerg Abke, Erich Barke	CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
37	Holger Kropp, Carsten Reuter	A Mapping Methodology for Code Trees onto LUT-Based FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
37	Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya	An Integrated Approach for Synthesizing LUT Networks.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
37	Igor Lemberski	Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
37	Wei-Kang Huang, Fred J. Meyer, Xiao-Tao Chen, Fabrizio Lombardi	Testing configurable LUT-based FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
37	A. R. Naseer, M. Balakrishnan, Anshul Kumar	Direct mapping of RTL structures onto LUT-based FPGA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
37	Balakrishna Kumthekar, Luca Benini, Enrico Macii, Fabio Somenzi	In-Place Power Optimization for LUT-Based FPGAs.	DAC	1998	DBLP DOI BibTeX RDF
37	Hyunchul Shin, Chunghee Kim	Performance-oriented technology mapping for LUT-based FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
37	Hannah Honghua Yang, D. F. Wong 0001	Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs.	ICCAD	1994	DBLP DOI BibTeX RDF
36	Ajay Anand Kumar, Bart Loeys, Gerarda Van De Beek, Nils Peeters, Wim Wuyts, Lut Van Laer, Geert Vandeweyer, Maaike Alaerts	varAmpliCNV: analyzing variance of amplicons to detect CNVs in targeted NGS data.	Bioinform.	2023	DBLP DOI BibTeX RDF
36	Diana M. Negoescu, Humberto González, Saad Eddin Al Orjany, Jilei Yang, Yuliia Lut, Rahul Tandra, Xiaowen Zhang, Xinyi Zheng, Zach Douglas, Vidita Nolkha, Parvez Ahammad, Gennady Samorodnitsky	Epsilon*: Privacy Metric for Machine Learning Models.	CoRR	2023	DBLP DOI BibTeX RDF
36	Irina Lut, Katie Harron, Pia Hardelid, Margaret O'brien, Jenny Woodman	'What about the dads?' Linking fathers and children in administrative data: A systematic scoping review.	Big Data Soc.	2022	DBLP DOI BibTeX RDF
36	Anatoliy Lut	Proof-of-Concept (PoC) Biometric-Based Decentralized Digital Identifiers.	IDC	2022	DBLP DOI BibTeX RDF
36	Wei Jin, Yan Zhao, Yun Qi, Hoi Lut Ho, Shoufei Gao, Yingying Wang	Photoacoustic Spectroscopy of Gas Filled Hollow Core Fiber.	OFC	2022	DBLP BibTeX RDF
36	Yuliia Lut, Michael Wang, Elissa M. Redmiles, Rachel Cummings	How we browse: Measurement and analysis of digital behavior.	CoRR	2021	DBLP BibTeX RDF
36	Yingzhen Hong, Haihong Bao, Wei Jin, Shoulin Jiang, Hoi Lut Ho, Shoufei Gao, Yingying Wang	Oxygen Gas Sensing with Photothermal Spectroscopy in a Hollow-Core Negative Curvature Fiber.	Sensors	2020	DBLP DOI BibTeX RDF
36	Wei Jin, Haihong Bao, Pengcheng Zhao, Yun Qi, Hoi Lut Ho	High Sensitivity Gas Detection with Microstructured Optical Fibres.	ICTON	2020	DBLP DOI BibTeX RDF
36	Rachel Cummings, Sara Krehbiel, Yuliia Lut, Wanrong Zhang 0001	Privately detecting changes in unknown distributions.	ICML	2020	DBLP BibTeX RDF
36	Rachel Cummings, Sara Krehbiel, Yuliia Lut, Wanrong Zhang 0001	Privately detecting changes in unknown distributions.	CoRR	2019	DBLP BibTeX RDF
36	Ajay Anand Kumar, Lut Van Laer, Maaike Alaerts, Amin Ardeshirdavani, Yves Moreau, Kris Laukens, Bart Loeys, Geert Vandeweyer	pBRIT: gene prioritization by correlating functional and phenotypic annotations through integrative data fusion.	Bioinform.	2018	DBLP DOI BibTeX RDF
36	Kristl Vonck, Mathieu Sprengers, Evelien Carrette, Ine Dauwe, Marijke Miatton, Alfred Meurs, Lut Goossens, Veerle de Herdt, Rik Achten, Evert Thiery, Robrecht Raedt, Dirk Van Roost, Paul Boon 0001	A Decade of Experience with Deep Brain Stimulation for patients with Refractory Medial Temporal Lobe epilepsy.	Int. J. Neural Syst.	2013	DBLP DOI BibTeX RDF
36	Walker H. Land, John J. Heine, Mark J. Embrechts, Tom Smith, Robert Choma, Lut Wong	New approach to breast cancer CAD using partial least squares and kernel-partial least squares.	Medical Imaging: Image Processing	2005	DBLP DOI BibTeX RDF