Search results for "MOSFET"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
89	Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita	High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dopant-segregated schottky transistor, nonvolatile configurable memory
89	Shaoxi Wang, Rui He, Lihong Zhang	MOSFET model assessment for submicron and nanometer bulk-driven applications.	CCECE	2009	DBLP DOI BibTeX RDF
71	Adrian M. Ionescu, V. Pott, R. Fritschi, Kaustav Banerjee, Michel J. Declercq, Philippe Renaud, C. Hibert, Philippe Flückiger, G. A. Racine	Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture.	ISQED	2002	DBLP DOI BibTeX RDF
68	Michael J. Van der Tol, Savvas G. Chamberlain	Buried-channel MOSFET model for SPICE.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
67	Deyuan Xiao, Gary Chen, Roger Lee, Yung Liu, ChiCheong Shen	Planar split dual gate MOSFET.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	novel device, planar split dual gate, tunable sub-threshold swing, MOSFET
67	Feng Liu, Jin He 0003, Yue Fu, Jinhua Hu, Wei Bian, Yan Song, Xing Zhang 0002, Mansun Chan	Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes.	ISQED	2008	DBLP DOI BibTeX RDF	double-gate MOSFET, drain current, compact model
60	Yogesh Singh Chauhan, François Krummenacher, Renaud Gillon, Benoit Bakeroot, Michel J. Declercq, Adrian M. Ionescu	A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling.	VLSI Design	2007	DBLP DOI BibTeX RDF
57	Michael Walter Payton, Fat Duen Ho	A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation PART-I MOSFETs and CMOS inverters.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
57	Shinji Odanaka	Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
57	Kyu-Il Lee, Jinsoo Kim, Young June Park, Hong-Shick Min	Simple frequency-domain analysis of MOSFET-includingnonquasi-static effect.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
57	R. P. Suresh, P. Venugopal, S. Tamizh Selvam, S. Potla	Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFET.	VLSI Design	1996	DBLP DOI BibTeX RDF
56	Hamilton Klimach, Márcio C. Schneider, Carlos Galup-Montoro	A test chip for automatic MOSFET mismatch characterization.	SBCCI	2006	DBLP DOI BibTeX RDF	matching, characterization, analog design, MOSFET, mismatch
56	Bo Shen, Sunil P. Khatri, Takis Zourntos	Implementation of MOSFET based capacitors for digital applications.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	MOSFET capacitor, constant capacitance, reference capacitor
56	Carlos Galup-Montoro, Márcio C. Schneider, Viriato C. Pahim	Fundamentals of next generation compact MOSFET models.	SBCCI	2005	DBLP DOI BibTeX RDF	MOSFET model, inversion-charge model, surface potential model, compact model
46	Yu Cao, Colin C. McAndrew	MOSFET modeling for 45nm and beyond.	ICCAD	2007	DBLP DOI BibTeX RDF
46	Ryuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita	Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation.	ISVLSI	2006	DBLP DOI BibTeX RDF
46	Anurag Chaudhry, M. Jagadesh Kumar	Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET using Two-Dimensional Numerical Simulation Studies.	VLSI Design	2004	DBLP DOI BibTeX RDF
46	Rafael M. Coitinho, Luiz H. Spiller, Márcio C. Schneider, Carlos Galup-Montoro	MOSFET Model with a Small Set of Parameters for Electronic Engineering Education.	MSE	2001	DBLP DOI BibTeX RDF
46	Brian S. Cherkauer, Eby G. Friedman	Channel width tapering of serially connected MOSFET's with emphasis on power dissipation.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
43	Geoffrey C.-F. Yeap	Leakage current in low standby power and high performance devices: trends and challenges.	ISPD	2002	DBLP DOI BibTeX RDF	gate tunneling leakage, low standby power, off-state sub-threshold leakage, system-on-a-ship (SoC), high performance, CMOS technology, leakage current
42	Yangyuan Wang, Xing Zhang 0002, Xiaoyan Liu, Ru Huang	Novel devices and process for 32 nm CMOS technology and beyond.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	high-k, non-planar MOSFET, quasi-ballistic transport, CMOS technology, metal gate
42	Hyunsik Im	Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model).	ISLPED	2002	DBLP DOI BibTeX RDF	?-power model, MOSFET modeling, Saturation current
42	Tuck-Boon Chan, Puneet Gupta 0001	On Electrical Modeling of Imperfect Diffusion Patterning.	VLSI Design	2010	DBLP DOI BibTeX RDF	non-rectangular mosfet, active layer rounding, trapezoid mosfet, imperfect diffusion patterning
35	David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat	Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic.	ISLPED	2009	DBLP DOI BibTeX RDF	short-channel effects, subthreshold logic, variability, cmos digital integrated circuits, ultra-low power, gate leakage
35	Hamed Aminzadeh, Mohammad Danaie, Reza Lotfi	Design of high-resolution MOSFET-only pipelined ADCs with digital calibration.	DATE	2007	DBLP DOI BibTeX RDF
35	Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta	Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design.	VLSI Design	2007	DBLP DOI BibTeX RDF
35	Tatjana V. Pesic, Nebojsa D. Jankovic	A compact nonquasi-static MOSFET model based on the equivalent nonlinear transmission line.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
35	Yuh-Shyan Hwang, Jiann-Jong Chen, Wen-Ta Lee	High-order linear transformation MOSFET-C filters using operational transresistance amplifiers.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
35	Yulei Weng, Alex Doboli	Digital cell macro-model with regular substrate template and EKV based MOSFET model.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF
35	Bhavana Jharia, Sankar Sarkar, Rajendra Prasad Agarwal	Analytical Study of Impact Ionization and Subthreshold Current in Submicron n-MOSFET.	ISQED	2005	DBLP DOI BibTeX RDF
35	Virgínia Helena Varotto Baroncini, Oscar da Costa Gouveia-Filho	Design of RF CMOS low noise amplifiers using a current based MOSFET model.	SBCCI	2004	DBLP DOI BibTeX RDF	noise, CMOS, RF, LNA
35	Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman	Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization.	ISQED	2003	DBLP DOI BibTeX RDF
35	Abhisek Dixit, V. Ramgopal Rao	A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime.	VLSI Design	2003	DBLP DOI BibTeX RDF
35	A. B. Bhattacharyya, Shrutin Ulman	PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
35	Thomas Tille, Jens Sauerbrey, Doris Schmitt-Landsiedel	A low-voltage MOSFET-only Sigma-Delta modulator for speech band applications using depletion-mode MOS-capacitors in combined series and parallel compensation.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
35	Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru	Model-adaptable MOSFET parameter-extraction method using an intermediate model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
35	Raymond S. Winton, William R. Bandy	A simple, continuous, analytical charge/capacitance model for the short-channel MOSFET.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
35	Mohamed A. Imam, Mohamed A. Osman, Ashraf A. Osman	MOSFET global modeling for deep submicron devices with a modified BSIM1 SPICE model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
35	William R. Bandy, Raymond S. Winton	A new approach for modeling the MOSFET using a simple, continuous analytical expression for drain conductance which includes velocity-saturation in a fundamental way.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
35	Chun-Jung Chen, Wu-Shiung Feng	Relaxation-based transient sensitivity computations for MOSFET circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
35	Mitiko Miura-Mattausch	Analytical MOSFET model for quarter micron technologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
35	Shiuh-Wuu Lee	A proposed method for determining a MOSFET gate electrode's bottom dimension and the on-state fringing capacitance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
35	Takayasu Sakurai, Bill Lin 0001, A. Richard Newton	Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
35	Shiuh-Wuu Lee	Universality of mobility-gate field characteristics of electrons in the inversion charge layer and its application in MOSFET modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
35	Hiroo Masuda, Yukio Aoki, Jun'ichi Mano, Osamu Yamashiro	MOSTSM: a physically based charge conservative MOSFET model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
35	James A. Barby, Jirí Vlach, Kishore Singhal	Polynomial splines for MOSFET model approximation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
35	Ross A. Williams, Deva N. Pattanayak	ADAM: a two dimensional, two-carrier MOSFET simulator based on generalized stream functions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
35	Sudipta Sarkar, Ananda S. Roy, Santanu Mahapatra	A Non Quasi-static Small Signal Model for Long Channel Symmetric DG MOSFET.	VLSI Design	2010	DBLP DOI BibTeX RDF	Non Quasi-Static Analysis, Double-Gate MOSFET
35	Raúl Valín Ferreiro, Natalia Seoane, Manuel Aldegunde, Antonio J. García-Loureiro	The MOSFET Virtual Organisation: Grid Computing for Simulation in Nanoelectronics.	eScience	2009	DBLP DOI BibTeX RDF	DG-SOI MOSFET, EGI, NGI-es, Grid computing, Monte Carlo Simulation, Nanoelectronics
35	Hamilton Klimach, Carlos Galup-Montoro, Márcio C. Schneider, Alfredo Arnaud	MOSFET Mismatch Modeling: A New Approach.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	mismatch compact model, simulation, matching, integrated circuit design, MOSFET
35	Oleg Semenov, Arman Vassighi, Manoj Sachdev	Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	MOSFET leakage, reliability, quality, CMOS integrated circuits, I DDQ testing
32	Toshiro Akino, Takashi Hamahata	A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation.	PATMOS	2006	DBLP DOI BibTeX RDF
32	Ranjith Kumar, Volkan Kursun	Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies.	ISCAS	2006	DBLP DOI BibTeX RDF
32	Rainer Krenzke, Cang Ji, Dirk Killat	A 36-V H-bridge driver interface in a standard 0.35-μm CMOS process.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
32	Wei Guo, Daquan Huang	Noise and linearity analysis for a 1.9 GHz CMOS LNA.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
32	Saed G. Younis, Thomas F. Knight Jr.	Non-dissipative rail drivers for adiabatic circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	driver circuits, distributed parameter networks, lumped parameter networks, passive networks, nondissipative rail drivers, adiabatic circuits, CMOS charge recovery logic, energy dissipation per operation, SCRL circuits, rail waveform generation, rail driver circuit, multiple harmonics, harmonic rail driver, passive reactive components, trimmed transmission line segments, CMOS logic circuits, CMOS circuits, harmonics
32	Kiyoo Itoh 0001	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
32	S. Yoshitomi	Challenges to Accuracy for the Design of Deep-Submicron RF-CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	130 nm, RF-CMOS analog circuits, MOSFET models, EKV3.0 model, electro magnetic effects, building blocks, deep submicron
28	Ashkan Abdipour, Mohsen Hayati, Andrei Grebennikov	Implementation of class-E/F3 power amplifiers based on the variations of the MOSFET grading coefficient, built-in potential and output capacitance along with their roles in MOSFET selectivity.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
28	Yuta Ikutajima, Hirotaka Koizumi	Choke-less Class-E Oscillator Using p-MOSFET and n-MOSFET.	ISIE	2023	DBLP DOI BibTeX RDF
28	Oussama Zobiri, Abdelmalek Atia, Müslüm Arici	A critical evaluation based on Lattice Boltzmann method of nanoscale thermal behavior inside MOSFET and SOI-MOSFET.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
28	Kyuhyun Cha, Jongwoon Yoon, Jinhee Cheon, Kwangsoo Kim	The limitation of the Split-Gate MOSFET(SG-MOSFET) at 3.3kV.	ICEIC	2021	DBLP DOI BibTeX RDF
28	Giacomo Barletta, V. C. Ngwan	Study of gate leakage mechanism in advanced charge-coupled MOSFET (CC-MOSFET) technology.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
28	N. M. Roscoe, Y. Zhong, Stephen J. Finney	Comparing SiC MOSFET, IGBT and Si MOSFET in LV distribution inverters.	IECON	2015	DBLP DOI BibTeX RDF
28	Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang	Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2014	DBLP DOI BibTeX RDF
28	Tsuyoshi Funaki	A study on gate voltage fluctuation of MOSFET induced by switching operation of adjacent MOSFET in high voltage power conversion circuit.	EMC Compo	2013	DBLP DOI BibTeX RDF
28	Phanumas Khumsat, Apisak Worapishet	A 0.5-V R-MOSFET-C Filter Design Using Subthreshold R-MOSFET Resistors and OTAs With Cross-Forward Common-Mode Cancellation Technique.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
28	Viranjay M. Srivastava, Kalyan S. Yadav, Ghanshyam Singh	Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
28	K. Ragini, M. Satyam, B. C. Jinaga	Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Universal Logic Gates	CoRR	2010	DBLP BibTeX RDF
25	Farhad Alibeygi Parsan, Ahmad Ayatollahi, Adib Abrishamifar	Investigating the linearity of MOSFET-only switched-capacitor DeltaSigma modulators under low-voltage condition.	DDECS	2009	DBLP DOI BibTeX RDF
25	Mawahib Hussein Sulieman	On the Reliability of Interconnected CMOS Gates Considering MOSFET Threshold-Voltage Variations.	NanoNet	2009	DBLP DOI BibTeX RDF	Reliability, CMOS, threshold voltage, gates
25	Mario Alfredo Reyes-Barranca, Salvador Mendoza-Acevedo, Alejandro Ávila-García, José Luis González-Vidal, Luis M. Flores-Nava	Floating gate MOSFET circuit design for a monolithic MEMS GAS sensor.	SBCCI	2009	DBLP DOI BibTeX RDF	FGMOS, gas sensor, MEMS
25	Yongji Jiang, Garrett S. Rose	A dual-MOSFET equivalent resistor thermal sensor.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	integrated circuits, dynamic thermal management, vlsi, temperature sensors
25	Mohammad Danaie, Hamed Aminzadeh, Sasan Naseh	On the Linearization of MOSFET Capacitors.	ISCAS	2007	DBLP DOI BibTeX RDF
25	Hamid Charkhkar, Alireza Asadi, Reza Lotfi	A 1.8V, 10-bit, 40MS/s MOSFET-only pipeline analog-to-digital converter.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Yun Seop Yu, H. W. Kye, B. N. Song, S.-J. Kim, J.-B. Choi	A new multi-valued static random access memory (MVSRAM) with hybrid circuit consisting of single-electron (SE) and MOSFET.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Phanumas Khumsat, Apisak Worapishet	High-gain current amplifiers for low-power MOSFET-C filters.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Il Song Han	A Pulse-based Neural Hardware Implementation Based on the Controlled Conductance by MOSFET Circuit.	IJCNN	2006	DBLP DOI BibTeX RDF
25	Kyu-Il Lee, Chanho Lee, Hyungsoon Shin, Young June Park, Hong-Shick Min	Efficient frequency-domain simulation technique for short-channel MOSFET.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
25	Masahiro Murakawa, Mitiko Miura-Mattausch, Tetsuya Higuchi	Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithm.	ASP-DAC	2005	DBLP DOI BibTeX RDF
25	Fábio A. Pereira, Mário C. G. de Oliveira, Ana Isabela Araújo Cunha	CMOS analog current-mode multiplier based on the advanced compact MOSFET model.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
25	Somnath Sengupta	Analytical expression of HD3 due to non-linear MOS switch in MOSFET-C sample and hold circuits.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
25	Michael Walter Payton, Fat Duen Ho	A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
25	Mitiko Miura-Mattausch	MOSFET modeling for RF-CMOS design.	ASP-DAC	2004	DBLP DOI BibTeX RDF
25	Ferdinando Bedeschi, Edoardo Bonizzoni, Andrea Fantini, Claudio Resta, Guido Torelli	A low-power low-voltage MOSFET-only voltage reference.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
25	Shelly Xiao, José B. Silva, Un-Ku Moon, Gabor C. Temes	A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
25	Malgorzata Langer, Zbigniew Lisik, Ewa Raj, Nam Kyun Kim, Jan Szmidt	Simulations for Thermal Analysis of MOSFET IPM Using IMS Substrate.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF
25	R. Srinivasan, Navakanta Bhat	Effect of Scaling on the Non-quasi-static Behaviour of the MOSFET for RF IC's.	VLSI Design	2003	DBLP DOI BibTeX RDF
25	Rodrigo L. Oliveira Pinto, Franco Maloberti	Novel Design Methodology for Short-Channel MOSFET Analog Circuits.	IWSOC	2003	DBLP DOI BibTeX RDF
25	Koichi Nose, Takayasu Sakurai	Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.	ISLPED	2002	DBLP DOI BibTeX RDF
25	Dmitrii V. Chernov, Marian K. Kazimierczuk, Vladimir G. Krizhanovski	Class-E MOSFET low-voltage power oscillator.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
25	Hiroki Sato, Akira Hyogo, Keitaro Sekine	A Vt-zero equivalent MOSFET and its applications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
25	Yigang He, Jinguang Jiang, Yichuang Sun	CMOS R-MOSFET-C fourth-order Bessel filter with accurate group delay.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
25	Tsung-Sum Lee, Tai-Hua Chen	Two low-voltage fully differential MOSFET-C voltage-controlled oscillators for frequency tuning.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
25	Luís Cléber C. Marques, Carlos Galup-Montoro, Sidnei Noceti Filho, Márcio C. Schneider	A switched-MOSFET filter for application in hearing aid devices.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
25	Luís Cléber C. Marques, Carlos Galup-Montoro, Sidnei Noceti Filho, Márcio C. Schneider	Switched-MOSFET technique for programmable filters operating at low-voltage supply.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
25	Nikolaos Nastos, Yannis Papananos	A CAD tool for benchmarking MOSFET models.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
25	Asen Asenov, Andrew R. Brown, John H. Davies, Subhash Saini	Hierarchical approach to "atomistic" 3-D MOSFET simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
25	Louiza Sellami, Robert W. Newcomb	A MOSFET bridge fluid biosensor.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
25	Yuhua Cheng, Kai Chen 0002, Kiyotaka Imai, Chenming Hu	A unified MOSFET channel charge model for device modeling in circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF