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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 3990 publication records. Showing 3990 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
93 | Johann Großschädl |
The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 16th Annual Computer Security Applications Conference (ACSAC 2000), 11-15 December 2000, New Orleans, Louisiana, USA, pp. 384-393, 2000, IEEE Computer Society, 0-7695-0859-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency |
92 | W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi |
A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 398-402, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron |
88 | Y. Hamid, Martin Langhammer |
Multiplier architectures for FPGA double precision functions (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 287, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
fpga, floating point |
75 | Nuno Bandeira, Ken Vaccaro, James A. Howard |
A Two's Complement Array Multiplier Using True Values of the Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(8), pp. 745-747, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
Pezaris multiplier, Baugh-Wooley multiplier, celluar-subtractor multiplier, Array multiplier, parallel multiplier, binary multiplication |
75 | Chang Han Kim, Yongtae Kim, Nam Su Chang, IlHwan Park |
Modified Serial Multipliers for Type-IV Gaussian Normal Bases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INDOCRYPT ![In: Progress in Cryptology - INDOCRYPT 2005, 6th International Conference on Cryptology in India, Bangalore, India, December 10-12, 2005, Proceedings, pp. 375-388, 2005, Springer, 3-540-30805-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
serial multiplier, Finite fields, ECC, Massey-Omura multiplier, Gaussian Normal Basis |
71 | S. M. Aziz |
A C-testable modified Booth's array multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 278-282, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
C-testable multiplier, modified Booth algorithm, gate-level design, parallel processing, logic testing, integrated circuit testing, digital arithmetic, stuck-at faults, CMOS logic circuits, multiplying circuits, logic arrays, array multiplier, parallel multiplier |
66 | Shreesha Srinath, Katherine Compton |
Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 51-58, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
asymmetric multipliers, composable multipliers, multiplier design |
66 | Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001 |
Design of a radix-2m hybrid array multiplier using carry save adder format. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 172-177, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
hybrid multiplier, low power, carry save adder |
66 | Xu Zhou, Zhimin Tang |
A New Architecture of a Fast Floating-Point Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Programming Technologies, 5th International Workshop, APPT 2003, Xiamen, China, September 17-19, 2003, Proceedings, pp. 23-30, 2003, Springer, 3-540-20054-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Floating-point Multiplier, Processor |
66 | Arash Reyhani-Masoleh, M. Anwarul Hasan |
A New Construction of Massey-Omura Parallel Multiplier over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(5), pp. 511-520, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
optimal normal bases, Finite field, Massey-Omura multiplier, all-one polynomial |
63 | Peter Kornerup |
A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(8), pp. 892-898, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
systolic linear-array multiplier, right-shift algorithms, multiplier cell, digit-product terms, least significant digit first, active elements, module-multiplier, Montgomery module-reduction, RSA encryption, modular division, cryptography, logic design, systolic arrays, systolic array, digital arithmetic, multiplying circuits, latches, modular inverses, Hensel codes, digit-serial multiplier |
60 | Hyeong-Ju Kang, In-Cheol Park |
Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 693-696, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
59 | Sandeep S. Kumar, Thomas J. Wollinger, Christof Paar |
Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(10), pp. 1306-1311, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
least significant digit multiplier, elliptic/hyperelliptic curve cryptography, public key cryptography, digit serial multiplier, Bit serial multiplier |
59 | Johann Großschädl |
A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2001, Third International Workshop, Paris, France, May 14-16, 2001, Proceedings, pp. 202-219, 2001, Springer, 3-540-42521-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
iterative modulo multiplication, polynomial basis representation, bit-serial multiplier architecture, smart card crypto-coprocessor, Elliptic curve cryptography, finite field arithmetic |
59 | Eric M. Schwarz, Robert M. Averill III, Leon J. Sigal |
A Radix-8 CMOS S/390 Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 2-9, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Booth algorithm, computer arithmetic, multiplication, multiplier, floating-point unit |
59 | Belle W. Y. Wei, He Du, Honglu Chen |
A complex-number multiplier using radix-4 digits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 84-, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
complex-number multiplier, radix-4 digits, arithmetic datapath, complex-number digital signal processor, binary signed digits, fast multiplication, compact layout, three-multiplication scheme, radix-4 operands, delays, delay, encoding, digital arithmetic, multiplying circuits, binary additions, coding scheme |
59 | George A. Hadgis, P. R. Mukund |
A novel CMOS monolithic analog multiplier with wide input dynamic range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 310-314, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
analogue multipliers, circuit feedback, CMOS monolithic analog multiplier, input dynamic range, voltage-controlled variable linear resistor, feedback network, PSpice simulation results, circuit analysis computing, linearity, SPICE, operational amplifiers, operational amplifier, CMOS analogue integrated circuits |
58 | Alexandre F. Tenca, Georgi Todorov, Çetin Kaya Koç |
High-Radix Design of a Scalable Modular Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2001, Third International Workshop, Paris, France, May 14-16, 2001, Proceedings, pp. 185-201, 2001, Springer, 3-540-42521-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
modular multiplier, montgomery multiplier, high-radix, scalable architecture |
58 | Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar |
A multiplier generator for Xilinx FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 322-323, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs |
56 | Marcelo E. Kaihara, Naofumi Takagi |
Bipartite Modular Multiplication Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(2), pp. 157-164, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Algorithms, Computer arithmetic |
56 | Nicola Petra, Davide De Caro, Antonio G. M. Strollo |
A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(11), pp. 1470-1483, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
VLSI, High-Performance, Digital, Reed-Solomon codes, Arithmetic, finite field multiplication, polynomial basis |
56 | Jongsun Park 0001, Khurram Muhammad, Kaushik Roy 0001 |
High-performance FIR filter design based on sharing multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(2), pp. 244-253, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
55 | Arash Reyhani-Masoleh, M. Anwarul Hasan |
On Low Complexity Bit Parallel Polynomial Basis Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2003, 5th International Workshop, Cologne, Germany, September 8-10, 2003, Proceedings, pp. 189-202, 2003, Springer, 3-540-40833-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Finite or Galois field, Mastrovito multiplier, pentanomial, trinomial and equally-spaced polynomial, polynomial basis |
54 | M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas |
New and Improved Architectures for Montgomery Modular Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mob. Networks Appl. ![In: Mob. Networks Appl. 12(4), pp. 281-291, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reconfigurable multiplier, scalable multiplier, RSA, ECC, carry save adders, Montgomery modular multiplication |
53 | Charles Tsen, Sonia González-Navarro, Michael J. Schulte, Brian J. Hickmann, Katherine Compton |
A Combined Decimal and Binary Floating-Point Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 8-15, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
53 | Martin Novotný, Jan Schmidt |
General Digit-Serial Normal Basis Multiplier with Distributed Overlap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 94-101, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
53 | Chip-Hong Chang, Ravi Kumar Satzoda, Swaminathan Sekar |
A novel multiplexer based truncated array multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 85-88, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
53 | Lei Zhou, Yong Ping Xu, Fujiang Lin |
A gigahertz wideband CMOS multiplier for UWB transceiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5087-5090, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
53 | Kip C. Killpack, Eric Mercer, Chris J. Myers |
A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA, pp. 188-201, 2001, IEEE Computer Society, 0-7695-1037-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
53 | Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang |
Low-power fixed-width array multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 307-312, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
fixed-width multiplier, left-to-right multiplier, reduced-width multiplier, low power |
53 | Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang |
Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 492-499, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams |
52 | Chua-Chin Wang, Gang-Neng Sung |
Low-Power Multiplier Design Using a Bypassing Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(3), pp. 331-338, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Low power multiplier, Timing control, Partial product, Bypassing |
52 | Sun-Mi Park, Ku-Young Chang, Dowon Hong |
Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(9), pp. 1211-1215, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
shifted polynomial basis, irreducible pentanomial, finite field arithmetic, Bit-parallel multiplier |
52 | Ku-Young Chang, Dowon Hong, Hyun Sook Cho |
Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(12), pp. 1628-1630, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Karatsuba method, AOP, finite field arithmetic, redundant representation, Bit-parallel multiplier |
52 | Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin |
Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(5), pp. 539-549, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
cryptography, fault-tolerant computing, fault detection, finite fields, multiplier, single stuck-at fault |
52 | Yeshwant Kolla, Yong-Bin Kim, John Carter |
A novel 32-bit scalable multiplier architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 241-244, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
CMOS VLSI, architecture, multiplier |
52 | Hak-soo Yu, Jacob A. Abraham |
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 441-446, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
3-bit-scan, power-delay-area tradeoffs, synchronous sequential, multiplier, partial product |
52 | Bong-Il Park, In-Cheol Park, Chong-Min Kyung |
A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 243-, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Booth algorithm, Carry-Save Adder and Wallace Tree, Multiplier |
51 | Dimitris Bekiaris, Kiamal Z. Pekmestzi, Christos A. Papachristou |
A high-speed radix-4 multiplexer-based array multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 115-118, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
modified booth, multiplexer-based, radix-4 multiplier, array multiplier |
50 | Ron S. Waters, Earl E. Swartzlander Jr. |
A Reduced Complexity Wallace Multiplier Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 59(8), pp. 1134-1137, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
High-speed multiplier, Wallace multiplier, Dadda multiplier |
49 | Peter-Michael Seidel, Lee D. McFearin, David W. Matula |
Binary Multiplication Radix-32 and Radix-256. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 23-32, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
48 | Soonhak Kwon, Kris Gaj, Chang Hoon Kim, Chun Pyo Hong |
Efficient Linear Array for Multiplication in GF(2m) Using a Normal Basis for Elliptic Curve Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004. Proceedings, pp. 76-91, 2004, Springer, 3-540-22666-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
finite field, elliptic curve cryptography, Massey-Omura multiplier, Gaussian normal basis, critical path delay |
46 | Brian J. Hickmann, Andrew Krioukov, Michael J. Schulte, Mark A. Erle |
A parallel IEEE P754 decimal floating-point multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 296-303, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Chih-Hsing Lin, Ching-Te Chiu |
A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3888-3891, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Saurabh Singh, K. Radhakrishna Rao |
Low Voltage Analogue Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1772-1775, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Sai Mohan Kilambi, Behrouz Nowrouzian |
A Genetic Algorithm Employing Correlative Roulette Selection for Optimization of FRM Digital Filters over CSD Multiplier Coefficient Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 732-735, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Bo Yang 0010, Nikhil Joshi, Ramesh Karri |
A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 280, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng |
Integrated algorithmic logical and physical design of integer multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1014-1017, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
booth, interconnect, partial product, TDM |
46 | Amir Khatibzadeh, Kaamran Raahemifar |
A Novel Design of a 6-GHz 8 X 8-b Pipelined Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 387-391, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Magnus Själander, Henrik Eriksson, Per Larsson-Edefors |
An Efficient Twin-Precision Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 30-33, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
46 | Jin-Hua Hong, Cheng-Wen Wu |
Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(3), pp. 474-484, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Süleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale |
Design guidelines for reconfigurable multiplier blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 293-296, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Wonjong Kim, Seungchul Kim, Hanjin Cho, Kwang-youb Lee |
A fast-serial finite field multiplier without increasing the number of registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 157-160, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Ahmad A. Hiasat |
New Efficient Structure for a Modular Multiplier for RNS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(2), pp. 170-174, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
hardware requirements, VLSI, computer arithmetic, Residue number system, time delay, modular multiplication |
46 | Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy 0001 |
Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 230-235, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
46 | Vesselin K. Vassilev, Julian F. Miller, Terence C. Fogarty |
On the Nature of Two-Bit Multiplier Landscapes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), July 19-21, 1999, Pasadena, CA, USA, pp. 36-45, 1999, IEEE Computer Society, 0-7695-0256-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
46 | Dinesh Somasekhar, V. Visvanathan |
A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(4), pp. 415-422, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
46 | Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert Felber, Matthias Braendli |
Multi-gigabit GCM-AES Architecture Optimized for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings, pp. 227-238, 2007, Springer, 978-3-540-74734-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Galois/Counter Mode (GCM), hybrid multiplier, Field Programmable Gate Array (FPGA), Very Large Scale Integration (VLSI), Advanced Encryption Standard (AES), high throughput, digit-serial multiplier, bit-parallel multiplier |
45 | Tae Ho Kim, Sang Chul Kim, Chang Hoon Kim, Chun Pyo Hong |
Scalable Montgomery Multiplier for Finite Fields GF(p) and GF(2^m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 458-461, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Multi-Precision CSA, Scalable Multiplier, VLSI, Montgomery Multiplication |
45 | Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin |
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(2), pp. 143-150, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
cryptography, fault-tolerant computing, fault detection, multiplier, finite fields arithmetic |
45 | Yijun Liu, Stephen B. Furber |
The design of a low power asynchronous multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 301-306, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Booth's algorithm, low power, benchmark, multiplier, asynchronous logic |
45 | Syed Mahfuzul Aziz, C. N. Basheer, Joarder Kamruzzaman |
A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 504-506, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Modified Booth, Generic, Synthesis, VHDL, Multiplier, C-Testable |
45 | Berk Sunar, Çetin Kaya Koç |
An Efficient Optimal Normal Basis Type II Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(1), pp. 83-87, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Galois field, space complexity, optimal normal basis, Massey-Omura multiplier |
45 | Rong Lin |
A Reconfigurable Low-Power High-Performance Matrix Multiplier Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 321-328, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power CMOS circuits, parallel counter-multiplier circuits, reconfigurable architecture, Matrix multiplication |
45 | Ranjeet Ranade, Sanjay Bhandari, A. N. Chandorkar |
VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 318-319, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Digital Multiplier and Adder, VLSI Implementation of Neural Networks, Artificial Neural Networks (ANN) |
45 | Charles U. Martel, Vojin G. Oklobdzija, R. Ravi 0001, Paul F. Stelling |
Design Strategies for Optimal Multiplier Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 42-49, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Algorithms, Circuit design, Partial product reduction, Multiplier design |
44 | Zhijun Huang, Milos D. Ercegovac |
High-Performance Low-Power Left-to-Right Array Multiplier Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(3), pp. 272-283, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Left-to-right array multiplier, tree multiplier, layout regularity, low-power design, high-performance design |
44 | Mallika De, Bhabani P. Sinha |
Testing of a parallel ternary multiplier using I2L logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 387-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
integrated injection logic, parallel ternary multiplier, I/sup 2/L logic, multivalued I/sup 2/L circuits, input balanced ternary full adder, precarry generator, multivalued current inputs, multivalued current outputs, generated test sets, skew fault, fault diagnosis, logic testing, design for testability, logic design, digital arithmetic, fault location, stuck-at fault, generalized model, adders, adder, multiplying circuits, multivalued logic circuits, test sets, parallel multiplier |
43 | Abner Corrêa Barros, Victor Wanderley Costa de Medeiros, Viviane Lucy Santos de Souza, Paulo Sérgio Brandão do Nascimento, Ângelo Mazer, João Paulo Fernandes Barbosa, Bruno P. Neves, Ismael Santos 0001, Manoel Eusébio de Lima |
Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 40-45, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, scientific computing, floating-point, HPC |
43 | Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José Monteiro 0001, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis |
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, pp. 25-39, 2005, Springer, 978-0-387-73660-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu |
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 245-269, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
generator, BIST, computer arithmetic, polynomials, VLSI design, multiplication, division |
42 | Meng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou |
Sub-word and reduced-width Booth multipliers for DSP applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 575-578, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
42 | Kazimierz Wiatr, Ernest Jamro |
Implementation of Multipliers in FPGA Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 415-420, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
42 | George Havas, Jean-Pierre Seifert |
The Complexity of the Extended GCD Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 1999, 24th International Symposium, MFCS'99, Szklarska Poreba, Poland, September 6-10, 1999, Proceedings, pp. 103-113, 1999, Springer, 3-540-66408-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
computational problems of diophantine equations, extended gcd computations, Approximation algorithms, NP-hardness, probabilistically checkable proofs, interactive proof systems |
41 | Gang Zhou, Harald Michalik, László Hinsenkamp |
Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 193-203, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
AES-GCM, pipelined Karatsuba multiplier, FPGAs, finite field arithmetic |
41 | Abdulah Abdulah Zadeh |
A Novel Approach for Multiplication over GF(2m) in Polynomial Basis Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: Proceedings of the The Third International Conference on Availability, Reliability and Security, ARES 2008, March 4-7, 2008, Technical University of Catalonia, Barcelona , Spain, pp. 1346-1351, 2008, IEEE Computer Society, 978-0-7695-3102-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Hybrid multiplier, GF, Polynomial (Standard) Basis, Finite Field |
41 | Johann Großschädl |
High-Speed RSA Hardware Based on Barret's Modular Reduction Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2000, Second International Workshop, Worcester, MA, USA, August 17-18, 2000, Proceedings, pp. 191-203, 2000, Springer, 3-540-41455-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
RSA algorithm, partial parallel multiplier, full-custom VLSI design, pipelining, Public-key cryptography, modular arithmetic |
41 | David M. Mandelbaum, Stefanie G. Mandelbaum |
A Fast, Efficient Parallel-Acting Method of Generating Functions Defined by Power Series, Including Logarithm, Exponential, and Sine, Cosine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(1), pp. 33-45, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multinomials, multiplier tree, partitions, functions, Arrays, exponential, logarithm, sine, power series, cosine |
40 | Arash Reyhani-Masoleh |
A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2008, 10th International Workshop, Washington, D.C., USA, August 10-13, 2008. Proceedings, pp. 300-314, 2008, Springer, 978-3-540-85052-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Finite or Galois field, Mastrovito multiplier, polynomial basis, bit-serial multiplier |
40 | David W. Matula, Asger Munk Nielsen |
Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 140-147, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
pipelined packet forwarding floating point, packet forwarding floating point format, rounder design, packet forwarding format, standard binary IEEE 754 floating point format, multiplication algorithms, ALU pipeline paradigm, data hazards, pipelined floating point operations, execution phases, multiplier packet forwarding pipelines, execution phase, logic levels, multiplier pipelines, forwarding pipelines, IEEE 754 binary floating point compatibility, pipeline arithmetic, data dependent operations |
39 | Md. Ibrahim Faisal, Magdy A. Bayoumi |
A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1460-1463, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Tzu-Yuan Kuo, Jinn-Shyan Wang |
A low-voltage latch-adder based tree multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 804-807, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Chang Sun, Hongjun Wang 0004, Hua Li, Tai-Hoon Kim |
Perceptually Adaptive Lagrange Multiplier for Rate-Distortion Optimization in H.264. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FGCN (1) ![In: Future Generation Communication and Networking, FGCN 2007, Ramada Plaza Jeju, Jeju-Island, Korea, December 6-8, 2007, Proceedings, pp. 459-463, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Yunhua Wang, Linda DeBrunner, Dayong Zhou, Victor E. DeBrunner |
A Multiplier Structure Based on a Novel Real-time CSD Recoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3195-3198, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Ramachandruni Venkata Kamala, M. Sudhakar, M. B. Srinivas |
An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 155-159, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Zih-Heng Chen, Ming-Haw Jing, Trieu-Kien Truong, Yaotsu Chang |
Another Look at the Sequential Multiplier over Normal Bases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1799-1802, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Suryanarayana Tatapudi, José G. Delgado-Frias |
A High Performance Hybrid Wave-Pipelined Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 282-283, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Justin Hensley, Anselmo Lastra, Montek Singh |
A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 128-137, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Jieh-Hwang Yen, Lan-Rong Dung, Chi-Yuan Shen |
Design of power-aware multiplier with graceful quality-power trade-offs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1642-1645, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang |
A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1174-1177, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Soonhak Kwon |
A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain, pp. 196-, 2003, IEEE Computer Society, 0-7695-1894-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
39 | Minyue Fu 0001, Soura Dasgupta, Yeng Chai Soh |
Integral quadratic constraint approach vs. multiplier approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICARCV ![In: Seventh International Conference on Control, Automation, Robotics and Vision, ICARCV 2002, Singapore, 2-5 December 2002, Proceedings, pp. 144-149, 2002, IEEE, 981-04-8364-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
39 | Kiwon Choi, Minkyu Song |
Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 701-704, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Lijun Gao, Keshab K. Parhi |
Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 574-577, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Mohammad K. Ibrahim, Abulaziz Almulhem |
Bit-level pipelined digit serial GF(2m) multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 586-589, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Hyun-Sung Kim 0001, Kee-Young Yoo |
Area Efficient Exponentiation Using Modular Multiplier/Squarer in GF(2m. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COCOON ![In: Computing and Combinatorics, 7th Annual International Conference, COCOON 2001, Guilin, China, August 20-23, 2001, Proceedings, pp. 262-267, 2001, Springer, 3-540-42494-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Shyh-Jye Jou, Hui-Hsuan Wang |
Fixed-Width Multiplier for DSP Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 318-322, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
39 | Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian |
An Effective BIST Architecture for Fast Multiplier Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 117-121, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
39 | Chi-Hung Lin, Mohammed Ismail 0001 |
A 1.8V High Dynamic-Range CMOS High-Speed Four Quadrant Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 372-375, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
39 | Deepak Kapur, Mahadevan Subramaniam |
Mechanically Verifying a Family of Multiplier Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 8th International Conference, CAV '96, New Brunswick, NJ, USA, July 31 - August 3, 1996, Proceedings, pp. 135-146, 1996, Springer, 3-540-61474-5. The full citation details ...](Pics/full.jpeg) |
1996 |
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