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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 375 occurrences of 273 keywords
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Results
Found 367 publication records. Showing 367 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
134 | Farooq Butt |
Porting the mcc PowerPC C/C++ Compiler into an Interactive Development Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 31(8), pp. 64-73, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
C++ |
101 | Charles D. Norton |
The International Workshop on Parallel C++ (IWPC++), Kanazawa, Ishikawa Prefecture, Japan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 31(8), pp. 28-30, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
C++ |
85 | Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden |
Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 738-743, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reliability, PowerPC, PowerPC, IR-drop, power distribution network |
85 | Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington |
A high performance bus and cache controller for PowerPC multiprocessing systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 204-211, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor |
79 | Brian F. Veale, John K. Antonio, Monte P. Tull, Sean A. Jones |
Selection of instruction set extensions for an FPGA embedded processor core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
76 | Charles P. Roth, Frank E. Levine, Edward H. Welbon |
Performance monitoring on the PowerPC 604 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 212-215, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PowerPC 604 microprocessor, multichip processors, Groupe Bull, performance evaluation, integrated circuit testing, workstations, performance monitoring, microprocessor chips, PCs, Microsoft, IBM, computer testing, Apple, Motorola |
76 | Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore |
The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 196-203, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PowerPC 603e microprocessor, low-power superscalar microprocessor, portable products, on-chip instruction, cache associativity, bus modes, 120 SPECint92, 105 SPECfp92, die size, software controllable power-down modes, power saving capability, 16 Kbyte, performance evaluation, performance, computer architecture, system design, power consumption, data cache, cache storage, microprocessor chips, frequency, system buses, portable computers, portable computers, transistors, 100 MHz |
76 | Trung A. Diep, Christopher Nelson, John Paul Shen |
Performance Evaluation of the PowerPC 620 Microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 163-175, 1995, ACM, 0-89791-698-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PowerPC |
68 | Harold W. Cain, Kevin M. Lepak, Mikko H. Lipasti |
A dynamic binary translation approach to architectural simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 29(1), pp. 27-36, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
65 | Peter M. Behr, S. Pletner, Angela C. Sodan |
PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 277-286, 2000, IEEE Computer Society, 0-7695-0550-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
PowerPC MPC620, two-way nodes, crossbar interconnection network, distributed memory architecture |
65 | Farooq Butt |
Rapid Development of a Source-Level Debugger for PowerPC Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 29(12), pp. 73-77, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
PowerPC |
55 | Mahdi Fazeli, Reza Farivar 0003, Seyed Ghassem Miremadi |
Error Detection Enhancement in PowerPC Architecture-based Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 21-33, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Physical fault injection, Power supply disturbances, Concurrent error detection, Control flow checking |
55 | Mahdi Fazeli, Reza Farivar 0003, Seyed Ghassem Miremadi |
A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 266-274, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
55 | Patrick J. Bohrer, James L. Peterson, E. N. Elnozahy, Ramakrishnan Rajamony, Ahmed Gheith, Ronald L. Rockhold, Charles Lefurgy, Hazim Shafi, Tarun Nakra, Richard O. Simpson, Evan Speight, Kartik Sudeep, Eric Van Hensbergen, Lixin Zhang 0002 |
Mambo: a full system simulator for the PowerPC architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS Perform. Evaluation Rev. ![In: SIGMETRICS Perform. Evaluation Rev. 31(4), pp. 8-12, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
53 | Allon Adir, Hagit Attiya, Gil Shurek |
Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(5), pp. 502-515, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
PowerPC architecture, synchronization instructions, models, specification, consistency, Shared memory, multiprocessor systems, out-of-order execution |
53 | Shantanu Ganguly, Shervin Hojat |
Clock distribution design and verification for PowerPC microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 58-61, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PowerPC |
53 | Julie Shipnes, Mike Philip |
A Modular Approach to Motorola PowerPC Compilers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 37(6), pp. 56-62, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
PowerPC |
44 | Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich |
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 3-8, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Microprocessor, Delay Testing |
44 | Martin S. Schmookler, Michael Putrino, Anh Mather, Jon Tyler, Huy Van Nguyen, Charles Roth, Mukesh Sharma, Mydung N. Pham, Jeff Lent |
A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia, pp. 12-, 1999, IEEE Computer Society, 0-7695-0116-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
44 | Mario Porrmann, Ulrich Rückert 0001, Karl Michael Marks, Jörg Landmann |
HiBRIC-MEM, a Memory Controller for PowerPC Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 653-657, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
43 | M. Armstead, Michael Cogswell, S. Halverson, T. Musta |
PowerPC Visual Simulator: Peeking Under the Hood of the PowerPC Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994, pp. 413-418, 1994, IEEE Computer Society, 0-8186-6565-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
42 | Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy |
Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 534-537, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
PowerPC |
42 | Anthony Correale Jr. |
Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPD ![In: Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995, pp. 75-80, 1995, ACM, 0-89791-744-8. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PowerPC |
34 | Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis |
The Molen compiler for reconfigurable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 6(1), pp. 6, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, reconfigurable computing, Instruction scheduling |
34 | Pedro Trancoso |
Dynamic Split: Flexible Border Between Instruction and Data Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 476-483, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Valentina Salapura, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, Dong Chen 0005, Paul Coteus, Alan Gara, Mark Giampapa, Michael Gschwind, Manish Gupta 0002, Shawn Hall, Ruud A. Haring, Philip Heidelberger, Dirk Hoenicke, Gerard V. Kopcsay, Martin Ohmacht, Rick A. Rand, Todd Takken, Pavlos Vranas |
Power and performance optimization at the system level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 125-132, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
BlueGene/L, application performance analysis, application scaling in multiprocessor systems, power/performance efficient systems, power/performance tradeos in systems, chip multiprocessors, supercomputers |
34 | Amir Hekmatpour, James Coulter |
Coverage-Directed Management and Optimization of Random Functional Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 148-155, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Gordon J. Brebner |
Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings, pp. 35-44, 2002, IEEE Computer Society, 0-7695-1801-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Pedro Furtado 0001, Henrique Madeira |
Fault Injection Evaluation of Assigned Signatures in a RISC Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-2, Second European Dependable Computing Conference, Taormina, Italy, October 2-4, 1996, Proceedings, pp. 55-72, 1996, Springer, 3-540-61772-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
34 | Bryan Black, Andrew S. Huang, Mikko H. Lipasti, John Paul Shen |
Can Trace-Driven Simulators Accurately Predict Superscalar Performance? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 478-485, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
33 | Magnus O. Myreen, Michael J. C. Gordon |
Verified LISP Implementations on ARM, x86 and PowerPC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Theorem Proving in Higher Order Logics, 22nd International Conference, TPHOLs 2009, Munich, Germany, August 17-20, 2009. Proceedings, pp. 359-374, 2009, Springer, 978-3-642-03358-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Joon Huang Chuah, Joel Knight |
VertiCal, a Universal Calibration System for eSys High Performance 32-Bit PowerPC Microcontrollers; Test Challenges & Solution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 64-67, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova |
Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA, pp. 111-118, 2005, IEEE Computer Society, 0-7695-2627-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Weining Gu, Zbigniew Kalbarczyk, Ravishankar K. Iyer |
Error Sensitivity of the Linux Kernel Executing on PowerPC G4 and Pentium 4 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June - 1 July 2004, Florence, Italy, Proceedings, pp. 887-, 2004, IEEE Computer Society, 0-7695-2052-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis |
The PowerPC Backend Molen Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 434-443, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina |
Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 574-583, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham |
Validating PowerPC Microprocessor Custom Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 17(4), pp. 61-76, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
33 | Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina |
At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 3-8, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
delay testing, at-speed testing, microprocessor testing |
33 | Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham |
Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 9-14, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Simulation, Validation, Memories, Assertions, Symbolic |
33 | Alan J. Drake, Todd D. Basso, Spencer M. Gold, Keith L. Kraver, Phiroze N. Parakh, Claude R. Gauthier, P. Sean Stetson, Richard B. Brown |
CGaAs PowerPC FXU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 730-735, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
design methodology, microprocessors, testing methodology, Gallium Arsenide |
33 | L. Robinson, G. Whisenhunt |
A PowerPC platform full system simulation-from the MOOSE up. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: Proceedings of the IEEE International Performance Computing and Communications Conference, IPCCC 1999, Phoenix/Scottsdale, Arizona, USA, 10-12 February 1999, pp. 458, 1999, IEEE, 0-7803-5258-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Claude Limousin, Alexis Vartanian, Jean-Luc Béchennec |
PopSPY: A PowerPC Instrumentation Tool for Multiprocessor Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31 - September 3, 1999, Proceedings, pp. 262-265, 1999, Springer, 3-540-66443-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Li-C. Wang, Magdy S. Abadir, Jing Zeng |
On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(4), pp. 524-532, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
assertion test generation, design error model, validation, ATPG, logic verification, symbolic trajectory evaluation |
33 | Li-C. Wang, Magdy S. Abadir, Jing Zeng |
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 273-277, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Design Error Models, Verification, Design Validation |
33 | Rajesh Raina, Robert F. Molyneaux |
Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 222-229, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
High-Level Design Validation, Silicon Validation, Pseudo-Random Testing, Microprocessor Testing |
33 | Craig Hunter, Justin Gaither |
Design and implementation of the "G2" PowerPC 603e-embedded microprocessor core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 473-479, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
33 | Lucas Aaron Womack |
A Study of Virtual Memory MTU Reassembly within the PowerPC Architectur. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: MASCOTS 1997, Proceedings of the Fifth International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, January 12-15, 1997 Haifa, Israel, pp. 81-90, 1997, IEEE Computer Society, 0-8186-7758-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
33 | Sonya Gary, Pete Ippolito, Gianfranco Gerosa, Carl Dietz, Jim Eno, Hector Sanchez |
PowerPC 603, A Microprocessor for Portable Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 11(4), pp. 14-23, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
32 | Alejandro Rico, Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, Chen-Yong Cher, Pradip Bose |
Performance and power evaluation of an in-line accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 81-82, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
vmx, accelerator, powerpc, simd |
32 | Joe Gebis, David A. Patterson 0001 |
Embracing and Extending 20th-Century Instruction Set Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 40(4), pp. 68-75, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
instruction set architectures, PowerPC, SIMD processors, vector architecture |
32 | Jeff H. Derby, Robert K. Montoye, José E. Moreira |
VICTORIA: VMX indirect compute technology oriented towards in-line acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 303-312, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
VMX, SIMD, accelerators, powerPC |
32 | Kazunori Ogata, Hideaki Komatsu, Toshio Nakatani |
Bytecode fetch optimization for a Java interpreter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), San Jose, California, USA, October 5-9, 2002., pp. 58-67, 2002, ACM Press, 1-58113-574-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
pipelined interpreter, stack caching, Java, performance, superscalar processor, PowerPC, bytecode interpreter |
32 | Dean E. Dauger, Viktor K. Decyk |
Numerically-Intensive "Plug-and-Play" Parallel Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2001 IEEE International Conference on Cluster Computing (CLUSTER 2001), 8-11 October 2001, Newport Beach, CA, USA, pp. 75, 2001, IEEE Computer Society, 0-7695-1116-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
AppleSeed, plug and play, MacMPI, Pooch, easy, parallel computing, GUI, MPI, cluster computing, Unix, technology transfer, Macintosh, PowerPC, ease of use, Apple, Mac, plasma physics, AltiVec |
32 | Yossi Malka, Avi Ziv |
Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 644-649, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
21264, coverage anaysis, verification, architecture, validation, microprocessor, PowerPC, pseudo-random, Alpha |
32 | Thomas H. Einstein |
Mercury Computer Systems' modular heterogeneous RACE(R) multicomputer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Heterogeneous Computing Workshop ![In: 6th Heterogeneous Computing Workshop, HCW 1997, Geneva, Switzerland, April 1, 1997, pp. 60-, 1997, IEEE Computer Society, 0-8186-7879-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Mercury Computer Systems, modular heterogeneous RACE multicomputer, heterogeneous multicomputer, Analog Devices, SHARC 21060, Apple PowerPC 603p, optimal processor, physical processing density, heterogeneity, distributed memory systems, programmability, IBM, hardware cost, Motorola |
32 | Bruce L. Jacob, Trevor N. Mudge |
Software-Managed Address Translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997, pp. 156-167, 1997, IEEE Computer Society, 0-8186-7764-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
software-managed address translation, memory management design, high clock-rate PowerPC implementation, OSF/1, superpages, sub-page protection, sparse address spaces, shared memory, storage management, Mach |
32 | Chi-Hung Chi, Siu-Chung Lau |
Reducing data access penalty using intelligent opcode-driven cache prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 512-517, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
data access penalty, intelligent opcode-driven, LOAD-UPDATE, LOAD-MODIFY, IBM PowerPC, HP Precision Architecture, intelligent data prefetching, instruction decode unit, storage management, data cache, cache storage, cache prefetching |
23 | Manoel T. F. Cunha, Jose C. F. Telles, Alvaro L. G. A. Coutinho |
On the Implementation of Boundary Element Engineering Codes on the Cell Broadband Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VECPAR ![In: High Performance Computing for Computational Science - VECPAR 2008, 8th International Conference, Toulouse, France, June 24-27, 2008. Revised Selected Papers, pp. 490-504, 2008, Springer, 978-3-540-92858-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Parallel Programming, SIMD, Vectorization, Cell Broadband Engine, Boundary Element Method, Boundary Elements |
23 | Hiroshi Inoue, Takao Moriyama, Hideaki Komatsu, Toshio Nakatani |
AA-Sort: A New Parallel Sorting Algorithm for Multi-Core SIMD Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 189-198, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Sándor Héman, Niels Nes, Marcin Zukowski, Peter A. Boncz |
Vectorized data processing on the cell broadband engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DaMoN ![In: Workshop on Data Management on New Hardware, DaMoN 2007, Beijing, China, June 15, 2007, pp. 4, 2007, ACM, 978-1-59593-772-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Marc Berndl, Benjamin Vitale, Mathew Zaleski, Angela Demke Brown |
Context Threading: A Flexible and Efficient Dispatch Technique for Virtual Machine Interpreters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 20-23 March 2005, San Jose, CA, USA, pp. 15-26, 2005, IEEE Computer Society, 0-7695-2298-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Akihiko Miyoshi, Charles Lefurgy, Eric Van Hensbergen, Ramakrishnan Rajamony, Raj Rajkumar |
Critical power slope: understanding the runtime effects of frequency scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 16th international conference on Supercomputing, ICS 2002, New York City, NY, USA, June 22-26, 2002, pp. 35-44, 2002, ACM, 1-58113-483-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
energy aware computing |
23 | M. D. Bennett, Neil C. Audsley |
Predictable and Efficient Virtual Addressing for Safety-Critical Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECRTS ![In: 13th Euromicro Conference on Real-Time Systems (ECRTS 2001), 13-15 June 2001, Delft, The Netherlands, Proceedings, pp. 183-190, 2001, IEEE Computer Society, 0-7695-1221-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Vivek Sarkar, Mauricio J. Serrano, Barbara B. Simons |
Register-sensitive selection, duplication, and sequencing of instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 15th international conference on Supercomputing, ICS 2001, Sorrento, Napoli, Italy, June 16-21, 2001, pp. 277-288, 2001, ACM, 1-58113-410-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Li-C. Wang, Magdy S. Abadir |
On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 121-130, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
custom circuits, high level circuit extraction, ATPG, DFT, time-to-market |
23 | Li-C. Wang, Magdy S. Abadir |
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(1-2), pp. 191-205, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
assertion test generation, assertion, array, design error, logic verification, symbolic trajectory evaluation |
23 | Armin Biere, Edmund M. Clarke, Richard Raimi, Yunshan Zhu |
Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 11th International Conference, CAV '99, Trento, Italy, July 6-10, 1999, Proceedings, pp. 60-71, 1999, Springer, 3-540-66202-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Esther Stümpel, Michael Thies, Uwe Kastens |
VLIW Compilation Techniques for Superscalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 7th International Conference, CC'98, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS'98, Lisbon, Portugal, March 28 - April 4, 1998, Proceedings, pp. 234-248, 1998, Springer, 3-540-64304-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
23 | E. Kofi Vida-Torku, George Joos |
Designing for scan test of high performance embedded memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 101-108, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Kun Cheng, Weiyue Liu, Qi Shen, Shengkai Liao |
Design and Implementation of High-throughput PCIe with DMA Architecture between FPGA and PowerPC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1809.07702, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
22 | Rui Zhou 0005, Qingguo Zhou, Yong Sheng, Kuan-Ching Li |
Erratum to: XtratuM/PPC: a hypervisor for partitioned system on PowerPC processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 63(2), pp. 611, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Rui Zhou 0005, Qingguo Zhou, Yong Sheng, Kuan-Ching Li |
XtratuM/PPC: a hypervisor for partitioned system on PowerPC processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 63(2), pp. 593-610, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Tareq M. Malas, Aron J. Ahmadia, Jed Brown, John A. Gunnels, David E. Keyes |
Optimizing the performance of streaming numerical kernels on the IBM Blue Gene/P PowerPC 450 processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Comput. Appl. ![In: Int. J. High Perform. Comput. Appl. 27(2), pp. 193-209, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Radisav Cojbasic, Omer Cogal, Pascal Andreas Meinerzhagen, Christian Senning, Conor Slater, Thomas Maeder, Andreas Burg, Yusuf Leblebici |
FireBird: PowerPC e200 based SoC for high temperature operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013, San Jose, CA, USA, September 22-25, 2013, pp. 1-4, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Tareq M. Malas, Aron J. Ahmadia, Jed Brown, John A. Gunnels, David E. Keyes |
Optimizing the Performance of Streaming Numerical Kernels on the IBM Blue Gene/P PowerPC 450 Processor ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1201.3496, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
22 | |
IBM PowerPC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Parallel Computing ![In: Encyclopedia of Parallel Computing, pp. 907, 2011, Springer, 978-0-387-09765-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Mark Bucciero, John Paul Walters, Roger Moussalli, Shanyuan Gao, Matthew French |
The PowerPC 405 Memory Sentinel and Injection System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011, Salt Lake City, Utah, USA, 1-3 May 2011, pp. 154-161, 2011, IEEE Computer Society, 978-0-7695-4301-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Rod Blaine Foist, Cristian Grecu, André Ivanov, Robin Turner |
An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Educ. ![In: IEEE Trans. Educ. 51(3), pp. 312-318, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Rod Blaine Foist, André Ivanov, Robin Turner |
An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE '07, San Diego, CA, USA, June 3-4, 2007, pp. 127-128, 2007, IEEE Computer Society, 0-7695-2849-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Stephen Barrett, Julie Spratt, Ralph Depping, Ramachandran Ranganathan |
PowerPC Kernel Implementation for GSM Radio Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2007 International Conference on Embedded Systems & Applications, USA 2007, June 25-28, 2007, Las Vegas, Nevada, USA, pp. 98-106, 2007, CSREA Press, 1-60132-052-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
22 | Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John, Jeff Stuecheli, John Griswell, Paul Tu, Louis Capps, Anton Blanchard, Ravel Thai |
Automatic testcase synthesis and performance model validation for high performance PowerPC processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2006 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2006, March 19-21, 2006, Austin, Texas, USA, Proceedings, pp. 154-165, 2006, IEEE Computer Society, 1-4244-0186-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Arvind |
UNUM: A Tinker-Toy Approach to Building Multicore PowerPC Microarchitectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 39, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Nagu R. Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing-Chao Lin |
Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 10(2-3), pp. 105-125, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Charles D. Wait |
IBM PowerPC 440 FPU with complex-arithmetic extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 49(2-3), pp. 249-254, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Himyanshu Anand, Jayanta Bhadra, Alper Sen 0001, Magdy S. Abadir, Kenneth G. Davis |
Establishing latch correspondence for embedded circuits of PowerPC microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30 - December 2, 2005, pp. 37-44, 2005, IEEE Computer Society, 0-7803-9571-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Waleed Al-Assadi, Thomas Dick |
Design for Test Methodology for the IBM PowerPC 440 Embedded Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005, pp. 109-114, 2005, CSREA Press, 1-932415-54-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
22 | Shivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman |
Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 54-58, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Nandu Tendolkar, Dawit Belete, Ashutosh Razdan, Hereman Reyes, Bill Schwarz, Marie Sullivan |
Test methodology for Freescale's high performance e600 core based on PowerPC© instruction set architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pp. 9, 2005, IEEE Computer Society, 0-7803-9038-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Gerard Boudon, Alan Wall, Joe Foster, Barry Wolford, John Fakiris |
A 800 MHz PowerPC SOC with PCI-X DDR266, DDRII-667, and RAID assist. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Proceedings 2004 IEEE International SOC Conference, September 12-15, 2004, Hilton Santa Clara, CA, USA, pp. 183-186, 2004, IEEE, 0-7803-8445-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | |
Micro News: Moving into the 90-nm chip market; PowerPC runs at up to 2.5 GHz. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 23(2), pp. 6, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Kevin J. Nowka, Gary D. Carpenter, Bishop Brock |
The design and application of the PowerPC 405LP energy-efficient system-on-a-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 47(5-6), pp. 631-640, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Hazim Shafi, Patrick J. Bohrer, James Phelan, Cosmin Rusu, James L. Peterson |
Design and validation of a performance and power simulator for PowerPC systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 47(5-6), pp. 641-652, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop Brock, Koji I. Ishii, Tuyet Nguyen, Jeffrey L. Burns |
A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(11), pp. 1441-1447, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Richard Raimi, James Lear |
Silicon Debug of a PowerPC[tm] Microprocessor Using Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 21(1), pp. 79-94, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Grieg, Cedric Collins, Troy Benjegerdes, Brett M. Bode |
Linux Clustering using the PowerPC G4 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IASTED PDCS ![In: International Conference on Parallel and Distributed Computing Systems, PDCS 2002, November 4-6, 2002, Cambridge, USA, pp. 521-526, 2002, IASTED/ACTA Press, 0-88986-366-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
22 | Paul Kartschoke, Shervin Hojat |
Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 65-70, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Gilbert Vandling |
Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for Nintendo. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001, pp. 593-599, 2001, IEEE Computer Society, 0-7803-7169-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Keith Diefendorff, Pradeep K. Dubey, Ron Hochsprung, Hunter Scales |
AltiVec Extension to PowerPC Accelerates Media Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 20(2), pp. 85-95, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Frank P. O'Connell, Steven W. White |
POWER3: The next generation of PowerPC processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 44(6), pp. 873-884, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | John M. Borkenhagen, Richard J. Eickemeyer, Ronald N. Kalla, Steven R. Kunkel |
A multithreaded PowerPC processor for commercial servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 44(6), pp. 885-898, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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